3D IC Technology – OSAT Perspective

Min Yoo in Amkor Technology Taiwan

Status Update: Amkor’s

2.5D and 3D TSV Development

Agenda

• Drivers & Timing

• Key Product Development Activity

• Production Challenges

Amkor TSV Platform Roadmap

“Drivers and Timing”

FCBGA – Migration to TSV

• Die-to-die connections at on-chip speeds and power.

• Allows multiple process nodes in a single silicon package.

• Only use 28nm for functions that need it.

• Partition large logic blocks into smaller, higher yield sub-blocks.

– Much lower cost 28nm products

– Less sensitivity to 28nm process issues

Logic 1

Logic 1

Logic 1

Logic 2

Cache

Logic 2

Analog Logic

1

Logic

2

Cache

Analog

Multi-Die

Interposer

SOC

Traditional

SOC

Logic

Logic

Logic

Logic

Logic

New !!

Multi-Die

Interposer

SOC

Monolithic

FPGA

SOC

TSV Production Intercepts

– Amkor View

All Products planning on 22/20nm in future platforms for TSV

2012 2013 2014 2015 2011

Production Since 2010

Interposer Required

Interp. Req’d

Si InterpT + DDRT + Logic

Apps ProcessorT + DDR

Memory (DDRT)

Si InterposerT + Logic

Logic – Backside Metal

GPU, CPU

Smart Phone / Tablet

ASIC, FPGA

Power Amp.

MEMsT

Mobile Devices

Server, Wide I/O

Die with SV indicated by = T

Key TSV Product &

Development Activity

TSV Bearing Wafer Supply Chain

Logistics

TSV Product Challenges

Substrate

Interposer

Silicon

Micro Copper Pillar Bumping

Micro Joining

Underfill

Subassembly &

Package Warpage

Thermal

Thin Wafer Handling

Interposer Thinning

Amkor Capability

2.5D FPGA Module

µBumping of TSV Devices

• Formation of Back-side / Front-side µBumps

– All development and qualifications at 40µm pitch today

– 30µm pitch demonstrated

– 20µm pitch requires development (registration) & new photoresist (resolution)

Wafer Finishing of TSV Devices

• 200/300mm Thin Wafer Support in ATK4

– Cleared to bond up to 40um front side bumps ; excellent TTV at ~2µm

Wafer Finishing of TSV Devices

• TSV Reveal, Isolation and Passivation

– Key : No damage to silicon, liner or tip

– Critical : No copper residue on surface

Silicon Etch Recess

Ni – Au on Copper Via

Grind – Expose TSV

Completed TSV Backside

Structure

SiN

TEOS

Oxide liner

Wafer Finishing of TSV Devices

• 200/300mm Thin Wafer Handling – De-bonding

Assembly (BEOL)

Joint technology • Compression technology primarily used with TSV pitches ~ 40µm

• Mass reflow begins to reach limit at 40µm pitch due to shorting potential

• Warpage of substrate under mass reflow limits ability to reduce TSV pitch

50um 40um 30um

20um

Bonding

Method

Reflow Reflow/

Compression

Compression Compression

Bump

Structure

Solder Cu-Solder Cu-Solder

2010 2011 2012 2013

Cu-Solder

Process

Chip to Chip Chip to Wafer

Bump Pitch

Chip to Substrate ( Organic / Si interposer)

Good Registration

Substrate + Logic + Memory

Interposer Only

80µm

Bump

Wide I/O MPGA

APU

Cross Section of Memory on Logic

• Thermo-Compression Bond + Non Conductive Paste (NCP)

– Thin die handling capability to 50µm

– Material dispense critical

Pitch ≥ 40µm today ; 30µm 2012

Pillar to Ni-Au Pad as standard

Chip

Cu Pillar with SnAg µBumps

40µm today

Courtesy of Xilinx, TSMC, Amkor

Assembly of TSV Devices

• Assembly Experience on Silicon Interposer

• Substrate body size ranges from 35mm up to 55mm

• Interposer thickness as thin as 60um, but typically at100um

Pitch ≥ 40µm today ; 30µm 2012 80µm Tall Plated SnAg or SnPb Bumps

Pitch ≥ 150µm today ; ≥ 130µm 2012

Chi

p

Chi

p

Many Assembly Flows – Requires

Flexibility

Many Options – Amkor Engaged in Each

Chip on Chip “CoC-oS”

Chip on Wafer “CoW-oS”

Chip on Substrate “Co-CoS”

TSV Reliability Data – General

• ASIC (die to die = face to face)

• Multiple Die on Interposer ; 100µm thick, 10µm TSV at 210µm pitch

• Logic at 40µm pitch µbump with 25µm dia. ; over 200k micro-bumps

• Passed Level 4 MRT ; TC Condition B 1000 cycles ; HTS 1000 hrs and

HAST 110C, 85% RH, 500 Hours

• Handset – 45nm Baseband (die to die = face to back)

• Memory ~ 100µm thick

• Logic ~ 50µm thick with 10µm TSV at 40um pitch ; either peripheral or area

array bump pitch to substrate

• Passed MRT L3 260’C (3x reflow) ; T/C-B 1000 cycles ; HTS 1000 hrs

TSV Lessons Learned

• Design Rules and Standards

• Simulation, Thermal, Mechanical, Tolerance

• Test and FA Methods

• Adaptive assembly methods

• Feed forward product characteristics

Design Rules and Standards

• Successful deployment of 2.5D and 3D

TSV requires careful definition of design rules.

• International standards will help reduce

variability and complexity.

Simulation

• Complexity forces computational solutions for

predicting performance and yield.

• Better specification of material properties

is needed.

Adaptive Assembly Methods

• For greater process latitude, process

equipment must adapt to the measured

characteristics of incoming material.

– For example:

• Warpage

• Planarity

• TTV

TSV Must Succeed or We Face

This: