3d ic readiness - global semiconductor alliance
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3D IC Readiness
GSA 3D IC Workshop
October 22, 2014
Charles Woychik
Invensas Corporation
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Outline
• Background
• Assessing Readiness
• Status and Summary
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Outline
• Background
• Assessing Readiness
• Status and Summary
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What Is 3D Packaging?
This Is... …But So Is This.
The level of Hardware Engineering now required to build the miniaturized and wearable devices of tomorrow, is Package Engineering (what Invensas calls Interconnectology).
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• Formation: Founded in 2011 as a wholly owned subsidiary of Tessera
Technologies, Inc. (Nasdaq:TSRA)
• Goal: Develop and commercialize breakthrough semiconductor interconnect
solutions and IP in Mobile, Storage and Cons. Electronics.
• Core Focus: “Interconnectology”: adv. interconnect, semiconductor
packaging, memory circuitry, modules, 3D TSV architecture.
• Company: 50+ Employees (1/3 PhD). Headquarters: San Jose, CA.
• IP: ~1300 patents and applications.
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Invensas Technology Roadmap
BVA for Fine Pitch PoP
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Invensas 3DIC Capabilities
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Assembly Prototyping Line Capabilities
Lead Free Certified 10 Heat 3 Cool Zones CDA or N2 Cover Gas
Reflow
Centrifugal Action Zero Discharge Ionic Contamination Tester*
Flux Clean
Jet Dispense Volumetric Control Repeatability 25µm 350 x 350mm Work Area
Underfill
Batch Ovens Convection Vacuum Inert Gas Flow (N2)
Cure
Transfer Mold Compression mold capable Film capable Vacuum assist
Encapsulation
Auto alignment Wafer level printing Proflow for fine features ProActive (Ultrasonic squeegee)
D/A Print
Gold/Copper wire-bonder Fine-pitch Low Loop
Wire Bond
FC Bonder Accuracy ±2 µm Flux Dip, TCB, Dispense C2C, C2W High-force, Ultra Low-force
Die Placement
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JEOL 6610LV Scanning Electron Microscopes
Functions: • High resolution imaging of the sample surface topography and crystallographic structure.
Sonoscan Ultrasonic Imaging
Functions: • Ultrasonic imaging • Efficient detection of voids (as thin as 0.1um)
Resolution: • X-y resolution of 4-6 um, frequencies and materials depended.
Dage XD7600NT 2D X-ray System
Functions: • High resolution 2D x-ray inspection
Functions: •Temperature Cycling (Single Zone) • IC packages-JEDEC Standard JESD22-A104 • Optical-JEDEC Standard JESD22-A104G
Temperature Cycling Chamber (Espec)
Temperature & Humidity Chamber (Espec)
Functions: • Bias/unbiased Humidity Chamber • IC packages-JEDEC Standard JESD22-A101 • Optical- JEDEC Standard J-STD-020 • Optical-Cyclic Damp Heat; SMIA Standard 4.2.2.2-B2.2
FA / Reliability Capabilities
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2.5D Test Vehicles at Invensas
TV3Interposer Size (mm2) 27x19TSV Dimensions (um) 10x100# of TSVs 8615FC Bump Pitch (um) 180/250# of FC bumps 7076
Top Die Size (mm2) 10x12# of Top Dies/Interposer 2Min Micro-bump Pitch (um) 60# of Micro-bumps/top die 7744Bond Metallurgy Solder capped Cu pillar
Chip - Chip Assembly centric flow
TV4Interposer Size (mm2) 24x24TSV Dimensions (um) 5x50# of TSVs 4000FC Bump Pitch (um) 180/250# of FC bumps 8872
Top Die Size (mm2) 9x9# of Top Dies/Interposer 4Min Micro-bump Pitch (um) 30# of Micro-bumps/top die 32098Bond Metallurgy Cu-Cu direct bond
Chip – Wafer fab centric flow
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Outline
• Background
• Assessing Readiness
• Status and Summary
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Typical Technology Transitions
Acceptance of next-generation technologies is catalyzed
by the convergence of 5 key factors:
1. Cost/benefit ratio of incumbent technology becomes minimal
2. New technology moves beyond feasibility stage
3. Industry leaders come to consensus on timetable
4. Willingness to invest
5. Robust ecosystem is ready
IMAPS Device Packaging 2013
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2.5D or 3DIC Readiness? Getting the Nomenclature Right
3D Integration
3D SIC Integration 3D MIC Integration
Silicon Interposers
Memory Stacking
Logic + Memory Stacking
3D Monolithic Silicon
V. Pavlidis (EPFL)
Passive Functional Functional Functional
Logic Partitioning, Master-Slave Memory, Wide I/O + Logic, Cache off logic
Master-Slave Memory, Wide I/O + Logic
IMAPS Device Packaging 2013
Reference: John Lau
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TSV Interposer Readiness – Invensas’ Perspective
TSV Etch
TSV Dielectric Liner
TSV Barrier
TSV Fill (plating)
TopSide RDL
Topside Passivation\Finish
Temporary Bond
Backgrind\Reveal
Backside Low Temp Oxide
Backside CMP
Backside Metal/Passivation
Wafer Bump/ Debond/ Dice
Top Side (ubump) Back Side (C4)
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Temporary Bonding Issues
• Increased wafer handling and yield issues • Temporary bonding limits subsequent processing temp to <200°C
• Conventional oxides need higher growth temperature • Conventional polyimides cure at higher temperature
• Issue of thickness scalability Low value add; no improvement in material properties in years Need alternatives to temporary bonding
Front side processing Temporary bonding
Thinning & backside processing (≤ 200 °C) De-bonding
Passivation (PI)
Insulation
Cu (TSV/RDL)
Si
Carrier wafer
Temporary bond
Si
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Alternate Thin Wafer Handling Approaches
Approaches that…
- Eliminate Temporary Bond/Debond
- Permit scaling of wafer thickness
- Minimize warpage
Examples:
- Chip to wafer bonding with wafer level compression molding
- Carrier-less wafer stacking (Tezzaron’s FaStack)
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Ref: www.tezzaron.com
Compression molded chip to wafer stacking at Invensas
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Critical Steps and Metrology Process Parameter Techniques Comments
TSV RIE Diameter Optical interferometry, SEMDepth Optical interferometry, SEMProfile SEM Destructive
TSV Liner Dielectric Thickness Ellipsometry Blanket filmsStep Coverage SEM Destructive
TSV Barrier/Seed Thickness Resistance, XRF Blanket filmsStep Coverage SEM, TEM Destructive
TSV Fill Purity Resistance, Auger, SIMSOverburden Resistance, XRFVoids x-ray tomography, SEM slow, destructiveStrress Micro Raman (in Si), (in Cu) Post anneal
Temporary Bond/debond Voids Scanning Acoustic MicroscopyThickness Contact gage, capacitance ImmatureDebond quality optical microscopy, SEM Immature
Wafer Backgrind Thickness Contact gage, CapacitanceUniformity CapacitanceBow/Warp Capacitance
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Critical Steps and Metrology
Process Parameter Techniques Comments
TSV reveal Endpoint Optical, feed forward from TSV depthCu Contamination Scanning Surface Pot. Diff, TXRF, SIMS
Wafer Bonding Alignment IR Microscopy, Electrical VerniersBow/Warp Capacitance, Optical (Moire)Defectivity IR Microscopy
Bumping Coplanarity Optical (laser triangulation, confocal)Missing Bumps Optical, SEM
Dice Edge quality SEMPick and place Die strength Four point bend
Edge Cracks Optical
Die bond (subs., C2C, C2W) Alignment IR Microscopy, Electrical Verniers, SEMWarpage Optical (Moire)
Underfill Voids Scanning Acoustic Microscopy, SEMWarpage Optical (Moire)
Chip Interoperability and Standards: 3D Enablement Center
http://wiki.sematech.org/3D-Standards
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Chip Interoperability and Standards: 3D Enablement Center
http://wiki.sematech.org/3D-Standards
• One-stop location to identify ongoing 3D standards activities – 3D standards activities are currently spread across a wide range of standard development
organizations (SDOs).
• Open for public access and comment – Open dialog among members of the standards community – Help identify unmet standards needs – Encourage participation in standards
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Chip Interoperability and Standards: 3D Enablement Center
http://wiki.sematech.org/3D-Standards
• One-stop location to identify ongoing 3D standards activities – 3D standards activities are currently spread across a wide range of SDOs
• Open for public access and comment – Open dialog among members of the standards community – Help identify unmet standards needs – Encourage participation in standards
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(July 2012)
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HVM Readiness Scorecard
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Technology and equipment • Mostly “mature”, albeit in low volume • Need to drive alternatives to Temporary Bond/Debond • 3D EDA tools are becoming more common
Metrology • Fairly mature
Standards • Coming along • SEMI, IEEE, JEDEC, …
Ecosystem • Fab/OSAT alternatives to turnkey solutions exist*
* “Enabling a Manufacturable 3D Technologies and Ecosystem using 28nm FPGA with Stack Silicon Interconnect Technology” IMAPS 2013 (Xilinx)
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HP Logic + Stacked Memory Interposer
CPU+L1/L2 cache
On-package, stacked Memory > 2GB
Interposer
Main Memory
Future CPUs: L1 cache about 32KB, L2 cache 256KB, on package large size DRAM > 2GB
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1 Interposers available in volume production since 2012
2 & 3 Stacked memory becoming available for on-package and main memory - Micron’s Hybrid Memory Cube - SK Hynix’s High Bandwidth Memory and LRDIMM Module - Samsung’s Wide I/O DRAM and server module Server CPUs leveraging stacked memory to appear soon
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Outline
• Background
• Assessing Readiness
• Status and Summary
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2.5D HVM Readiness*
Ref: *The International Technology Roadmap for Semiconductors 2012 update
We are here
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Typical Technology Transitions – Status of 2.5D
Acceptance of next-generation technologies is catalyzed by the convergence of several factors: New technology moves beyond feasibility stage Industry leaders come to consensus on timetable Cost/benefit ratio of incumbent technology becomes minimal Willingness to invest Robust ecosystem is (almost) ready
3D is less mature • Cost, thermal management and test remain key concerns • A major product pull is necessary to drive Common reference flow(s), prototypes and cost models
IMAPS Device Packaging 2013
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