3D ASICs program at Fermilab

Fermilab ASIC Design Group (G.Deptuch, F.Fahim, J.Hoff, M.Trimpl, A.Shenai, T.Zimmerman)

R.Yarema – retiredD.Christian, R.Lipton, T.Liu

and collaboratorsfrom:

BNL Upton NY, SLAC Menlo Park CA, AGH-UST Kraków Poland

US Universities: Brown U., Cornell U.and industrial partners:

Tezzaron Naperville IL, Ziptronix Morrisville NC, RTI Research Triangle Park NC, ALLVIA Sunnyvale CA,

CVInc. Dallas TX,

Introduction

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Environment of integrated circuits technology for radiation detector readout systems is:

• Competitive

• Investments hungry

• Characterized by long gaining experience curves for the ASIC groups

• Challenging due to restrictions in access to the cutting edge technologies, legalities and bureaucratic burden associated with it

Groups tend to emphasize on one or a few particular detector technologies, families of design blocs, design methodologies or assembly works and excel offering complementary sets of skills and tools to the community

Fermilab advanced 3D-IC technology

gaining the World leading position

3D chip is composed of two or more layers of active electronic components and features horizontal intra-tier and vertical inter-tier connectivity,

Distinguishing features of 3D technologies: 4Through Silicon Vias (TSV)5Bonding5Wafer thinning5Back-side processing3

Transformational change: 4Finer pitch pixels 5Less mass 5Higher localized “on detector” functionality 5Bump bond alternative 5Non dead space arrays 3

Support: glass or

Si interposer

3

Motivation

Strategic goal: 4 side buttable, dead-area-free detectors for uses ranging from X-ray, visible, IR imaging to classical tracking

3D ASIC with TSVs

threading connections

Large-area seam-

less sensor

Long-term goal:

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Review: design VICTR

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Review: design VIPIC1

6 AEM Nov. 4, 2013

VIPIC1 (Prototype) is designed to quickly count the number of hits in every pixel and read out the # of hits, and addresses in a dead timeless manner,

Matrix of 64×64 pixels divided into

16 group of 4×64 pixels read

through one LVDS buffer

7

Design of VIPIC1 - 1

G.Deptuch, M.Demarteau, J.Hoff, R.Lipton, A.Shenai, M.Trimpl, et al., “Vertically Integrated Circuits at Fermilab“, IEEE Transaction on Nuclear Science, vol. 57, no. 4, (2010), pp. 2178-2186

G.Deptuch, M.Trimpl, R.Yarema, D.P.Siddons, G.Carini, R.Szczygieł, P.Grybos, P.Maj, “VIPIC IC - Design and Test Aspects of the 3D Pixel Chip”, Proceedings of Nuclear Science Symposium, Knoxville, USA, October 2010

G.Deptuch, G.Carini, P.Gryboś, P.Kmon, P.Maj, M.Trimpl, D.P.Siddons, R.Szczygieł, R.Yarema, „Design and Tests of the Vertically Integrated Photon Imaging Chip” – submitted to IEEE Transaction on Nuclear Science

more details:

Sparsification engine selects hit

pixels in every group for readout

Active area: 5120×5120 μm2, chip:

6.3×5.5 mm2

Only digital information read out

(160 ns /hit pixel)

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Digital:1400 transistorsAnalog: 280 transistors

discriminator output

12-bit for configuration7-bit trim offset, 3-bit trim Rf,single/dif mode, CAL enable

Doubled bond pads for each signal

Power suplies tied between tiers

4in-pixel 1-stage pipe-line logic 4disributed sparsifier: 8 bit priority encoder, pixel readout selector, pixel address generator and counter output42×5-bit long counters4configuration registers: single bit / pixel (pixel SET, pixel RESET) and 12 bit DAC and configuration (calib., singl./diff.)

8

Design of VIPIC1 - 2

4Single ended or pseudo-differential CSA-shaping filter-discriminator: shaping time tp=250 ns, power ~25 mW / analog pixel, noise <150 e- ENC, gain(Cfeed=8fF) = ~115mV/8keV (optimized for 8 keV in Si - linearity up to 3×8 keV)41 threshold discriminator410 bit/pixel DAC adjustments

Pixel 80x80 mm2

2-lines for CAL circuits

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• 3D-IC Consortium established in late 2008, 17 members; 6 countries + Tezzaron

• Fermilab set up 1st 3D-IC MPW for HEP-MPW frame accepted for fab in 03/2010

• 1st working chips got from 2 bonded pairs of wafers (TC) in 06/2012

• March-May-June 2013 last 3D bonded wafers (TC and DBI) yielding more good chips

Via middle – TSV

in foundry after FEOL

130nm CMOS 6M1P

Face-Face

TS Vias (f=1mm)

Fabrication of VIPIC1 - 11st 3D-IC MPW RUN

Tezzaron / NovatiZiptronix / licensed to Novati

Better yields

observed

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Tests VIPIC1 electrical - 1

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Map of pixels with noise (scale: black – 0 mV rms, white – 10 mV rms)

4 Hamamatsu baby sensors available as singulated dies, decided to be used while waiting for ultimate bonding of BNL sensors using the DBI process

Layout of ”to sensor pads” on VIPIC1

original 80 mm - pitch pads for BNL sensors overlaid with 100 mm pitch pads for Hamamatsu sensors

80 mm pitch

100 mm pitch

skipped row skipped column

Noise (ENC) calculated using gain from calibration with charge injection

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Tests VIPIC1 bump bonded to sensor - 1

4 100 mm pitch Hamamatsu pixel baby-sensor with Sn-Pb bumps

4 deposition technique on a single die with ENIG UBM on Al substrate pads by (CVInc.) – pads f=60 mm

4UBM deposited on VIPIC (ENIG pads are bondable)

4 300 mm thick Hamamatsu pixel sensor mounted on top of VIPIC (75 mm bump, post reflow gap at 45 mm to 50 mm prior to addition of underfill)

4 Optimization of the Ni-Au deposition led to almost 100% of pads retaining UBM and bumps

500 mm thick

back-side of sensor

Wire bonding pads

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Tests VIPIC1 bump bonded to sensor - 2

Detector biased at 120 V (full depletion) 109Cd and 55Fe used

W mask with Fermilab logo

ROIC area

rows & cols skipped

2G

2 4 55Fe source used

4 All signals integrated above

threshold set higher than noise

4Only very limited number of pixels are

insensitive

4significant gain dispersions

4 Full sparsified readout (from all 16 groups of 4×64 pixels) used

4Acquisition run for a few hours to accumulate enough of statistics

Transmission radiogram of a small W mask (2.5×2.5 mm2) placed atop of the sensor back-side illuminated and fully depleted

mask has features

smaller than the

sensor pitch, e.g.

center hole f=75

mm

observations

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Tests VIPIC1 bump bonded to sensor - 34 Scanning of thresholds (vt2-vt1) with fine 0.5 mV/step resolution

4 Full sparsified readout using 50 MHz data serialization clock simultaneously from every group

4 Duration of a single readout cycle ~80ms (timing precision)

4 Reference data without source

4 Sources used:- 109Cd 22 keV (1mCi)- 55Fe 5.9 keV (10mCi)

Detector biased at 120 V (full depletion)109Cd 22keV and 55Fe 5.9keV

4 5.9 keV photon à 1640 e-/h+

Gain= (420-350) mV/ph*1ph/1640=43mV/e-

Noise= 3.5 mV rms*1e-/43mV = 83e- rms

Response gets strongly nonlinear above

approximately 18 keV

Selected results from a single pixel from a run with flat field illumination

Definite analyses (noise, gain, statistics) are underway…

as well as devices bonded to 64 ×64 pixel sensors are expected before the end of 2013

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Invitation

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Invitation

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