3a ee600 lab1_schwappach

REVIEW OF SPICE: LAB 1 1

Review of SPICE: Lab 1

Loren Karl Schwappach

EE600: Modern Solid State Devices

Colorado Technical University

6 September 2011


Abstract

This lab reviews some of the essential features available through the use of the modeling tool

known as SPICE. It uses PSPICE to perform several analysis of a simple TTL inverter circuit.


Table of Contents

Objectives………………………………………………………………………………..…….4

Theory and Design Approaches / Trade-offs…………………………………………….…….4

Circuit Schematics………………………………………………………………………..……5-8

Analysis

Part 1: DC Transfer Characteristics…………………………………………………….9

Function…………………………………………………………………..…….10

Threshold Voltage…………………………………………………...………….11

Noise Margins……………………………………………………………….12-13

Power Curve…………………………………………………………………….14

Part 2: AC Characteristics………………………………………………...…………15-16

Extra: Frequency Analysis………………………………………………..…………17-18

Part 3: Propagation Delays and Rise/Fall Times

Propagation Delays ………………………………………………………….19-23

Rise and Fall Times………………………………………………………….23-24

Max Switching Frequency…………………………….………………………..25

Conclusions…………………………….……………………………………………………26-27


Review of SPICE: Lab 1

Objectives:

This lab exercises a circuit analysis tool called PSPICE. SPICE stands for Simulated

Program with Integrated Circuit Emphasis. It was originally an analog circuit simulator that was

developed by students at the University of California at Berkley. This lab assignment is

designed to review a few of the circuit modeling and analysis tools available in SPICE. The

student performing the lab models a simple TTL circuit, performs a DC analysis of the circuit,

and identifies the circuits function, threshold voltage, noise margins, and power used. Next the

student performs an AC analysis finding the gain, Zin, and Zout. Finally the student uses a 10 us

digital pulse to find the circuits propogation delays, and rise/fall times.

Theory and Design Approaches / Trade-offs:

There are no specific design requirements for this project since it is not a design project,

but a SPICE learning / review lab.


Circuit Schematics:

Figure 1: Circuit 1 Schematic for DC Analysis

This circuit (Fig. 1) is used for generating the DC transfer characteristics of the circuit.

GND_0

0

R4k

R11.6k

R21k

Q1Q2N3904 D2

D1N4001

Q2Q2N3904

Q3Q2N3904

Q4Q2N3904

GND_0

R3130

Vcc5Vdc

VinA

5Vdc

Circuit 1Part 1: DC Characterisitcs

Review of SPICE: Lab 1Loren K. Schwappach

RL20k

CL40n

Out


Figure 2: Circuit 2 Schematic for AC Analysis

This circuit (Fig. 2) is used for generating the AC small-signal characteristics of the

circuit. It replaces VinA’s source with a VAC source as shown.

GND_0

0

R4k

R11.6k

R21k

Q1Q2N3904 D2

D1N4001

Q2Q2N3904

Q3Q2N3904

Q4Q2N3904

GND_0

R3130

Vcc5Vdc


VinA

1Vac1.3845Vdc

Circuit 2Part 2: AC Characteristics

RL20k

CL40n

Out


Figure 3: Circuit 3 Schematic for Frequency Analysis

This circuit (Fig. 3) is was used as an extra circuit for performing a frequency analysis of

the circuit. It is the same as Fig 2.

GND_0

0

R4k

R11.6k

R21k

Q1Q2N3904 D2

D1N4001

Q2Q2N3904

Q3Q2N3904

Q4Q2N3904

GND_0

R3130

Vcc5Vdc


Circuit 3Extra: Frequency Analysis

VinA

1Vac1.3845Vdc

RL20k

CL40n

Out


Figure 4: Circuit 4 Schematic for Propagation Delay and Rise/Fall Time Analysis

This circuit (Fig. 3) is was used for simulating a 50 us pulse input. It replaces VinA with a pulse

source as shown.

GND_0

0

R4k

R11.6k

R21k

Q1Q2N3904 D2

D1N4001

Q2Q2N3904

Q3Q2N3904

Q4Q2N3904

GND_0

R3130

Vcc5Vdc


Circuit 4Part 3: Propogation Delays and Rise/Fall Times

RL20k

CL40n

VinA

TD = 20uTF = .1u

PW = 50uPER = 100u

V1 = 0

TR = .1u

V2 = 5

DC = 0

Out


Analysis:

Part 1: DC Transfer Characteristics:

Figure 5: DC Characteristics Simulation Settings

In order to calculate DC Characteristics a DC sweep was run using the settings shown

above. A trace of Vout was also added to the plot to obtain the initial Vout vs. Vin results.


Figure 6: DC Characteristics Simulation Results

Function:

It can be seen from the results that there are at least two distinct linear regions where the

circuit is performing switching. It is also observed that an input low voltage (0 V to 1.3 V)

results in a high output voltage (3 V to 3.89 V), while am input high voltage (1.44 to 5 V) results

in a low output voltage (around 23 mV). The linear regions occur when VinA is between 1.3 V

and 1.44 V). This identifies that the circuit is operating as an inverter circuit.


Threshold Voltage:

Figure 7: Logic Threshold Possibilities

There are several ways to identify the circuit’s logic threshold or switching point. The

first is to draw a line with a slope of one on the output results shown by Fig. 7. For an inverter

this is the point where Vin equals Vout and occurs on the second linear region identified at 1.39

V. Another popular method for finding the logic threshold is to take the point where Vout (high)

begins to switch to Vout (low) and subtracting the point where Vout low begins to remain steady

and then dividing this result in half. The points (VinA (low), Vout(high)) and (VinA (high),

Vout(low)) are found by adding a second plot to the graph and using the new top plot to find the

points where the slope (derivative) of Vout equal -1. Using this method the logic threshold is at


1.38V. It is therefore estimated that the logic threshold for this circuit occurs at the initial

position (where Vout equals VinA) at 1.39 V since it lies closer to the middle of the second and

more importantly the more drastically sloped linear region. The true logic threshold probably

occurs in between these two values. (1.38 V < logic threshold < 1.39 V).

Noise Margins:

Figure 8: Noise Margin Calculations

The noise margins for the circuit are found using the previously identified (VinA (low),

Vout(high)) and (VinA (high), Vout(low)) points found where the slope of Vout equaled -1. The

Logic Noise Margin is the difference between what the circuit outputs as a valid logic voltage


and what the circuit expects to see as a valid logic voltage. The two equations I used to find

noise margins are:

The higher the noise margins the better the circuit will be able to handle a diverse range

of logic values. You can find Vout(high), Vout(low), VinA(low), and VinA(high) by using the

method previously mentioned (where slope of Vout equaled -1) or by estimating and using

minimum numbers for high output and maximum numbers for the low output. Since

and the is around 2.375 V. Since

and the is around 586 mV. Thus the inverter

circuit has a good NMH and a poor NML. Ideal noise margins would be approximately 2.5 V

for this inverter circuit.


Power Curve:

Figure 9: SPICE Results of Power Used By Circuit

According to the power used results only 6 mW of power is used when the input is 0 V

and only 16 mW of power is used when the input is 5 V. The majority of power (165 mW) is

used when the inverter is in the linear (amplification) region and the input is between 1.3 V and

1.44 V.


Part 2: AC Characteristics:

Figure 10: AC Characteristics Small Signal Gain Analysis Settings

AC Small signal characteristics were obtained by modifying the input source from a DC

source to an AC source and by placing the DC value at the bias point (turn on point) value

identified near the middle of the linear region of Vout from Fig. 7. The value of 1.3845 was

used for the bias since it resulted in a larger small signal gain than the predicted logic threshold

value of 1.3924V. A bias point small signal gain analysis was then created by selecting

“calculate small-signal DC gain” and clicking on “view simulation output file”. The results

follow.


Figure 11: AC Characteristics Small Signal Gain Results

The small signal gain analysis results showed the circuit gain to be approximately -62.37

(G=-62.37). The input impedance (Zin) was calculated to be 3.547 kΩ and the output impedance

(Zout) was calculated to be 112.9Ω. An ideal inverter circuit would have an input impedance of

infinity and an output impendence of zero.


Extra: Frequency Analysis:

Figure 12: AC Sweep Analysis Settings for Frequency Analysis.

As an extra step for this lab a frequency analysis of the circuit was obtained by running a

AC Sweep/Noise analysis of the circuit as shown above. This allowed for the creation of a bode

plot highlighting the corner frequency (-3dB) point of the circuit.


Figure 13: AC Characteristics Small Signal Gain Results

I changed the y-axis to obtain the decibel gain of the circuit using the DB function on a

trace of Vout. This illustrated that the corner frequency of the circuit occurred at approximately

37 kHz. The -3dB point is the point at which the power is reduced to ½ of the maximum and the

voltage gain is reduced to .707 of the maximum.


Part 3: Propagation Delays and Rise/Fall Times:

Figure 14: Pulse Transient Simulation Settings

The next section required changing the input source with a Vpulse source and setting up

the Vpulse input as shown by Fig. 4. In order to obtain propagation delay times (high to low and

low to high) and rise / fall times a transient analysis (Time Domain) simulation was ran using a

run time of 320 us, a start time of 120 us, and a maximum step size of 10 ns. This would allow

for two periods of the input pulse. A trace for Vout and VinA were then added to the completed

simulation.


Figure 15: Propagation Delay and Rise / Fall Time Analysis - Zoomed Out

The figure above (Fig. 15) represent two periods of the input pulse and resultant output

waveform. Propagation delay low to high and rise time results are obtained next by zooming in

from the point where the input changes from high to low (at about 170 us) to the point where the

output starts to become fixed at its high value (at about 182 us). Propagation delay high to low

and fall time results are obtained by zooming in from the point where the input changes from low

to high (at about 219.866 us) to the point where the output starts to become fixed at its low value

(at about 221.5 us).


Propagation Delays:

Figure 16: Propagation Delay Low to High Results

The low to high propagation delay time for this circuit is calculated by taking the time at

the point the output has risen from low to fifty percent of the high output and subtracting the time

at which the output begins to rise due to a logic change by the input pulse. This is defined by the

following formula:

Since was found to occur at 173.259 us and was found to occur

at 170.207 us the resultant propagation delay time from low to high is 3.052 us. This is a time

factor of about seven times longer than the low to high propagation delay time results.


Figure 17: Propagation Delay High to Low Results

The high to low propagation delay time for this circuit is calculated by taking the time at

the point the output has fallen from high to fifty percent of the high output and subtracting the

time at which the output begins to fall due to a logic change by the input pulse. This is defined

by the following formula:


at 220.027 us the resultant propagation delay time from high to low is 394 ns. This is a time


factor of about seven times quicker than the high to low propagation delay time results. The total

propagation delay is the sum of both propagation delays divided in half or 1.723 us.

Rise and Fall Times:

Figure 18: Rise Time Results

The rise time for this circuit is calculated by taking the time at the point the output has

risen from low to ninety percent of the high output and subtracting the time at which the output

has risen from low to ten percent of the high output. This is defined by the following formula:



at 170.725 us the resultant rise time is 8.355 us. This is a time factor of thirteen times longer

than the fall time results shown next.

Figure 19: Fall Time Results

The fall time for this circuit is calculated by taking the time at the point the output has

fallen from high to ten percent of the high output and subtracting the time at which the output has

fallen from high to ninety percent of the high output. This is defined by the following formula:


Since was found to occur at 220.738 us and was found to occur at

220.119 us the resultant fall time is 619 ns. This is a time factor of thirteen times faster than the

rise time results.

Max Switching Frequency:

The maximum switching frequency for a circuit is normally defined by the formula:

With the fall time calculated at 619 ns and the rise time calculated at 8.355 us the

maximum switching frequency of this circuit is approximately 111 kHz. This requires that the

fastest clock run below this frequency. Furthermore, the frequency analysis showed the corner

frequency at approximately 37 kHz; therefore it would be beneficial to limit the fastest clock

frequency below this value. It is clear that this inverter would function poorly for high speed

GHz devices. ETL would be a better option for such devices.


Conclusions:

Summary of Results

Evaluation Procedure Parameter Ideal Inverter This Inverter

Transfer Characteristic VThreshold 2.5 V

Estimated at

1.39 V

Noise Margins

NMH 2.5 V 2.375 V

NML 2.5 V 586 mV

Power Used

P @ VinA = 0 V 0W 6 mW

P @ VinA = 5 V 0W 16 mW

PMax 0W 165 mW

Small Signal Gain Av -62.37

Impedances

Zin 3.547 k ohms

Zout 0 112.9 ohms

3dB Corner Frequency F3dB 37 kHz

Propagation Delays

tPHL 0 s 394 ns

tPLH 0 s 3.052 us

tP 0 s 1.723 us

Rise Time tLH 0 s 8.355 us

Fall Time tHL 0 s 619 ns

Max Frequency fMax 111 kHz

In conclusion this lab successfully met the assignments objectives. PSPICE was shown

to be an effective utility for analyzing a circuit and summarizing this circuit’s digital and analog

characteristics. The inverter analyzed in this design had a poor NML (as do most TTL circuits),

and is not suitable for high frequency applications (GHz range). It is essential for an engineer to


know how to use and apply modeling tools. PSPICE is just such a tool and has incredible

applications if the engineer knows how to use them.

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