350-w,two-phaseinterleaved pfc pre-regulatordesign...

1 Abstract

2 Review the Benefits of Interleaving PFC Boost Pre-Regulators

Application ReportSLUA369B–February 2005–Revised March 2007

350-W, Two-Phase Interleaved PFC Pre-regulator DesignReview

Mike O'Loughlin .................................................................................................... System Power MAN

In higher power applications to utilize the full line power and reduce line current harmonics PFCpre-regulators are generally required. In these high power applications interleaving PFC stages canreduce inductor area and reduce output capacitor ripple current. This is made possible through theinductor ripple current cancellation that occurs with interleaving. This application note reviews the designof a 350-W two phase interleaved power factor corrected (PFC) pre-regulator. This power converterachieves PFC with the use of the UCC28528 PFC/PWM controller along with the UCC28220 interleavedPWM controller that is used to interleave the two power stages. The converter also has a 2-W auxiliarybias supply that supplies power to the converters gate drive and PWM/PFC circuitry. The completeschematic of the working design is shown in Figure 7 and Figure 8.

Figure 1 shows the functional diagram of a two phase interleaved boost converter. The interleaved boostconverter is simply two boost converters operating 180 degrees out of phase. The input current is the sumof the two inductor currents IL1 and IL2. Because the inductor’s ripple currents are out of phase, theycancel each other out and reduce the input ripple current caused by the boost inductors. The best inputinductor ripple current cancellation occurs at 50% duty cycle. The output capacitor current is the sum ofthe two diode currents (I1 + I2) less the dc output current. This reduces the output capacitor ripple current(IOUT) as a function of duty cycle. As the duty cycle approaches 0%, 50% and 100% duty cycle, the sum ofthe two diode currents approaches dc. At any of these optimum operating points, the output capacitor onlyhas to filter the inductor ripple currents.

SLUA369B–February 2005–Revised March 2007 350-W, Two-Phase Interleaved PFC Pre-regulator Design Review 1Submit Documentation Feedback

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLUA369B

www.ti.com

L1 I1

IL1

S1

On

Off

S1

S2

On

Off

L2 I2

S1

IL2

2

I1

I2

Icout = (I1 +I2) − Iout 0A

RLOADCOUT

ICOUT

IOUTIIN

VIN

IIN

IIN = IL1 + IL2

Review the Benefits of Interleaving PFC Boost Pre-Regulators

Figure 1. Interleaved Boost Stage

350-W, Two-Phase Interleaved PFC Pre-regulator Design Review2 SLUA369B–February 2005–Revised March 2007Submit Documentation Feedback


www.ti.com

2.1 Input Ripple Current Reduction as a Function of Duty Cycle

K(D)��IIN�IL1 (1)

K(D)� 1� 2D1� D

if D� 0.5(2)

K(D)� 2D� 1D

if D� 0.5(3)

0 0.1 0.2 0.3 0.6 0.7 0.9 1.00

0.2

0.4

0.6

0.8

1.0

0.4 0.5 0.8

0.1

0.3

0.5

0.7

0.9

INPUT CURRENT/INDUCTOR RIPPLE CURRENT vs

DUTY CYCLE

K(D

) −

Indu

ctor

Rip

ple

Cur

rent

− C

ance

latio

n F

acto

r

Duty Cycle − D( Θ)

VIN(�)� VIN(rms)� 2� sin(�) line voltage as a function of phase angle. (4)

D(�)�VOUT� VIN(�)

VOUT duty cycle as function of phase angle (5)


The following equations show how the ratio of input ripple current to inductor ripple current (K(D)) varywith changes in duty cycle. Figure 2 shows how K(D) varies with changes in duty cycle. It’s important toremember these variations in input ripple current, when selecting inductors for the interleaved boostconverters. This is because the duty cycle in PFC pre-regulator is not fixed and changes with line voltage.

Figure 2. Input Ripple Current Reduction

In PFC pre-regulators the duty cycle (D(θ)) is not constant and varies with changes in line voltage (Vin(θ)). The amount of duty cycle variation for universal applications can be quite large. This variation in dutycycle can be observed by evaluating a converter that was designed for a universal input of 85 V to 265 Vwith a regulated 385 V dc output. At low line the duty cycle (D1(θ)) varies from 100% to 68% and at highline the duty cycle (D2(θ)) varies from 100% down to 2%. The inductor ripple current cancellation will notbe 100% throughout the line cycle. However, it is good enough to drastically reduce the input ripplecurrent for a given inductance. The highest ripple current in this example would occur at the peak of lowline with a duty cycle of 68%. The amount of inductor ripple current seen at the input for this duty cyclewould be 55%.

where ω = 2 π fLINEand θ = ωτ



www.ti.com

00

0.1

0.2

0.7

0.8

0.9

0.3

0.4

0.5

0.6

1.0

DUTY CYCLE vs

PHASE ANGLE

180160120906030

D1

(Θ),

D2

(Θ) −

Dut

y C

ycle

Phase Angle − Θ

2.2 Evaluate Magnetic Volume Reduction

ESINGLE�12

LI2 single stage inductor energy. (6)

EINTERLEAVED�12

L� I2�

2�

12

L� I2�

2�

14

LI2 two phase total inductor energy. (7)

IPEAK�POUT(max)� 2

�

VIN(min) (8)

WaAcSINGLE�L� IPEAK

B�

IRMSCD�

L� IPEAKB

�

IPEAK2�

CD (9)

WaAcINTERLEAVED�L�

IPEAK2

B�

IPEAK2� 2�

CD (10)


Figure 3. Duty Cycle Variation in Universal PFC Pre-Regulator

The inductor ripple current cancellation allows the designer to reduce boost inductor magnetic volume.This is due to the energy storage requirement of the two interleaved inductors being half that of singlestage pre-regulator designed for the same power level, switching frequency and inductance.

The amount of reduction in boost inductor volume can be seen mathematically by comparing the requiredinductor area products of single stage PFC pre-regulator (WaAcSINGLE) with that of a two phaseinterleaved pre-regulator inductor (WaAcINTERLEAVED) for a given inductance. The exact values for theinductor (L), inductor RMS current (IRMS), current density (CD) and flux density (B) are not required to showthe reduction in area product.

4 350-W, Two-Phase Interleaved PFC Pre-regulator Design Review SLUA369B–February 2005–Revised March 2007Submit Documentation Feedback


www.ti.com

2�WaAcINTERLEAVEDWaAcSINGLE

�12 (11)

2.3 Output Capacitor Ripple Current Reductions as a Function of Duty Cycle

ICOUT(single)(D)� (1� D)� [1� (1� D)]�

(12)

ICOUT(D)�12

(1� 2D)� (1� 2D)2� if D� 0.5

(13)

ICOUT(D)�12

(2� 2D)� (2� 2D)2� if D� 0.5

(14)

0 0.1 0.2 0.3 0.4 0.8 0.9 1.0

D

0

0.05

0.10

0.35

0.40

0.45

0.5 0.6 0.7

0.15

0.20

0.25

0.30

0.50

GAIN/PHASE vs

FREQUENCY

ICOUT(single)

ICOUT (D)

No

rmal

ized

Cap

acito

r R

MS


The ratio of the total interleaved area product (2 X WaAcINTERLEAVED) to the area product of a single stagepre-regulator is 0.5. This results in a 50% reduction in area product just by interleaving, which will result ina substantial reduction in boost magnetic volume.

Interleaving PFC pre-regulators if done in this fashion will not increase the size of the EMI filter. Acommon design practice is to select the switching frequency of the power converter below the EMI band of150 kHz. The second harmonic of switching frequency would be twice the fundamental and will most likelybe in the EMI band and would need to be filtered to meet specifications. Interleaving two pre-regulatorscauses the input to see a switching frequency that is twice the switching frequency of a single phase. Thismeans the fundamental switching frequency of the converter will most likely be pushed into the EMI bandand be at the second harmonic of an individual stage's switching frequency. However, the input ripplecurrent is reduced by a factor of two. This should not put any additional constraints on the EMI filter.

Figure 4 shows the normalized output capacitor RMS current in a single stage boost (ICOUT(single)(D)) andthe normalized capacitor RMS current in a two phase interleaved boost converter (ICOUT(D)) as a functionof duty cycle. Figure 4 illustrates that the output capacitor ripple current in a two phase interleaved is halfthat in a traditional single stage boost converter for the same power levels. The reduction in RMS currentreduces heating caused by the capacitor’s ESR losses, reducing electrical stress.

Figure 4. Normalized Output Capacitor Ripple Currents



www.ti.com

3 Design ReviewDesign Review

The power supply design requirements are presented in Table 1. Please note this 350-W PFCpre-regulator design is based on a TI evaluation module HPA117, TI User’s Guide Literature numberSLUU228, which is orderable through TI. Please visit www.ti.com for details. Also note that the designpresented in this application note is based on typical values. In a production environment a worst caseanalysis would have to be conducted.

Table 1. Design Requirements

PARAMETER MIN TYP MAX

VIN 85 V RMS 110 V or 230 V RMS 265 V RMS

VOUT 374 V 390 V 425 V

VRIPPLE 30 V

Current THD at 350 W 10%

PF at 350 W 0.95

Full load efficiency 90%

fS 100 kHz

Holdup requirements (tHOLD) 20 ms

fLINE 47 Hz 50 Hz 60 Hz



www.ti.com

+V

ref

Mu

lt

VF

F

VA

+

CA

Vo

ut

Ria

c

Ra Rb

PF

CR

sen

se

Rm

o

Rm

o

UC

C28

5228

+ +

UC

C27

324

Co

ut

T1

T2

L2

L1

D1

D2

Vo

ut

RL

Rfa

Cza

Cp

a

Rfb

Czb

Cp

b

UC

C28

220

20K

30K

Rc

Rd

Rse

nse

Rre

set

Rse

nse

Rre

set

Vin

= 8

5 to

265

V R

MS

CT

RL

T1

T2

Rg

ate

Rg

ate

Rsl

op

eS

lop

e

CH

GD

SC

HG

Rch

g

Rd

sch

g

6.81

K

10K

Iac

Cvf

fR

vff

MO

UT

Vc

Design Review

Figure 5. Functional Schematic



www.ti.com

3.1 Boost Inductor Selection

L1� L2�VIN(min)� 2

�� DMIN(LL)

�IL� fS�

85 V� 2� � 0.694.1 A� 100 kHz

� 200 �H(15)

3.2 Output Capacitor Selection (COUT)

COUT�

2� POUT�1

fLINE

VOUT2� �

VOUT2�

2� 123 �F

(16)

COUT�14�

POUTVOUT��0.637

VRIPPLE� 0.8� �� fLINE� 104 �F

(17)

ESRMAX�VRIPPLE� 0.2

POUT� 2�

VIN(min)��

� 1.3 �

(18)

COUT�COUT

(1� 0.2)(1� 0.2)� 220 �H

(19)

Iterations�fS

2� fLINE� 1� 103

(20)

Step�

� 1fLINE�

Iterations (21)

IIN(t)�POUT� 2

�

VIN(min)� sin(�� t)

(22)

ICOUT(rms)�

�Iterations

n�1�

IIN(n� Step)2�1

2(2� 2� D1(n� Step))� (2� 2� D1(n� Step))

2� �

2

�

�

�

Iterations

�� 1 A

Design Review

Cooper Electronics designed the 200 µH, CTX16-17309, boost Inductors for our design.

There are three determining criteria for selecting the output capacitor. They are holdup energy, outputripple voltage and lastly RMS ripple current. Equation 16 and Equation 17 are used to select the outputcapacitor. Equation 16 selects the output capacitor based on holdup requirements, while Equation 17sizes capacitance base on output voltage (VRIPPLE) requirements. The designer should select the largestresult of Equation 16 and Equation 17 for the design.

The capacitor should also be de-rated based on capacitor tolerances. The following equation de-rates theoutput capacitor based on 20% error in capacitance tolerance and a 20% variation over the life of thecapacitor.

The RMS ripple current for the boost capacitor can be calculated with the following equations. To usethese equations it is a good idea to use MathCAD or MATLAB design tools.

(23)



www.ti.com

3.3 FET and Diode Selection

PSEMI� �POUT�� POUT�� 0.5� 19 W

(24)

3.4 Diode Selection

IDIODE�POUT

2� VOUT� �� 2.3 A

(25)

IDIODE(peak)� �POUT 2

�

2� VIN(min)� ��IL1

2�� 5.3 A

(26)

PDIODE�POUT� VF

2� VOUT� �� 0.6 W

(27)

3.5 FET Selection Based on RMS and Peak Currents and Estimated FET Losses

IPEAK� �POUT 2

�


2�� 5.3 A

, peak FET current. (28)

IFET(rms)� fLINE� �Iterations

n�1�

�D1(n�Step)

fS�

O

�IIN(n� Step)

2�

2� dt(29)

IINton(t)� �

POUT� 2�


2� sin(�� t)

, peak FET line currents (IINton(t)) at switch turn off. (30)

IINtoff(t)� �

POUT� 2�


2� sin(�� t)

, peak FET line currents (IINtoff(t)) at switch turn off. (31)

COSS(avg)� 2� COSS(spec)�VDS(spec)

VOUT� � 2� 310 pF� 25 V

385 V� � 160 pF

(32)

Design Review

To meet the efficiency requirements (η) of the design a power budget (PSEMI) of 19 W was set. Selectingthese semiconductor devices are always trial an error. It may take several tries before the appropriatesemi conductor devices can be chosen for the design.

To reduce switching losses CREE CSD10060 SiC rectifiers were used. These diodes have close to zeroreverse recovery current. The following equation is used to estimate the diode loss (PDIODE) and diodepeak (IDIODE(peak)) and average current (IDIODE), where Vf is the forward voltage drop of the boost diode.These diodes in our design will dissipate around 0.6 W (PDIODE) per diode dissipating a total of 1.2 W forboth diodes in the design. This leaves 17.8 W of losses for the boost FETs and the auxiliary bias supply.

The following equation estimates FET RMS current (IFET(rms)) which is needed to estimate boost FET(PFET) losses.

Part of the total FET losses are contributed Coss (COSS(avg)) charging and discharging during a PWMswitching cycle. COSS varies with line voltage and is not a linear function. The following equation andinformation from the FETs data sheet can be used to calculate COSS(avg). COSS(spec) is the typical COSSmeasured at a specified VDS voltage (VDS(spec)). A IRF840, 8 A 500 V FET was selected for the design.The estimated COSS(avg) was roughly 160 pF.



www.ti.com

QGS(miller)� 30 nC , the typical maximum miller plateau gate charge for VDS equal to 400 V. (33)QGS(max)� 52 nC (34)

IGATE�VGS(max)

2� RGATE , is average FET gate drive current. (35)

tON(delay)� tOFF(delay)�QGS(miller)

IGATE (36)

PSWITCH(toff)� fLINE �Iterations

n�1�IINtoff

(n� Step)� VOUT� tOFF(delay)� , switching losses at FET turnoff. (37)

PSWITCH(ton)� fLINE �Iterations

n�1�IINton

(n� Step)� VOUT� tON(delay)� , switching losses at FET turn-on. (38)

PCOSS�12� COSS� VOUT

2� fS , COSS loss. (39)

PGATE� QOFF� VGS(max)� fS , FET gate loss. (40)

PRDS(on)� IFET(rms)� RDS(on) , FET RDS(on) loss (41)PFET� PSWITCH(toff)� PSWITCH(ton)� PCOSS� PGATE� PRDS(on)� 5 W (42)

Design Review

To estimate FET turn-on (tON(delay)) and turn off (tOFF(delay)) delays requires studying the FETs VGS versusQG characteristics of Figure 6 along with the following equations.

Figure 6.

, is the amount of gate charge when the FET VGS is at its maximum VGS(max).

The estimated FET loss (PFET) for this design was 5 W. The total FET loss would be 10 W and with the1.2 W total diode loss comes to a total semiconductor loss of 11.2 W, which is below the 19 W powerbudget (PSEMI) that was initially set.



www.ti.com

3.6 Selecting Heat Sinks for the FETs

R�SA�TJ(max)�

34� TAMB� PFET�R�JC� R�CS�

PFET�

16.6OCW (43)

3.7 Over Voltage Protection and Under Voltage Lockout

3.8 Peak Current Limit

a�NPNS�

VPVS�

ISIP�

150 (44)

IPEAK� �POUT� 2

�

2� Vin(min)� ��IL1

2�� 1.3

(45)

RSENSE�

VC�0.5 V2

IPEAK� a , this equation takes into account slope compensation that is added later. (47)

IPEAK(startup)� 2� IPEAK (48)

3.9 Current Sense Transformer Reset Resistor (T1 and T2)

RRESET�

VC�0.5 V2

IPEAK� �1� DMIN(LL)�� a (49)

3.10 Oscillator and Maximum Duty Cycle Clamp

KOSC� �2.04� 1010��

s , UCC28220 oscillator constant. (50)

FOSC� 2� fS , UCC28220 internal oscillator frequency. (51)

FOSC� 2� fS , internal duty cycle clamp. (52)

Design Review

Because the diodes only dissipated 0.6 W heat sinks were not required for the boost diodes. However, theFETs required heat sinks and the following equation was used to calculate the thermal impedance (RθSA)of the required heat sink. This equation is based on a maximum allowable ambient temperature (TAMB) of40°C, and the thermal impedance from junction to case Rθjc of the IR840 and the case to sink thermalimpedance of a TO220 (RθCS) which all can be found in the IRF840’s data sheet. For this design wechose an AAVID 531202 heat sink to meet the RθSA requirements.

The OVP function and under voltage lockout (UVLO) were handled by the UCC28220. It is a simplecomparator that monitors the boost voltage. Information on setting up these thresholds can be found in theUCC28220’s data sheet. The OVP for this design was set to 425 V and UVLO was set to 108 V. Thepre-regulator will not start switching until VOUT reaches 108 V.

Peek current limit is set by the maximum control voltage (VC) at the input of the UCC28220’s PWMcomparator. Where “a” is the current sense transformer turns ratio of T1 and T2. The peak current limit trippoint was set for 130% of the nominal peak current to protect the boost FETs.

VC = 1.8, VCTRL was set to a maximum of 3.0 V to protect the UCC28220 CTRL pin. (46)

The peak current of the FET during power up is 2 times IPEAK under normal operation. This is due theexcessive slope compensation that is needed for stability.

The UCC28220’s oscillator and maximum duty cycle clamp are setup through resistor RCHG anddischarge. The desired duty cycle clamp (DMAX) was set at 0.9 to stop the current sense transformers fromsaturating.



www.ti.com

DMAX(osc)� 1� 2�1� DMAX� (53)

RDISCHG� KOSC

�1� DMAX(osc)�

FOSC (54)

3.11 Control Loop Compensation

3.12 Current Loop

RIAC�VIN(max)� 2

�

500 �A (55)

RVFF�1.5 V

Vin(min)2�RIAC

� 0.9(56)

fP1� fLINE�1.5%66% (57)

CVFF�1

2� �� RVFF� fP1 (58)

TC(s)� GID(s)�GCA(s) , current loop transfer function. (59)

GID(s)��IL1�IC

�

VOUT� RSENSE� a

s� L1� VC1 , control to output current transfer function. (60)

GCA(s)��IC�IL1

�

�s� RZB� CZA� 1�

s� RMO� �CZB� CPB�� s�CZB�CPBCZB�CPB

� RZB� 1�

� HCNTRL� HCA

(62)

Design Review

All the control equations for the voltage loop and current loop are estimates. The control equations in thispaper gives starting points for feedback compensation. In most control loops it is required to adjust theloop compensation as necessary with a network analyzer.

The first step in setting up the current loop is setting up the multiplier components. The RIAC resistor is tiedto the rectified line voltage and is what forces the current amplifier output to track changes in the linevoltage. This resistance typically is a group of series resistors needed to meet the high voltagerequirements.

The multiplier internal to the UCC28528 has a voltage feed forward (VFF) function that keeps the powerstage gain constant and provides soft power limiting when the line drops keeping the line current fromincreasing excessively. A detailed explanation can be found in TI/Unitrode application note SLUA196A.The VFF signal is produced through an internal current mirror within the PFC controller. The maximumcurrent leaving the VFF pin is equal to one half the IAC current. The following equations are used to selecta VFF resistor (RVFF) and a filter capacitor (CVFF) to remove ac components from the VFF signal.

The VFF signals ac portion has an affect on total current harmonic distortion (THD). The filter’s pole (fp1)is set at a frequency to limit the VFF contribution to 1.5% in order to meet the power supplies current THDdesign requirements.

This control methodology is based on average and peak current mode control and the following formulasto compensate the current loop. These calculations get the design close to the correct compensation andwill have to be fine tuned with a network analyzer. In this design example to compensate the current loop(TC(s)) we set a design goal of 45 degrees of phase margin and a crossover frequency of one tenth theswitching frequency.

VC1 = VC - 0.5 V, VC1 is the maximum control voltage at the input of the PWM comparator of the UCC28220. NoteEquation VC1 takes into account the 500 mV offset that is present in the UCC28220 PWM controller. (61)

The current amplifier compensation transfer function GCA(s) is as follows



www.ti.com

HCNTRL��VC

�VCTRL� 0.6

, internal divider of the UCC28220 CTRL pin. (63)

HCA��VCTRL�VCA(out)

�

RDRC� RD

� 0.594(64)

RSLOPE� 0.1 V��1� DMIN(LL)�

10 pF��IL�a�RSENSE

2 (65)

PFCRSENSE�VSENSE

POUT� 2�

VIN(min)�� (66)

RMO�

POUT� 2��1.1�PFCRSENSEVIN(min)��

2�VIN(min)� 2�

RIAC

�

VR(sense)2� IAC

(67)

RZB�

1

�GID�2��j�fS10�� RMO

HCA� HCNTRL , resistor RZA is set to force TC(s) to cross over at (fS/10). (68)

CZB�1

2� �� RZB� �fs10�

, capacitor CZB is adjusted to put a zero at frequency crossover. (69)

CPB�1

2� �� RZB� �fs2�

, capacitor CPB is used to attenuate high frequency noise. (70)

3.13 Voltage Loop (TV(s))

TV(s)� GVD(s)�GVA(s) (71)

Design Review

The voltage divider HCA was required to divide down the CA output of the UCC28528, to protect the CTRLpin of the UCC28220. This divider should work fine for any power requirement and should be considered afixed variable.

For stability the current sense signal needs slope compensation. It is required to add at least half of theinductor current down slope to the current sense signal. The UCC28220 has internal slope compensationthat is setup by resistor RSLOPE.

The UCC28528 needed a current sense resistor (PFCRSENSE) to monitor the input current. Calculating thisresistor value is based on allocating a maximum allowable current sense voltage (VSENSE).

The UCC28528 also uses the current sense signal to trigger power limiting. The power limit can be setupby properly selecting the multiplier resistor RMO. The power limit was set to 110% of full load power.Please refer to the UCC28528s data sheet for details on how this power limiting function works. Thepower limit was set at 110% as not to interfere with the UCC28220’s peak current limit function which wasset at 130%.

Putting a zero at loop crossover adds an additional 45 degrees of phase at crossover to ensure controlloop stability.

Compensating the voltage loop has two major constraints. First is attenuating the 2 x fLINE output capacitorvoltage ripple, this is required to reduce input current harmonic distortion. Second is control loop stability.If either of these criteria is compromised PF and THD will be affected greatly.



www.ti.com

GVD(s)��VOUT�VC

�

POUT�

VC2� s� COUT� VOUT , voltage control to output transfer function. (73)

H1�RB

RB� RA�

VREFVOUT

�7.5 VVOUT , this divider can also be used to set up the RA and RB voltage divider. (75)

GVA(s)� H1� gm�s� RZA� CZA� 1

s� RMO� �CZA� CPA�� s�CZA�CPACZA�CPA

� RZA� 1�(76)

RZA�

1�GV�2��j�fC��

H1� gm (77)

CZA�1

2� �� fC� RZA , CZA is set at fC to give the voltage loop 45 degrees of added phase at crossover. (78)

CPA�1

2� �� 2� fLINE�� VC�0.015

VRIPPLE�

1H1�gm�

, is sized to attenuate the output ripple voltage. (79)

Design Review

VC2 = 5.5 V, maximum voltage amplifier (VA) output. (72)

gm = 100 umho, trans-conductance voltage amplifier (VA) gain. (74)

To ensure that this loop would have low harmonic distortion the loop was designed to crossover (fC) at 10Hz.

After the critical parameters were calculated the power supply was constructed and evaluated. The finaldesign of the 350-W two phase interleaved PFC is shown in the schematics of Figure 7 and Figure 8. Thispower supply also has a 2-W auxiliary power supply that is based on a discontinues current mode (DCM)flyback topology.



www.ti.com

4 Schematic

++

+

1N

/C2

INA

3G

ND

4IN

B5

OU

TB

6V

DD

7O

UTA

8N

/CU

CC

2732

4DU

4

Schematic

Figure 7. 350-W Interleaved PFC Boost Pre-Regulator Schematic



www.ti.com

+

Schematic

Figure 8. 2-W, Flyback and PFC/PWM Controller Schematic



www.ti.com

5 Design Performance

−40

−32

−24

−16

−8

0

8

16

24

32

40

Gai

n−dB

−180

−144

−108

−72

−36

0

36

72

108

144

180

Pha

se−D

egre

es

Phase

Gain

TC(f) Current Loop Frequency ResponseVIN = 238 V DC, POUT = 350 W

100 1000 10000 100000

Frequency

100

Frequency

1000 10000 10000

−32

−24

−16

−8

0

8

16

24

32

40

Gai

n−dB

−180

−144

−108

−72

−36

0

36

72

108

144

180

Pha

se−D

egre

es

Phase

Gain

TC(f) Current Loop Frequency ResponseVIN = 120 V DC, POUT = 350 W

t − Time − 5 ms/div .

10 mV/div .

Output Ripple V oltage,POUT = 350 W

Design Performance

The current loop TC(s) was measured with a network analyzer and did not exactly track the modelpresented above. The TC(s) gain moved with input voltage and appeared to have a double pole around 30kHz. This is probably due to the excessive slope compensation that this topology requires. However, thecurrent loop was stable and did not have to be adjusted. Note to measure the current loop or voltage looprequires a dc input voltage, otherwise the line current and voltage affects the loop measurements. Anetwork analyzer with a low enough frequency range was not available to measure the voltage loop.

Figure 9. Figure 10.

Figure 11.



www.ti.com

5.1 Input Inductor Ripple Current Cancellation

t − Time − 5 ms/div.

CH1: 250 V/div .Rectified Line

Voltage

CH2: 20 mV/div .L1 Current


CH4: 20 mV/divInput Current

Input Inductor Ripple Current Cancellationat VIN = 85 V RMS, POUT = 350 W

t − Time − 10 µs/div.

CH1: 100 V/div .Rectified Line

Voltage



CH4: Input Current

Inductor Ripple Current Cancellationat VIN = 85 V RMS and POUT = 350 W

1

4

2

3


H1: 250 V/div .Rectified Line

Voltage



CH4: 20 mV/div .Input Current

Input Inductor Ripple Current Cancellationat VIN = 265 V RMS, POUT = 350 W

Design Performance

Figure 12 shows the inductor ripple current cancellation at the peak of line with a minimum input of 85 VRMS. From this graph it can be observed that the input current (CH4) is 1/2 the individual inductor ripplecurrents of L1 (CH2) and L2 (CH3). The ratio of input ripple current to inductor ripple current agrees withgraph in Figure 2. Note that the current ratio is 0.225 A/mV in the following graphs.

Figure 13.Figure 12.

Figure 14.



www.ti.com

5.2 Transient Response


CH2: VOUT100 V/div.

CH1: 100 V/div . Rectified Line

Line Transients at 350-W Load, V INStepped from 240 V to 120 V to 240 V


CH4: VOUT500 V/div.

CH3: IIN20 mV/div .

Startup No Load and V IN = 85 V


CH2: VOUT100 V/div.

CH1: 100 V/div . Rectified Line

Line Dropout at Full Load


CH4: VOUT500 V/div.

CH3: IIN20 mV/div .

Startup at V IN = 85 V, POUT = 350 W

Design Performance

The voltage loop of a PFC pre-regulator is generally below 10 Hz, which means the fastest the voltageloop can respond to a small transient is roughly 100 ms. In typical applications a PFC pre-regulator takes5 to 10 times as long to recover from a transient response. However, a large signal comparator built intothe UCC28528 control device allowed the design to recover from large signal transient responses in lessthan 200 ms.





www.ti.com

VIN = 85 V

VIN = 265 V

100908070605040302089

90

91

92

93

94

95

96

97

POUT − Output Power − %

Effi

cien

cy −

%EFFICIENCY

vsOUTPUT POWER

10090807060504030200.88

0.90

0.92

0.94

0.96

1.00

POUT − Output Power − %P

F

PF vs

OUTPUT POWER

0.98

VIN = 85 V

VIN = 265 V

0.00007

0.77313

1.54620

2.31927

3.09234

3.86540

4.63847

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 45 48 50

Harmonic

Am

plitu

de −

A

CURRENT HARMONICSVIN = 85 V, POUT = 350 W

0.00002

0.23643

0.47283

0.70923

0.94564

1.18204

1.41845

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

Harmonic

Am

plitu

de −

A

CURRENT HARMONICSVIN = 265 V, POUT = 350 W

6 Conclusion:

Conclusion:


Figure 21. Figure 22.

By interleaving boost pre-regulator stages enables the power supply designer to reduce boost inductorarea product by 50% and reduce boost capacitance RMS current. This allows the designer to reduce thesize of the PFC pre-regulator; as well as, use output filter capacitors with lower RMS ratings.

In high power applications interleaving PFC pre-regulators would be a good choice, where many boostFETs and boost diodes would be required for the design. In these applications the only added cost wouldbe adding the additional control circuitry that is needed to accomplish interleaving.



IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265

Copyright © 2007, Texas Instruments Incorporated

http://amplifier.ti.comhttp://dataconverter.ti.comhttp://dsp.ti.comhttp://interface.ti.comhttp://logic.ti.comhttp://power.ti.comhttp://microcontroller.ti.comhttp://www.ti.com/lpwhttp://www.ti.com/audiohttp://www.ti.com/automotivehttp://www.ti.com/broadbandhttp://www.ti.com/digitalcontrolhttp://www.ti.com/militaryhttp://www.ti.com/opticalnetworkhttp://www.ti.com/securityhttp://www.ti.com/telephonyhttp://www.ti.com/videohttp://www.ti.com/wireless

1 Abstract2 Review the Benefits of Interleaving PFC Boost Pre-Regulators2.1 Input Ripple Current Reduction as a Function of Duty Cycle2.2 Evaluate Magnetic Volume Reduction2.3 Output Capacitor Ripple Current Reductions as a Function of Duty Cycle

3 Design Review3.1 Boost Inductor Selection3.2 Output Capacitor Selection (COUT)3.3 FET and Diode Selection3.4 Diode Selection3.5 FET Selection Based on RMS and Peak Currents and Estimated FET Losses3.6 Selecting Heat Sinks for the FETs3.7 Over Voltage Protection and Under Voltage Lockout3.8 Peak Current Limit3.9 Current Sense Transformer Reset Resistor (T1 and T2)3.10 Oscillator and Maximum Duty Cycle Clamp3.11 Control Loop Compensation3.12 Current Loop3.13 Voltage Loop (TV(s))

4 Schematic5 Design Performance5.1 Input Inductor Ripple Current Cancellation5.2 Transient Response

6 Conclusion

350-w,two-phaseinterleaved pfc pre-regulatordesign...

Documents