3.1 積體電路層
DESCRIPTION
3.1 積體電路層. ρ:resitivity, σ:conductivity, Rs:Sheet Resistance. R=ρ(L/A)=(1/σ)(L/Wt)=(1/σt)=ρ/t=Rs (L=W). Rl=Rs*n ; n=L/W. C=ε ox (wl/Tox), ε ox =3.9ε o ;ε o =8.854*10 -14 F/cm. 3.2 MOSFET. n n =N d -N a ;P p =N a -N d. np =n i 2 (mass-action law) Ex3.1;3.2(P.3-14,15). - PowerPoint PPT PresentationTRANSCRIPT
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Introduction to VLSI Circuits and Systems
第 3 章 Physical Structure of CMOS Integrated Circuits3.1 積體電路層
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第 3 章 Physical Structure of CMOS Integrated Circuits
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R=ρ(L/A)=(1/σ)(L/Wt)=(1/σt)=ρ/t=Rs (L=W)
ρ:resitivity, σ:conductivity, Rs:Sheet Resistance
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第 3 章 Physical Structure of CMOS Integrated Circuits
Rl=Rs*n ; n=L/W
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C=εox(wl/Tox), εox=3.9εo ;εo=8.854*10-14 F/cm
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3.2 MOSFET
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np=ni2 (mass-action law) Ex3.1;3.2(P.3-14,15)
σ=q(unn+upp)=1/ρ, σ:conductivity, u:mobility
nn=Nd-Na ;Pp=Na-Nd
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第 3 章 Physical Structure of CMOS Integrated Circuits
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Cox=εox/tox ; CG=CoxAG ;Ex3.3(p.3-21)
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第 3 章 Physical Structure of CMOS Integrated Circuits
Rn=1/βn(VG-Vtn)
βn=unCox(W/L)
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第 3 章 Physical Structure of CMOS Integrated Circuits
Rp=1/β p(VG-|Vtp|)
βp=upCox(W/L)
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第 3 章 Physical Structure of CMOS Integrated Circuits
C 之效應
1. Time Delay
2. Power Dissipation
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Ee=CV2/2 ; P=i2R
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第 3 章 Physical Structure of CMOS Integrated Circuits
Layers: 1. P-sub( 基板 ) 2. n-well( 井區 ) 3. Gate Oxide
4.Gate(poly-Si) 5.n+ 6.p+ 7.Contact 8.Metal
FOX: Field Oxide 場氧化物3.3CMOS 各層
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第 3 章 Physical Structure of CMOS Integrated Circuits
1. M1~M5 間以 SiO2 隔離 ; M1~M5 間以 Via 連結( 銅 )
2. 元件用 Contact 與外面 M1 作連結 ( 材質 :W鎢 )
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第 3 章 Physical Structure of CMOS Integrated Circuits
3.4 設計 FET 陣列
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IC Design:CMOS Inverter
Metal 1, AlCu
P-Epi
P-Wafer
N-WellP-Well
PMD
p + p +n +n +
W
Metal 1Contact
P-well N-well Polycide gate and local interconnection
N-channel active region N-channel VtN-channel LDDN-channel S/D
P-channel active region P-channel VtP-channel LDDP-channel S/D
Shallow trench isolation (STI)
NMOS PMOS
Vin
Vout
STI
(a)
(b)
(c)
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CMOS inverter layout Mask 1, N-well Mask 2, P-well
Mask 3, shallow trench isolation Mask 4, 7, 9, N-Vt, LDD, S/D Mask 5, 8, 10, P-Vt, LDD, S/D
Mask 6, gate/local interconnection Mask 11, contact Mask 12, metal 1
IC Design: Layout and Masks of CMOS Inverter
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第 3 章 Physical Structure of CMOS Integrated Circuits
1. VDD ,VSS 使用 Metal 連接
2. n+ 與 p+ 差別 ;p+ 有 well
3. Metal 與 n+ 或 p+ 連接必須使用 Contact
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Bugs? 6 errors
F=BAR(xy+zw)
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F=?
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第 3 章 Physical Structure of CMOS Integrated Circuits
Exercise (P3-46)
• 1,2,3,5,6,8,10,11,12,13,14,15,16,18,19
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