EE547B ASSIGNMENT1Spring 15Due: 4/29/15

Student Name: AVINASH REDDY GOPU CIN: 304393159

Total: 15 Points

Problem 1: Write Back/ Write Invalidate Protocol (4 points)

Consider the MSI snooping protocol described in the text. The three states are encoded as follows:

Invalid: 00 Shared: 01 Modified: 10

Assume that there are three processors interconnected by a bus. Each processor has 2 cache lines with 4 words per line. There are 8 cache blocks in the centralized shared memory space. Assume also that the direct mapping scheme is used, i.e., Memory blocks A, C, E, G will be mapped to the top cache line, and Memory blocks B, D, F, H will be mapped to the bottom cache line if the corresponding processor accesses such blocks.

1) Refer to Figure 1. If the following event occurs, what will be the changes based onthe snooping cache coherence protocol? (You can make all the changes on the figure)(2 points)

P1: reads from A[2]

2) Refer to Figure 2. If the following event occurs, what will be the changes based on the snooping cache coherence protocol? (2 points)

P2: writes to B[3]=171

Cache0

S Tag W

01 A 0

2

4

8

10 B 4

5

8

9

P0

Cache1

S Tag W

01 A 0

2

4

8

00

P1

Cache2

STagW

00C8

10

12

14

01F20

21

22

23

2P2

Cache0

S Tag W

01 A 0

1

2

3

00 B 4

5

8

9

P0

Cache1

S Tag W

01 A 0

1

2

3

00

P1

Cache2

S Tag W

10 C 8

10

12

14

10 B 4

5

8

17

P24

Problem 2: Directory-Based Cache Coherence Protocol (4 points)

Consider the directory-based cache coherence protocol as follows.

This scheme combines the advantages of both write-through and write-back invalidation. In order to reduce bus traffic, only the very first write of a cache block uses a write- through policy. If a cache block is written more than once, it applies a write-back policy. There are four states in this protocol:

Uncached (Stage 00): The block is not found in the cache.

Valid (Stage 01): The cache block, which is consistent with the memory copy, has been read from shared memory and has not been modified.

Reserved (Stage 10): Data has been written exactly once since it has been read from shared memory. The cache copy is consistent with the memory copy, which is the only other copy. (Write-through policy applies.)

Dirty (Stage 11): The cache block has been modified (written) more than once, and the cache copy is the only one in the system (thus inconsistent with all other copies). (Write-back policy applies).

1) Reference to Figure 3. Each block contains four words (e.g. A1 contains A1[0], through A1[3]) Make all the changes on this figure after the following event occurs. Show all messages needed for the memory access (2 points) ( Assuming direct mapping)

P3 reads the number from B2[2].

2)Reference to Figure 4. Make all the changes on this figure after the following event occurs. Show all messages needed for the memory access (2 points) ( Assuming direct mapping)

P3 writes the number 12 to C3[2].C1

M1

P1

C2

M2

P2

C3

M3

P3

Figure 3 5

C1

M1

P1

C2

M2

P2

C3

M3

P36

Problem 3: (3 points)

7

8

Answer :a) P0: read 120 : Read Miss, Satisfied by memoryP0: read 128 : Read Miss, Satisfied by P1 CacheP0: read 130 : Read Miss, Satisfied by memory and write back 110Implementation 1: 100 + 40 + 10 + 100 + 10 = 260 stall cyclesImplementation 2: 100 + 130 + 10 + 100 + 10 = 350 stall cycles b) P0: read 100 : Read Miss, Satisfied by memoryP0: write 108 48 : Write hit, send invalidateP0: write 130 78 : Write miss satisfied by memory and write back 110Implementation 1: 100+15+10+100=225 stall cyclesImplementation 2: 100+15+10+100=225 stalls cyclesc) P1: read 120: Read Miss Satisfied by MemoryP1: read 128: Read hitP1: read 130: Read Miss Satisfied by memoryImplementation 1: 100+0+100=200 stall cyclesImplementation 2: 100+0+100=200 stall cycles d) P1: read 100: Read Miss Satisfied by memoryP1: write 108: 48 Write miss satisfied by memory and write back 128P1: write 130: 78 Write miss satisfied by memory Implementation 1: 100+100+10+100=310 stall cycles Implementation 2: 100+100+10+100=310 stall cycles

Problem 4: (4 points)

11

Answer:Writeback block; abort memory access

Invalid

s u bn o ss im etirw ecal

Write miss or invalidate for this block

CPU read

Shared

CPU read hit

Write miss this block

Invalidate for this block

Write miss for this block

PUrirte

Read miss

CP Plac bus

Place read miss on bus

U writee invaliP

Writeback block;abort memory

date on

Modified

CPU write hitCPU read hit

Writeback block; abort memory access

CPU writePlace invalidate on bus

owned

CPU read hit

Protocol Diagram

Answer: P0: read 110: Read Miss P0s cacheP3: read 110: Read Miss, MSI satisfies in memory, MOSI satisfy in P0s cacheP0: read 110: Read HitMSI: 40+10+100+0=150 stall cyclesMOSI: 40+10+40+10=100 stall cycles P0: read 120: Read miss satisfied in memoryP3: read 120: Read hitP0: read 120: Read miss satisfied in memoryBoth Protocols=100+100+0= 200 stall cycle P0: write 120 80: Write miss invalidate at P3P3: read 120: Read miss P0s cacheP0: read 120: Read hitBoth Protocols: 100+40+10+0=150 stall cycles P0: write 10888: Send Invalidate, Invalidate P3P3: read 108: Read Miss P0s cacheP0: write 108 98: Send Invalidate, Invalidate P3Both Protocols=15+40+10+15=80 stall cycles