3-tap fir filter optimizations
DESCRIPTION
3-Tap FIR Filter Optimizations. By: Jeff Rybczynski CMPE 222. 3-Tap FIR Filter Design. FIR Filter Control. Six States meaning 3 bit State Variable Each Multiply is in a separate state Asynchronous Reset. FIR Filter Data Path. 3 Independent Multiply Operations - PowerPoint PPT PresentationTRANSCRIPT
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3-Tap FIR Filter 3-Tap FIR Filter OptimizationsOptimizations
By: Jeff Rybczynski
CMPE 222
Monday, June 02, 2003
FIR Optimization – Jeff Rybczynski
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3-Tap FIR Filter Design3-Tap FIR Filter Design
Monday, June 02, 2003
FIR Optimization – Jeff Rybczynski
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FIR Filter ControlFIR Filter Control
Six States meaning 3 bit State Variable
Each Multiply is in a separate state
Asynchronous Reset
Monday, June 02, 2003
FIR Optimization – Jeff Rybczynski
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FIR Filter Data PathFIR Filter Data Path
3 Independent Multiply Operations
3 Independent Addition Operations
Not order dependent
Monday, June 02, 2003
FIR Optimization – Jeff Rybczynski
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Optimized FIR ControlOptimized FIR Control
Take out extra calculate steps and place all the multiplies in one CALC state
Add the values from the multiply step together in ADD state Place value directly into result before you raise output_ready
Monday, June 02, 2003
FIR Optimization – Jeff Rybczynski
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Changes to the Verilog CodeChanges to the Verilog Code
3'b100 : begin output_ready <= 1'b0; rin <= sample; end 3'b110 : acc <= rin * 24'h702a78; 3'b111 : acc <= rs0 * 24'h800000 + acc; 3'b101 : acc <= rs1 * 24'h4fd547 + acc; 3'b001 : begin output_ready <= 1'b1;
result <= acc; rs1 <= rs0; rs0 <= rin; end default : begin acc <= 24'h000000; output_ready <= 1'b0; end
• Original Verilog Code
Monday, June 02, 2003
FIR Optimization – Jeff Rybczynski
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Changes to the Verilog CodeChanges to the Verilog Code
• Optimized Code
2'b00 : begin output_ready <= 1'b0; rin <= sample; end
2'b10 : begin temp1 <= rin * 24'h702a78;temp2 <= rs0 * 24'h800000;temp3 <= rs1 * 24'h4fd547;
end2'b11 : begin
result <= temp1 + temp2 + temp3;rs1 <= rs0; rs0 <=rin;output_ready <=1’b1 end
2'b01 : output_ready <= 1'b0;
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FIR Optimization – Jeff Rybczynski
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Array MultiplierArray Multiplier
Similar to how you multiply by hand Cascading Array multiplier blocks
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FIR Optimization – Jeff Rybczynski
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Array Multiplier BlockArray Multiplier Block
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Array MultiplierArray Multiplier0
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
0 0 00 0 0 0
A3=1 A2=0 A1=1 A0=1
B0=1
B1=0
B2=1
B3=1
1 0 1 1
0 0 0 0
1 0 1 1
1 0 1 1
1 0 1 10 0 0 00
0
0
0 1 0 10 0 0 0
1 0 0 10 0 1 0
1 1 0 10 0 1 0
A BCO CI
S
A BCO CI
S
A BCO CI
S
A BCO CI
S
0
1111
0
0
0
0
1
0
1
1
0
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FIR Optimization – Jeff Rybczynski
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Add Array Multiplier to Add Array Multiplier to Verilog CodeVerilog Code
New Code:
array_multi a(temp1,rin, 24'h702a78);array_multi b(temp2,rs0, 24'h800000);array_multi c(temp3,rs1, 24'h4fd547);
Old Code:temp1 <= rin * 24'h702a78;temp2 <= rs0 * 24'h800000;temp3 <= rs1 * 24'h4fd547;
Monday, June 02, 2003
FIR Optimization – Jeff Rybczynski
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FIR DesignsFIR Designs
Area Time
Original FIR Design 77182.453125 9.77 ns
Optimized FIR 3 Latency 76806.578125 9.61 ns
Optimized FIR Array Multiplier 91060.187500 9.73 ns