3 rd sem record
TRANSCRIPT
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EXP NO: 01 DATE:
BINARY ADDERS
AIM
To develop the VHDL source code for binary addersa. Half adder b. Full adder
c. 4-bit parallel adder and obtain the simulation.
ALGORITHM
Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Check the syntax and debug the errors if found, obtain the synthesis report.Step4: Verify the output by simulating the source code.
BASIC ADDERS
HALF ADDER
VHDL SOURCE CODE
Dataflow Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hadd is
Port ( a : in std_logic;
b : in std_logic;sum : out std_logic;carry : out std_logic);
end hadd;architecture dataflow of hadd isbeginsum
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architecture Behavioral of haddbehavioral isbeginp1:process (a,b)beginsum
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entity xor2 isPort ( a : in std_logic;
b : in std_logic;z : out std_logic);
end xor2;architecture dataflow of xor2 isbeginz
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FULL ADDER
VHDL SOURCE CODE
Dataflow Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fadd_dataflow is
Port ( a : in std_logic;
b : in std_logic;c : in std_logic;sum : out std_logic;carry : out std_logic);
end fadd_dataflow;architecture dataflow of fadd_dataflow is
signal p,q,r,s:std_logic;begin
p
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t:= c and a;sum
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architecture dataflow of and2 isbeginz
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4-BIT PARALLEL ADDER (Binary adder):
VHDL SOURCE CODE
Structural Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;entity rca is
Port ( a : in std_logic_vector(3 downto 0);b : in std_logic_vector(3 downto 0);c : in std_logic;s : out std_logic_vector(3 downto 0);cout : out std_logic);
end rca;architecture structural of rca is
component fadd_behvport(a,b,c:in std_logic;sum,carry:out std_logic);end component;
signal c0,c1,c2:std_logic;begin
f1:fadd_behv port map (a(0),b(0),c,s(0),c0);f2:fadd_behv port map (a(1),b(1),c0,s(1),c1);f3:fadd_behv port map (a(2),b(2),c1,s(2),c2);f4:fadd_behv port map (a(3),b(3),c2,s(3),cout);
end structural;
fadd_behv component source code:
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library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fadd_behv is
Port ( a : in std_logic;b : in std_logic;c : in std_logic;sum : out std_logic;
carry : out std_logic);end fadd_behv;architecture Behavioral of fadd_behv isbeginp1:process(a,b,c)variable r,s,t:std_logic;beginr:= a and b;s:= b and c;t:= c and a;sum
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RESULT
Thus the OUTPUTs of Binary adders are verified and simulating the VHDL code.
EXP NO: 02 DATE:
MULTIPLEXERAIM
To develop the VHDL source code for multiplexer and obtain the simulation.
ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Check the syntax and debug the errors if found, obtain the synthesis report.Step4: Verify the output by simulating the source code.
VHDL SOURCE CODE
Dataflow Modeling:
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library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux_dataflow is
Port ( d : in std_logic_vector(3 downto 0);s : in std_logic_vector(1 downto 0);y : out std_logic);
end mux_dataflow;architecture dataflow of mux_dataflow issignal s0bar,s1bar,p,q,r,st:std_logic;begin
p
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Y : out STD_LOGIC);end mux1;
architecture Behavioral of mux1 is
beginwith S select Y
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z:out std_logic);end component;component and3
port(a,b,c:in std_logic;z:out std_logic);
end component;component or4
port(a,b,c,d:in std_logic;z:out std_logic);
end component;signal s0bar,s1bar,p,q,r,st:std_logic;begin
n1:not1 port map (s(0),s0bar);n2:not1 port map (s(1),s1bar);a1:and3 port map (d(0),s0bar,s1bar,p);a2:and3 port map (d(1),s0bar,s(1),q);a3:and3 port map (d(2),s(0),s1bar,r);a4:and3 port map (d(3),s(0),s(1),st);o1:or4 port map (p,q,r,st,y);
end structural;
and3 component source code:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and3 is
Port ( a : in std_logic;b : in std_logic;c : in std_logic;z : out std_logic);
end and3;architecture dataflow of and3 isbegin
z
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use IEEE.STD_LOGIC_UNSIGNED.ALL;entity or4 is
Port ( a : in std_logic;b : in std_logic;c : in std_logic;d : in std_logic;z : out std_logic);
end or4;architecture dataflow of or4 is
beginz
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ALGORITHMStep1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Check the syntax and debug the errors if found, obtain the synthesis report.Step4: Verify the output by simulating the source code.
VHDL SOURCE CODE
Dataflow Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux_dataflow is
Port ( d : in std_logic;s : in std_logic_vector(1 downto 0);z : out std_logic_vector(3 downto 0));
end demux_dataflow;architecture dataflow of demux_dataflow is
signal s0bar,s1bar:std_logic;begin
s0bar
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z(0)
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port(a,b,c:in std_logic;z:out std_logic);
end component;signal s0bar,s1bar:std_logic;begin
n1:not1 port map (s(0),s0bar);n2:not1 port map (s(1),s1bar);a1:and3 port map (d,s0bar,s1bar,z(0));a2:and3 port map (d,s0bar,s(1),z(1));
a3:and3 port map (d,s(0),s1bar,z(2));a4:and3 port map (d,s(0),s(1),z(3));
end structural;
and3 component source code:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and3 is
Port ( a : in std_logic;b : in std_logic;
c : in std_logic;z : out std_logic);
end and3;architecture dataflow of and3 isbegin
z
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Simulation output:
Synthesis RTL Schematic:
RESULT
Thus the OUTPUTs of Demultiplexer is verified and simulating the VHDL code.
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EXP NO: 04 DATE:
DECODERS
AIM
To develop the source code for decoders by using VHDL and obtain the simulation.
ALGORITHM
Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Check the syntax and debug the errors if found, obtain the synthesis report.Step4: Verify the output by simulating the source code.
VHDL SOURCE CODE
Dataflow Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity decoder_dataflow is
Port ( a : in std_logic;b : in std_logic;e : in std_logic;z : out std_logic_vector(3 downto 0));
end decoder_dataflow;architecture dataflow of decoder_dataflow is
signal abar,bbar:std_logic;
beginabar
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p1:process(a,b)begin
if (e='1') thenz(0)
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component not1port(a:in std_logic;
z:out std_logic);end component;
signal abar,bbar:std_logic;begin
n1:not1 port map (a,abar);n2:not1 port map (b,bbar);a1:nand3 port map (abar,bbar,e,z(0));
a2:nand3 port map (abar,b,e,z(1));a3:nand3 port map (a,bbar,e,z(2));a4:nand3 port map (a,b,e,z(3));
end structural;
nand3 component source code:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity nand3 is
Port ( a : in std_logic;
b : in std_logic;c : in std_logic;z : out std_logic);
end nand3;architecture dataflow of nand3 isbegin
z
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Synthesis RTL Schematic:
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RESULT
Thus the OUTPUTs of Decoder is verified and simulating the VHDL code.
EXP NO: 05 DATE:
ENCODER
AIM
To develop the source code for encoder by using VHDL and obtain the simulation.
ALGORITHM
Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Check the syntax and debug the errors if found, obtain the synthesis report.Step4: Verify the output by simulating the source code.
ENCODER
VHDL SOURCE CODE
Dataflow Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity encoder_dataflow is
Port ( d : in std_logic_vector(7 downto 0);z : out std_logic_vector(2 downto 0));
end encoder_dataflow;architecture dataflow of encoder_dataflow isbegin
z(2)
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Behavioral Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity encoder_behv is
Port ( d : in std_logic_vector(7 downto 0);e : in std_logic;
z : out std_logic_vector(2 downto 0));end encoder_behv;architecture Behavioral of encoder_behv isbegin
p1:process(d,e)begin
if (e='1') thencase d is
when "10000000"=>zzzzzzzzz
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use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity or4 is
Port ( a : in std_logic;b : in std_logic;c : in std_logic;d : in std_logic;z : out std_logic);
end or4;
architecture dataflow of or4 isbegin
z
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RESULTThus the OUTPUTs of Encoder is verified and simulating the VHDL code.
EXP NO: 06 DATE:
LATCHES AND FLIP FLOPS
AIM
To develop the VHDL source code fora. D latchb. D flip flop
c. JK flip flop and obtain the simulation.
ALGORITHM
Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Check the syntax and debug the errors if found, obtain the synthesis report.Step4: Verify the output by simulating the source code.
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D LATCH
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dlatch isPort ( D : in STD_LOGIC;
clk : in STD_LOGIC;Q : inout STD_LOGIC;Qbar : out STD_LOGIC);
end dlatch;
architecture Behavioral of dlatch is
beginprocess(clk)
beginif (clk='1')thenQ
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Synthesis RTL Schematic:
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D FLIPFLOP:
VHDL SOURCE CODE
Behavioral Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dff is
Port ( d : in std_logic;clk : in std_logic;rst : in std_logic;q : inout std_logic;qbar : inout std_logic);
end dff;
architecture Behavioral of dff isbegin
process(d,clk,rst,q,qbar)begin
if (rst='1') thenq
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Synthesis RTL Schematic:
JK FLIPFLOP:
VHDL SOURCE CODE
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity jkff is
Port ( j : in std_logic;k : in std_logic;clk : in std_logic;rst : in std_logic;q : inout std_logic;qbar : inout std_logic);
end jkff;architecture Behavioral of jkff isbegin
process(j,k,clk,rst,q,qbar)begin
if (rst='1') thenq
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q
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RESULT
Thus the OUTPUTs of Latches and Flip Flops are verified and simulating the VHDL code.
EXP NO: 07 DATE:
SHIFT REGISTERSAIM
To develop the VHDL source code for shift register and obtain the simulation.
ALGORITHM
Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Check the syntax and debug the errors if found, obtain the synthesis report.Step4: Verify the output by simulating the source code.
SERIAL-IN SERIAL-OUT SHIFT REGISTER:
VHDL SOURCE CODE
Behavioral Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity siso is
Port ( d : in std_logic;
clk : in std_logic;rst : in std_logic;q : out std_logic);
end siso;architecture Behavioral of siso is
signal x:std_logic_vector(7 downto 0);begin
process(d,clk,rst)begin
if (rst='1') thenq
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end Behavioral;
Simulation output:
Synthesis RTL Schematic:
SERIAL IN PARALLEL OUT SHIFT REGISTER:
VHDL SOURCE CODE
Behavioral Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity sipo is
Port ( d : in std_logic;clk : in std_logic;rst : in std_logic;q : inout std_logic_vector(7 downto 0));
end sipo;architecture Behavioral of sipo isbegin
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process(d,clk,rst)begin
if (rst='1') thenq
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use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity pipo is
Port ( d : in std_logic_vector(7 downto 0);clk : in std_logic;rst : in std_logic;q : out std_logic_vector(7 downto 0));
end pipo;architecture Behavioral of pipo is
beginprocess(d,clk,rst)begin
if (rst='1') thenq
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PARALLEL-IN SERIAL-OUT SHIFT REGISTER:
VHDL SOURCE CODE
Behavioral Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity piso is
Port ( d : in std_logic_vector(7 downto 0);clk : in std_logic;rst : in std_logic;load : in std_logic;q : out std_logic);
end piso;architecture Behavioral of piso isbegin
process(d,clk,rst,load)variable x:std_logic_vector(7 downto 0);
beginif (clk='1' and clk'event) then
if (rst='1') then
q
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x(4):=x(5);x(5):=x(6);x(6):=x(7);x(7):='Z';
end if;end if;
end if;end process;
end Behavioral;
Simulation output:
Synthesis RTL Schematic:
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UNIVERSAL REGISTER
VHDL SOURCE CODE
Behavioral modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity usrg8 isPort ( D : in STD_LOGIC_VECTOR (7 downto 0);
mode : in STD_LOGIC_VECTOR (2 downto 0);Dsl : in STD_LOGIC;
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Dsr : in STD_LOGIC;clk : in STD_LOGIC;pl : in STD_LOGIC;e : in STD_LOGIC;y : out STD_LOGIC_VECTOR (7 downto 0));
end usrg8;
architecture Behavioral of usrg8 issignal z:std_logic_vector(7 downto 0);
begin
process(clk,e,pl)begin
If(e='0') thenIf(pl='1') then
If(clk'event and clk='1') thencase conv_integer(mode) is
when 0 => z z z z z z z null ;end case;
end if;else z
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SYNCHRONOUS COUNTER:
VHDL SOURCE CODE
Structural Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity syncounter is
Port ( clk : in std_logic;rst : in std_logic;q : inout std_logic_vector(3 downto 0));
end syncounter;architecture structural of syncounter is
component tffport(t,clk,rst:in std_logic;
q,qbar:inout std_logic);end component;component and2port(a,b:in std_logic;
z:out std_logic);end component;
signal x1,x2:std_logic;signal x3,x4,x5,x6:std_logic:='Z';begin
t1:tff port map ('1',clk,rst,q(0),x3);t2:tff port map (q(0),clk,rst,q(1),x4);t3:tff port map (x1,clk,rst,q(2),x5);t4:tff port map (x2,clk,rst,q(3),x6);
a1:and2 port map (q(0),q(1),x1);a2:and2 port map (x1,q(2),x2);
end structural;
tff component source code:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity tff is
Port ( t : in std_logic;clk : in std_logic;
rst : in std_logic;q : inout std_logic;qbar : inout std_logic);
end tff;architecture Behavioral of tff isbegin
process(t,clk,rst,q,qbar)begin
if (rst='1') thenq
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qbar
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ASYNCHRONOUS COUNTER:
VHDL SOURCE CODE
Structural Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity asyncounter is
Port ( clk : in std_logic;rst : in std_logic;q : inout std_logic_vector(3 downto 0));
end asyncounter;architecture structural of asyncounter is
component tffport(t,clk,rst:in std_logic;q,qbar:inout std_logic);end component;
signal x1,x2,x3:std_logic;signal x4:std_logic:='Z';begin
t1:tff port map ('1',clk,rst,q(0),x1);t2:tff port map ('1',x1,rst,q(1),x2);t3:tff port map ('1',x2,rst,q(2),x3);t4:tff port map ('1',x3,rst,q(3),x4);
end structural;
tff component source code:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity tff is
Port ( t : in std_logic;
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clk : in std_logic;rst : in std_logic;q : inout std_logic;qbar : inout std_logic);
end tff;architecture Behavioral of tff isbegin
process(t,clk,rst,q,qbar)begin
if (rst='1') thenq
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EXP NO: 09 DATE:
MINI PROJECT
8-TAP FIR FILTER
AIM
To develop the VHDL source code for 8-TAP FIR FILTER and obtain the simulation.
ALGORITHM
Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Check the syntax and debug the errors if found, obtain the synthesis report.Step4: Verify the output by simulating the source code.
VHDL SOURCE CODE
Structural Modeling:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity DELAY isPort( D: in std_logic_vector(7 downto 0);
CLK : in std_logic;Q,QN: out std_logic_vector(7 downto 0));
end DELAY;
architecture DELAY of DELAY ISbegin
process(CLK)begin
if (CLK'event and CLK = ?1?)then Q
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Entity adder_16bit isGeneric (len : integer := 16);
Port (A,B : in std_logic_vector(15 downto 0);SUM : out std_logic_vector(16 downto 0));
End adder_16bit;
Architecture adder_16bit of adder_16bit isSignal C : std_logic_vector(16 downto 0);Signal S : std_logic_vector(15 downto 0);
Signal Cout : std_logic;
Component onebit FAPort (A,B,Cin : in std_logic; SUM,Cout: out std_logic);End component;
BeginC(0)
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Signal C : std_logic_vector(18 downto 0);Signal S : std_logic_vector(17 downto 0);Signal Cout : std_logic;
Component onebit FAPort (A,B,Cin : in std_logic; SUM,Cout: out std_logic);End component;
BeginC(0)
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End component;
BeginD0 : DELAY port map(x,CLK,x0,x0_bar);D1 : DELAY port map(x0,CLK,x1,x1_bar);D2 : DELAY port map(x1,CLK,x2,x2_bar);D3 : DELAY port map(x2,CLK,x3,x3_bar);D4 : DELAY port map(x3,CLK,x4,x4_bar);D5 : DELAY port map(x4,CLK,x5,x5_bar);
D6 : DELAY port map(x5,CLK,x6,x6_bar);D7 : DELAY port map(x6,CLK,x7,x7_bar);
M0 : mul_8X8 port map(x0,h0,p0);M1 : mul_8X8 port map(x1,h1,p1);M2 : mul_8X8 port map(x2,h2,p2);M3 : mul_8X8 port map(x3,h3,p3);M4 : mul_8X8 port map(x4,h4,p4);M5 : mul_8X8 port map(x5,h5,p5);M6 : mul_8X8 port map(x6,h6,p6);M7 : mul_8X8 port map(x7,h7,p7);
A0 : adder_16bit port map (p0,p1,s0);
A1 : adder_16bit port map (p2,p3,s1);A2 : adder_16bit port map (p4,p5,s2);A3 : adder_16bit port map (p6,p7,s3);A4 : adder_16bit port map (s0,s1,s4);A5 : adder_16bit port map (s2,s3,s5);A6 : adder_16bit port map (s4,s5,y);
End FIR_filter
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RESULT
Thus the OUTPUTs of 8 TAP FIR FILTER are verified and simulating the VHDL code.
EXP NO:10 DATE:
BASIC MATHEMATICAL OPERATIONS
AIM
To develop the 8051 Assembly language code for basic mathematical operations
d. Addition.
e. Subtraction.
f. Division.
g. Multiplication.
h. Multibyte Addition/
i. Addition of .series of 8 bit number.
j. Matrix Addition.
PROGRAMS
;************ Program description
;8 bit unsigned addition using register addressing
;R2 = NUM1; R3 = NUM2
;R4 = LSB, R5 = MSB
;************ Constants
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START: CLR A
MOV R4,A ;clear result vars
MOV R2,#20
MOV R3,#30 ;LOAD VALUES IN REGISTER
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MOV A,R2
ADD A,R3
JNC NOOFLOW
INC R5
NOOFLOW: MOV R4,A
SJMP $ ;Control stays here
END
;************ Program description
;16 bit Add
;************ Constants
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START:
MOV R6,#1Ah ;Load the first value into R6 and R7
MOV R7,#44h ;Load the second value into R4 and R5
MOV R4,#22h
MOV R5,#0DBh
LCALL ADD16_16 ;Call the 16-bit addition routine
SJMP $ ;Control stays here
ADD16_16:
;Step 1 of the process
MOV A,R7 ;Move the low-byte into the accumulator
ADD A,R5 ;Add the second low-byte to the accumulator
MOV R3,A ;Move the answer to the low-byte of the result
;Step 2 of the process
MOV A,R6 ;Move the high-byte into the accumulator
ADDC A,R4 ;Add the second high-byte `to the accumulator, plus carry.
MOV R2,A ;Move the answer to the high-byte of the result
;Step 3 of the process
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MOV A,#00h ;By default, the highest byte will be zero.
ADDC A,#00h ;Add zero, plus carry from step 2.
MOV R1,A ;Move the answer to the highest byte of the result
RET ;Return - answer now resides in R1, R2, and R3.
END
;************ Program description
;8 bit unsigned addition using register addressing
;R2 = NUM1; R3 = NUM2
;R4 = LSB, R5 = MSB
;************ Constants
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START: CLR A
MOV R4,A ;CLEAR RESULT
MOV R2,#20
MOV R3,#30 ;LOAD VALUES IN REGISTER
MOV A,R2
ADD A,R3
JNC NOOFLOW
INC R5
NOOFLOW: MOV R4,A
SJMP $ ;CONTROL STAYS HERE
END
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************ Program description
;16 bit SUB
;************ Constants
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START:
MOV R6,#22h ;Load the first value into R6 and R7
MOV R7,#0DBh ;Load the second value into R4 and R5
MOV R4,#1Ah
MOV R5,#0F9h
LCALL SUBB16_16 ;Call the 16-bit SUb routine
SJMP $ ;Control stays here
SUBB16_16:
;Step 1 of the process
MOV A,R7 ;Move the low-byte into the accumulator
CLR C ;Always clear carry before first subtraction
SUBB ;Subtract the second low-byte from the accumulator
MOV R3,A ;Move the answer to the low-byte of the result
;Step 2 of the process
MOV A,R6 ;Move the high-byte into the accumulator
SUBB A,R4 ;Subtract the second high-byte from the accumulator
MOV R2,A ;Move the answer to the low-byte of the result
RET ;Return - answer now resides in R2, and R3.
END
;************ Program description
;8 bit Division using register addressing
;R2 = NUM1; R3 = NUM2
;R4 = LSB, R5 = MSB
;************ Constants
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;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START:
MOV R2,#4
MOV R3,#2
MOV A,R3
MOV R4,A ;LOAD VALUES IN REGISTER
MOV A,R2
LOOP2:
SUBB A,R3
JC LOOP1
INC R5
DJNZ R4, LOOP2
SJMP LOOP3
LOOP1: INC R5
LOOP3: MOV R6,A
SJMP $ ;Control stays here
END
*********** Program description
;16 bit Multiplication
;************ Constants
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START:
MOV R6,#62h ;Load the first value into R6 and R7
MOV R7,#30h
MOV R4,#43h ;Load the first value into R4 and R5
MOV R5,#2Eh
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LCALL MUL16_16 ;Call the 16-bit subtraction routine
SJMP $
MUL16_16:
;Multiply R5 by R7
MOV A,R5 ;Move the R5 into the Accumulator
MOV B,R7 ; Move R7 into B
MUL AB ;Multiply the two values
MOV R2,B ; Move B (the high-byte) into R2
MOV R3,A ;Move A (the low-byte) into R3
;Multiply R5 by R6
MOV A,R5 ;Move R5 back into the Accumulator
MOV B,R6 ;Move R6 into B
MUL AB ;Multiply the two values
ADD A,R2 ;Add the low-byte into the value already in R2
MOV R2,A ;Move the resulting value back into R2
MOV A,B ;Move the high-byte into the accumulator
ADDC A,#00h ;Add zero (plus the carry, if any)
MOV R1,A ;Move the resulting answer into R1
MOV A,#00h ;Load the accumulator with zero
ADDC A,#00h ;Add zero (plus the carry, if any)
MOV R0,A ;Move the resulting answer to R0.
;Multiply R4 by R7
MOV A,R4 ;Move R4 into the Accumulator
MOV B,R7 ;Move R7 into B
MUL AB Multiply the two values
ADD A,R2 ;Add the low-byte into the value already in
R2
MOV R2,A ; Move the resulting value back into R2
MOV A,B ;Move the high-byte into the accumulator
ADDC A,R1 ;Add the current value of R1 (plus any carry)
MOV R1,A ;Move the resulting answer into R1.
MOV A,#00h ;Load the accumulator with zero
ADDC A,R0 ;Add the current value of R0 (plus anycarry)
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MOV R0,A ; Move the resulting answer to R1.
;Multiply R4 by R6
MOV A,R4 ;Move R4 back into the Accumulator
MOV B,R6 ;Move R6 into B
MUL AB ;Multiply the two values
ADD A,R1 Add the low-byte into the value already in R1
MOV R1,A ;Move the resulting value back into R1
MOV A,B ;Move the high-byte into the accumulator
ADDC A,R0 ;Add it to the value already in R0 (plus any carry)
MOV R0,A ; Move the resulting answer back to R0
RET ;Return - answer is now in R0, R1, R2, and
R3
END;
************ Program description
;8 bit Multiply using register addressing
;R2 = NUM1; R3 = NUM2
;R4 = LSB, R5 = MSB
;************ Constants
ORG 0x0000
LJMP START
ORG 0X0040
START:
MOV R0,#00h ;Load the first value into R0 and R1
MOV R1,#0B3h
MOV R2,#08h ;Load the first value into R3 and R2
MOV R3,#00h
LCALL div16_16 ;Call the 16-bit DIV routine
SJMP $
div16_16:
CLR C ;Clear carry initially
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MOV R4,#00h ;Clear R4 working variable initially
MOV R5,#00h ;CLear R5 working variable initially
MOV B,#00h ;Clear B since B will count the number of left-shifted
bits
div1:
INC B ;Increment counter for each left shift
MOV A,R2 ;Move the current divisor low byte into the
accumlator
RLC A ;Shift low-byte left, rotate through carry to apply highest bit
to high-byte
MOV R2,A ;Save the updated divisor low-byte
MOV A,R3 ;Move the current divisor high byte into the accumulator
RLC A high, rotating in carry from low-byte
MOV R3,A ;Save the updated divisor high-byte
JNC div1 Repeat until carry flag is set from high-byte
div2: ;Shift right the divisor
MOV A,R3 ;Move high-byte of divisor into accumulator
RRC A ;Rotate high-byte of divisor right and into carry
MOV R3,A ;Save updated value of high-byte of divisor
MOV A,R2 ;Move low-byte of divisor into accumulator
RRC A ;Rotate low-byte of divisor right, with carry from high-byte
MOV R2,A ;Save updated value of low-byte of divisor
CLR C ;Clear carry, we don't need it anymore
MOV 07h,R1 ;Make a safe copy of the dividend high-byte
MOV 06h,R0 ;Make a safe copy of the dividend low-byte
MOV A,R0 ;Move low-byte of dividend into accumulator
SUBB A,R2 ;Dividend - shifted divisor = result bit (no factor, only 0 or 1)
MOV R0,A ;Save updated dividend
MOV A,R1 ;Move high-byte of dividend into accumulator
SUBB A,R3 ;Subtract high-byte of divisor (all together 16-bit substraction)
MOV R1,A ;Save updated high-byte back in high-byte of divisor
JNC div3 ;If carry flag is NOT set, result is 1
MOV R1,07h ;Otherwise result is 0, save copy of divisor to undo subtraction
MOV R0,06h
div3:
CPL C ;Invert carry, so it can be directly copied into result
MOV A,R4
RLC A ;Shift carry flag into temporary result
MOV R4,A
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MOV A,R5
RLC A
MOV R5,A
DJNZ B,div2 ;Now count backwards and repeat until "B" is zero
MOV R3,05h ;Move result to R3/R2
MOV R2,04h ;Move result to R3/R2
RET
END
;************ Program description
;8 bit unsigned addition of series of numbers using indirect addressing
;INPUT LOCATION 41 to 4F,40 -number of digits, OUTPUT LOCATION 50 & 51
;;************ Constants
Input EQU 0x40
Result EQU 0x50
ResMsb EQU 0x30
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START: MOV A,#0
MOV ResMsb,A ;INITIALISE TEMP VARIABLES
MOV R0,#Input ;INITIALISE POINTERS
MOV R1,#Result
ACALL InitInputs ;INITIALISE MEMORY LOCATION
MOV A,@R0 ;INITIALISE COUNTER, R2 IS USED AS COUNTER
MOV R2,A
INC R0
CLR A ;CLEAR ACCUMULATOR TO STORE RESULT
ADD_AGAIN: ADD A,@R0
JNC NOOFLOW
INC ResMsb ;increment if carry occurs
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NOOFLOW: INC R0
DJNZ R2,ADD_AGAIN
MOV @R1,A ;STORE LSB IN RESULT LOCATION
INC R1
MOV @R1,ResMsb ;STORE MSB IN RESULT LOCATION
SJMP $ ;Control stays here
;FUNCTION TO LOAD VALUE AT MEMORY LOCATION
InitInputs: MOV @R0,#8 ;8 numbers to be added
MOV A,@R0 ;INITIALISE COUNTER
MOV R2,A
INC R0
DO_AGAIN: MOV @R0,#50 ;LOAD 50 IN TO MEMORY LOCATION
INC R0
DJNZ R2,DO_AGAIN
MOV R0,#Input ;INITIALISE POINTERS
RET
END
********** Program description
;8 bit unsigned addition using register addressing
;R2 = NUM1; R3 = NUM2
;R4 = LSB, R5 = MSB
;************ Constants
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START: CLR A
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MOV R4,A ;clear result vars
MOV R2,#20
MOV R3,#30 ;LOAD VALUES IN REGISTER
MOV A,R2
ADD A,R3
JNC NOOFLOW
INC R5
NOOFLOW: MOV R4,A
SJMP $ ;Control stays here
END
;************ Program description
;8 bit unsigned addition of series of numbers using indirect addressing
;INPUT LOCATION 41 to 48 - Array1, 50 to 58 - Array2, 60 to 68 results
;************ Constants
Array1 EQU 0x40 ;Array address
Array2 EQU 0x50
ResArray EQU 0x60
AddResult EQU 0x30
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START: MOV R0,#Array1 ;INITIALISE POINTERS
MOV R1,#Array2
MOV R3,#ResArray ;
ACALL InitInputs ;INITIALISE MEMORY LOCATION
MOV R2,#9 ;INIT COUNTER
ADD_AGAIN: MOV A,@R0 ;INITIALISE COUNTER, R2 IS USED AS COUNTER
ADD A,@R1
INC R0
INC R1
MOV AddResult,A ;STORE RESULT TEMPORARILY
MOV A,R3
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XCH A,R0
MOV @R0,AddResult
INC R3
XCH A,R0
DJNZ R2,ADD_AGAIN
SJMP $ ;Control stays here
;FUNCTION TO LOAD VALUE AT MEMORY LOCATION
InitInputs: MOV A,#1
MOV R2,#9 ;9 numbers to be added
REFILL: MOV @R0,A ;INITIALISE DATA
MOV @R1,A
INC A
INC R0
INC R1
DJNZ R2,REFILL
MOV R0,#Array1 ;INITIALISE POINTERS
MOV R1,#Array2
RET
END
RESULT
Thus the 8051 Assembly language code for basic mathematical operations was developed.
EXP NO:11 DATE:
SMALLEST AND LARGEST NUMBER
AIM
To develop the 8051 Assembly language code for find Smallest and largest number in given Array of
number.
PROGRAM
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;************ Program description
;8 bit unsigned addition of series of numbers using indirect addressing
;INPUT LOCATION 41 to 4F,40 -number of digits, OUTPUT LOCATION 50 & 51
;;************ Constants
Input EQU 0x40
Result EQU 0x50
Big EQU 0x30
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START: MOV A,#0
MOV Big,A ;INITIALISE TEMP VARIABLES
MOV R0,#Input ;INITIALISE POINTERS
MOV R1,#Result
ACALL InitInputs ;INITIALISE MEMORY LOCATION
MOV A,@R0 ;INITIALISE COUNTER, R2 IS USED AS COUNTER
MOV R2,A
INC R0
CLR C
CHK_AGAIN: MOV A,@R0
SUBB A,Big
JC OOFLOW
MOV Big,@R0 ;Small = A, if carry occurs
OOFLOW: INC R0
DJNZ R2,CHK_AGAIN
MOV @R1,Big ;STORE LSB IN RESULT LOCATION
SJMP $ ;Control stays here
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;FUNCTION TO LOAD VALUE AT MEMORY LOCATION
InitInputs: MOV @R0,#8 ;8 numbers to be processed
MOV A,@R0 ;INITIALISE COUNTER
MOV R2,A
INC R0
MOV A,#20
DO_AGAIN: MOV @R0,A ;LOAD 20,21... IN TO MEMORY LOCATION
INC A
INC R0
DJNZ R2,DO_AGAIN
MOV R0,#Input ;INITIALISE POINTERS
RET
END
RESULT
Thus the 8051 Assembly language code for find Smallest and largest number in given Array of number was
developed.
EXP NO: 12 DATE:
COUNT THE NUMBER OF EVEN AND ODD NUMBERS
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AIM
To develop the 8051 Assembly language code to count the Number of Even and odd numbers in given Array
of number.
PROGRAM
;************ Program description
;8 bit unsigned addition of series of numbers using indirect addressing
;INPUT LOCATION 41 to 4F,40 -number of digits, OUTPUT LOCATION 50 & 51
;50 - even numbers, 51 - oddnumbers
;R3 - even numbers,R4 - odd nubers
;************ Constants
Input EQU 0x40
Result EQU 0x50
EvenNum EQU 0x30
OddNum EQU 0x31
;************ variable declaration
ORG 0x0000
LJMP START
ORG 0X0040
START:
MOV A,#0
MOV EvenNum,A ;INITIALISE TEMP REGISTERS
MOV OddNum,A
MOV R0,#Input ;INITIALISE POINTERS
MOV R1,#Result
ACALL InitInputs ;INITIALISE MEMORY LOCATION
MOV A,@R0 ;INITIALISE COUNTER, R2 IS USED AS COUNTER
MOV R2,A
INC R0
CLR C
CHK_AGAIN:
MOV A,@R0
RRC A
JNC EVEN
INC OddNum ;ODD COUNT INCREMENTED
SJMP AGAIN
EVEN: INC EvenNum ;EVEN COUNT INCREMENTED
AGAIN: INC R0
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DJNZ R2 ,CHK_AGAIN
MOV @R1,EvenNum ;STORE LSB IN RESULT LOCATION
INC R1
MOV @R1,OddNum ;STORE LSB IN RESULT LOCATION
SJMP $ ;Control stays here
;************ FUNCTION TO LOAD VALUE AT MEMORY LOCATION **********************
InitInputs: MOV @R0,#8 ;8 numbers to be processed
MOV A,@R0 ;INITIALISE COUNTER
MOV R2,A
INC R0
MOV A,#20
DO_AGAIN: MOV @R0,A ;LOAD 20,21... IN TO MEMORY LOCATION
INC A
INC R0
DJNZ R2,DO_AGAIN
MOV R0,#Input ;INITIALISE POINTERS
RET
END
RESULT
Thus the 8051 Assembly language code to count the Number of Even and odd numbers in given Array
of number was developed.
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EXP NO:13 DATE:
TO FIND THE POSITIVE AND NEGATIVE NUMBER
AIM
To develop the 8051 Assembly language code to Find the Positive and Negative number .
PROGRAM
;************ Program description
;CHECKS THE GIVEN NUMBER IS ODD OR EVEN using indirect addressing
;INPUT LOCATION 40,OUTPUT LOCATION 41 = 0, if POSITIVE else 41 = 1
;************ Constants
Input EQU 0x40
;************ variable declaration
ORG 0x0000
LJMP STARTORG 0X0040
START:
MOV R0,#Input ;INITIALISE POINTERS
MOV @R0,#31 ;LOAD DATA IN MEMORY
CLR C
MOV A,@R0
INC R0
RLC A
JC NEGATIVE
MOV @R0,#0 ;NUMBER IS POSITIVE
SJMP DONE
NEGATIVE: MOV @R0,#1 ;NUMBER IS NEGATIVE
DONE: SJMP $ ;Control stays here
END
RESULT
Thus the 8051 Assembly language code to Find the Positive and Negative number was developed .
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EXP NO:14 DATE:
SORTING OF NUMBER
AIM
To develop the 8051 Assembly language code to Sort the number in Ascending and descending order.
PROGRAM
ASCENDING
ORG 00h
;-----------------------------------Data Required for the Program------------------------------------
MOV R4,#04h ;Counter for LOOP1
MOV 50h,#0x05
MOV 51h,#0x03MOV 52h,#0x02
MOV 53h,#0x04
;----------------------------Sort in Ascending Order Using Bubble Sort-------------------------------
LOOP1: ;Outer Loop - Handles number of passes
MOV R0, #03h
MOV R1,#50h ;Point to beginning of array
MOV A, R0 ;Initialize R0 - the counter for LOOP2
MOV R3, A ;to the value of R0 - the number of iterations in each pass is
same
;as the number of elements minus serial number of the current pass.
LOOP2: ;Inner Loop - Handles each pass.
MOV A, @R1 ;Copy a number of the array to the accumulator
MOV R3, A ;and store it in R3.
INC R1 ;Move to the net number
MOV A, @R1 ;and store that in the accumulator.
SUBB A, R3 ;Subtract the first from the second.
JNC Continue2 ;If no carry is generated the second is greater and the numbers
are ;in order with respect to each other. Otherwise they must
be swapped.
MOV A, @R1 ;Move the second number to the accumulator.
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XCH A, R3 ;Exchange contents of the accumulator and R3. This makes A
contain the first number and R1 the second.
MOV @R1, A ;Store the first number at the place where the second one was
stored.
DEC R1 ;Move to the previous memory location.
MOV A, R3 ;Copy the second number to the accumulator
MOV @R1, A ;and store it in the first number's place.
INC R1 ;Move to the next memory location.
Continue2:
DJNZ R0, LOOP2 ;Move on to the next iteration of the current pass.
Continue1:
DJNZ R4, LOOP1 ;Move on to the next pass.
Here: SJMP Here ;End of program - Loop here indefinitely.
END
;----------------------------------------------------------------------------------------------------
DESENDING
;----------------------------------------------------------------------------------------------------ORG 00h
;-----------------------------------Data Required for the Program------------------------------------
MOV R4,#04h ;Counter for LOOP1
MOV 50h,#0x02
MOV 51h,#0x04
MOV 52h,#0x03
MOV 53h,#0x05
;----------------------------Sort in Desending Order Using Bubble Sort-------------------------------
LOOP1: ;Outer Loop - Handles number of passes
MOV R0, #03h
MOV R1,#50h ;Point to beginning of array
MOV A, R0 ;Initialize R1 - the counter for LOOP2
MOV R3, A ;to the value of R0 - the number of iterations in each pass is
same
as the number of elements minus serial number of the current pass.
LOOP2: ;Inner Loop - Handles each pass.
MOV A, @R1 ;Copy a number of the array to the accumulator
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MOV R3, A ;and store it in R2.
INC R1 ;Move to the net number
MOV A, @R1 ;and store that in the accumulator.
SUBB A, R3 ;Subtract the first from the second.
JC Continue2
;If no carry is generated the second is greater and the numbers
are
in order with respect to each other. Otherwise they must be swapped.
MOV A, @R1 ;Move the second number to the accumulator.
XCH A, R3 ;Exchange contents of the
accumulator and R2. This makes A contain the first number
and R2 the second.
MOV @R1, A ;Store the first number at the place where the second one was
stored.
DEC R1 ;Move to the previous memory location.
MOV A, R3 ;Copy the second number to the accumulator
MOV @R1, A ;and store it in the first number's place.
INC R1 ;Move to the next memory location.
Continue2:
DJNZ R0, LOOP2 ;Move on to the next iteration of the current pass.
Continue1:
DJNZ R4, LOOP1 ;Move on to the next pass.
Here:
SJMP Here ;End of program - Loop here indefinitely.
END
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RESULT
Thus the 8051 Assembly language code to Sort the number in Ascending and descending order was
developed.