2.sys bus arch

7/29/2019 2.Sys Bus Arch

1/14

DigitalDe

signSec2.BusArchitectur

e

B

y:Dr.S.Th

ayaparan

Slidecontentsarefromthefollowingsourceoforigin:

1.http://en.wikipedia.org

/wiki/Bus_(computing)

2.http://www.arm.com/p

roducts/system-ip/amba/index.php

3.http://en.wikipedia.org

/wiki/Advanced_M

icrocontroller_Bus_Architecture

4.http://www.arm.com/images/Tools_Flow_

Large.jpg

5.http://www.arm.com/p

roducts/system-ip/amba-design-tools

/index.php

6.http://www.cl.cam.ac.u

k/teaching/0910/S

ysOnChip/sp6busn

oc/index.html

Busisasubsyste

mthat

transfersdatabe

tween

Background

AComputerSystem

Buscomponents

Thetechniquew

as

developedtored

uce

costsandimprov

e

modularity

2


2/14

Firstgenerationbusesare8-bitparallelbuse

s

Secondgenerationbuses

are16or32bitpa

rallelbuses

Bussy

stemslikePCI,PCIExpressareusedin

Computers

Buses

canbe:

Background

AComput

erSystem

Bus

.

-

2.S

erialbuses-Carry

datainbit-serialfo

rm(eg.USB,FireW

ire,andSerialATA)

Mostcomputershavebothinternalandexternalbuses.

Aninternalbus(localbus)connectsalltheinternalcomponentsofacomputerto

the

mothe

rboard(andthus,theCPUandinternalmemory)

Anexternalbusconnectsexternalperipheralstothemotherbo

ard

Netwo

rkconnectionssuc

hasEthernetaren

otgenerallyregard

edasbuses

Thirdgenerationbuseshavebeenemerging

intothemarketsinceabout2001,inc

luding

H

erTransortandInfin

iBand.

3

NewtechnologiessuchasInfiniBand(Serial)andHyperTransport(auto-negotiate

dbit

width,rangingfromtwo-

to32-linkintercon

nects)isfurtherblurringtheboundaries

betwe

ennetworksandbuses

InfiniB

andisintendedto

replacebothinternalbuseslikePCIaswellasexternaloneslike

FibreChannel

USBservesasaperipheralbus

ICcan

beusedasbotha

ninternalbus,ora

nexternal(access)

bus

Background

PCIvsPCI

ExpressBu

ses

PCI(PeripheralComponentInterconnect

)isalocalbus,designedbyIntelin19

92

PCIisaninterconnectionsystembetweenamicroprocessor

andattacheddevices

.

microprocessordesign

PCIisaparallelbusan

dittransmits32bitsatatimeina12

4-pinconnection(t

he

ext

rapinsareforpow

ersupplyandgrou

nding)and64bitsina188-pinconnection

PCIusesallactivepathstotransmitboth

addressanddatasignals,sendingthe

addressononeclockcycleanddataonthenext

InPCI,burstdatacan

besentstartingwithanaddressonth

efirstcycleanda

seq

uenceofdatatran

smissionsonacertainnumberofsuccessivecycles

PCIExpress(PCIe)isd

evelopedin2002a

nditisatwo-way,

serialconnectionthat

4

car

riesdatainpacketsalongtwopairsofpoint-to-pointdatalanes

PCIedoublesthedata

transferratesoforiginalPCI


3/14

ASampleBusA

rchitecture

FigureshowssometypicalexampleofI/Odevice

sthat

mightbea

ttachedtoexpansiondevices.Thetra

ditional

busconnectionusesthreebu

ses(i)localbus,(ii

)

systembusand(iii)expansion

bus

1.Localbu

sconnectstheprocessortocacheme

mory

andmaysupportoneormore

localdevices

2.Thecach

ememorycontrollerconnectsthecacheto

localbusandtothesystembus.

3.Systembusalsoconnectsm

ainmemorymodu

le

4.Input/ou

tputtransfertoan

dfromthemainm

emory

acrossthe

systembusdonot

interfacewiththe

processoractivitybecauseprocessaccessescach

e

memory.

Thisarrangementallowsthe

systemtosupport

awidevarietyofi/odevicesand

atthesametime,insulatethememorytoprocessortrafficfromi/otraffic.

5.ItispossibletoconnectIO

controllersdirectlyonto

thesystem

bus.Anefficients

olutionistomakeuseof

expansion

busforthispurpos

e

6.Anexpa

nsionbusinterface

buffersdatatransfer

betweensystembusandi/oc

ontrollerontheex

pansion

bus.

5

Bas

icBuswith1Initiatorand3Ta

rget

6


4/14

Bas

icBuswith2Initiatorand3Ta

rget

7

BridgedBus

Structures

8


5/14

S

oCDesign-AnExample

9

BlockDiagramofaMulti-C

ore`platform'chip

,usedinanumberofNetworkingProducts

ReusableIPs

10


6/14

Bus

DesignParameter

1.BusType:Dedicatedor

multiplexed

2.Arbitration:Centralized

ordistributed

3.Timing:SynchronousorAsynchronous

4.Buswidth:Address,data

.

,

,

,

,

Bus

DesignParameterindetails

1.BusType:

i)De

dicatedbus:busis

permanentlyassig

nedonly1function

E.g.separateaddressan

ddatalines;separ

atebusformemoryandI/Omodules

Adva

ntage:Itgiveshigh

performanceand

lessbuscontention

Disadvantage:Increase

dsizeandcost.

ii)Multiplexedbus:busisusedformoret

han1funcionindifferenttimezones

E.g.8085microprocessoroutputsA7-A0infirstclockcycleso

npinsAD7AD0.

Adva

ntages:fewpinslinesarerequired.L

owcostandsaved

esignspace

Disadvantages:slowin

speed

11

2.BusA

rbitration:

Severalbusmastersconnectedtoacommo

nbusmayrequire

accesstothebusa

tthe

same

time.Aselectionmechanismcalledb

usarbitrationdescribeswhichdevice

shouldbegivenaccesstothebus

i)Cen

tralizedapproach:Ahardwaredevice

calledbuscontrollerorbusarbiter

alloca

tesbus.Itusesone

ofthefollowingtype

(1)Daisychaining

(Forexample,A-B-C-D-E-A:Aloop)

(2)Polling

(3)Multipleprioritylevels

ii)Dis

tributedApproach

:Eachmasterhasarbitercomparedtoonlysinglein

centralizedapproach.Eq

ualresponsibilityisgiventoalldevice

stocarryoutarbitration

,

3.BusTim

ing:

i)synchronoustiming:E

veryeventissynch

ronizedbythecloc

k

ii)asy

nchronoustiming:Everyeventoccurringdependsonpreviouseventsofthebus.

12


7/14

4.Buswidth:

Itdec

idesthenumberoflinestobeusedfo

raddressanddata

.Moreaddressline

s

mean

smorememorycanbeaccessed.e.g16lineaddresscan

access216=64KB

ofData

locationswhere20addresslinecanaccess220=1MBofDatalocations.

More

datalinesmeansm

orenumberofbitscanbetransferredatatime.Therefore

speed

increases.

.

Abu

scansupportvario

ustypeofdatatransfer

1)Fo

rmultiplexedbus:

a)Writeoperatio

n:dataissentimm

ediatelyaftersend

ingtheaddress

b)Readoperation:Firstaddressissent,thensufficient

timeisgiventoaddressed

devicetooutputthedata.Then,

thedataisreadfro

mthebus

c)Readmodifyw

rite:Readdatatransferisfollowedby

writedatatransferatthe

sameaddress.

Itstopsothercpu

tousethebus.

d)Readafterwrite:Writertransferisfollowedwithrea

dtransferaftersom

e

accesstime.It

isusedtocheckth

edatawrite;used

forcheckingpurpo

se.

e)Blockoperation:Numberofdata

aretransferredatt

hesameaddressoneafter

another.e.g.savingfileinsecondarystorage

2)Fornon-multiplexedbus:

Addre

ssanddataoutputtedatthesametim

eondifferentbus

.Itisafastersyste

m.13

Syst

emBusSta

ndardsfor

SOC,ASIC

AMBA4.0byARMLt

d(Mainly32,64,128Bitparallelbus)

STBusbySTMicroele

ctronics(Buswid

thisprogrammable,parallelbus)

-

-

from

Silicore)

IBM

CoreConnectbu

stechnology,use

dinPowersystems,butalsoinmany

othe

rSoCslikesystem

swiththeXilinx

MicroBlazeorsimilarcores

IPBu

sByIntegratedDeviceTechnolog

y(IDT)

Alte

raAvalon-propr

ietarybussystem

forAlterasNios

II-SoCs

Note:

14

1.Open

Coresistheworld'slargestopensourcehardwarecomm

unitydeveloping

digitalopensourcehard

warethroughelec

tronicdesignautom

ation,withasimilar

ethostothefreesoftwa

removement

2.Open

Coreshopestoeliminateredundantdesignworkandsla

shdevelopment

costs

3.Anumberofcompanies

havebeenreporte

dasadoptingOpe

nCoresIPinchips


8/14

Sy

stemBusS

tandardsforComput

ers

S

-100bus

U

nibus

V

AXBI

HPPrecisionBus

EISA

VME

InfiniBand

UPA

PCI-X

M

bus

S

TDBus

S

MBus

Q

-Bus

ISA

Z

orroII

Z

orroIII

C

AMAC

VXI

NuBus

TURBOchannel

MCA

Sbus

VLB

PCI

PXI

AGP

PCIExpress

IntelQuickPathInterconnect

HyperTransport

15

F

ASTBUS

L

PC

HPGSCbus

CoreConnect

Adva

ncedMicrocontroller

BusArchit

ecture(AM

BA)

AM

BAwasintroducedbyARMLtdin

1996

Itis

widelyaccepted

inindustryasas

ystembusinterc

onnect

AM

BAiswidelyusedonarangeofASICandSoCparts

including

a

lications

rocessorsusedinmode

rnortablemobiledeviceslike

smartphones

Firs

tAMBAbuseswereAdvancedSystemBus(ASB)an

dAdvanced

PeripheralBus(APB)

Inits2ndversion,AM

BA2,ARMaddedAMBAHigh-pe

rformanceBus(A

HB)

thatisasingleclock-edgeprotocol

In2

003,ARMintroducedthe3rdgeneration,AMBA3,

includingAXIto

reachevenhigherperformanceinterconnectandtheA

dvancedTraceB

us

16

aspartote

ore

gton-c

p

eugantrace

souton

The

seprotocolsaretodaythede-fact

ostandardfor32

-bitembedded

pro

cessorsbecausetheyarewelldocumentedandcan

beusedwithout

royalties

Imp

ortantaspectof

aSoCisnotonly

itscomponentsb

utalsohowthey

are

inte

rconnected


9/14

AMBAisawidelyaccep

tedsolutionforth

eblockstointerfac

ewitheachother

ObjectiveoftheAMBA

specificationisto:

Adva

ncedMicrocontroller

BusArchit

ecture(AM

BA)

1.

facilitateright-first-timedevelopmen

tofembeddedmic

rocontrollerproducts

withoneormore

CPUs,GPUsorsign

alprocessors,

2.

betechnologyind

ependent,toallow

reuseofIPcores,peripheralandsystem

macrocellsacross

diverseICprocesse

s

3.

encouragemodularsystemdesignto

improveprocessorindependence,an

d

thedevelopmentofreusableperiphe

ralandsystemIPlibraries

4.

minimizesiliconin

frastructurewhile

supportinghighpe

rformanceandlow

poweron-chipcommunication.

17

A

MBAproto

colspecifications

AMBAspecificatio

ndefinesanon-chipcommunications

standardfor

designinghigh-performanceembedd

edmicrocontroller

s

-

participation.

AMBA4.0specific

ationdefinesfiveb

uses/interfaces:

1.AdvancedeXtensibleInterface(AXI)

2.AdvancedHigh-performanceBu

s(AHB)

3.AdvancedSystemBus(ASB)

4.AdvancedPeripheralBus(APB)

5.AdvancedTra

ceBus(ATB)

18

Note:Thetimingaspectsandthev

oltagelevelsonthe

busarenot

dictatedbythespecifications


10/14

CoreLinkSyst

emIP&D

esignToo

lsforAM

BA

Co

reLinkAMBAdesig

ntoolsfromARMc

omprisetwoproducts

AMBADesigner(ADR-301)for

configuring,generatingandstitchingRTL

,

fr

omNetworkInterc

onnect,throughDMAcontrollersto

M

emoryControllers

O

ncegenerated,ADR-301allowsthede

signertoconnect

eachoftheseblocks

together,andtogenerateatoplevel

verilogdesignfile.Further,ADR-301outputalsoincludesa

n

in

dustrystandardIP-XACTfileforintegratingintoother3rd

partydesignflows

Verification

&PerformanceExploration(VPE-301)forfunctional

19

verification

andperformanceoptimisationofAMBAAXIbasedSyste

m

IPandprocessors

Toperformfunctionalandperformance

explorationtaskson

yourgeneratedblockorsub-system.

VPE-301hastheuniqueabilitytonotonlymonitorsystem

performance,butalsotocapturestatisticaltrafficprofiles

for

re

playandevenmod

ification

20


11/14

21

22


12/14

Ad

vancedeXtensib

leInterfa

ce(AXI)

AX

I,thethirdgenerationofAMBAinterf

acedefinedintheAMBA3specification,

istargetedathighperformance,highclo

ckfrequencysystemdesignsandincludes

fea

tureswhichmakeitversuitableforhihseedsub-mic

rometerinterconnect:

1

.separateaddress/controlanddataphases

2

.supportforunaligneddatatransfersusingbytestrobes

3

.burstbasedtran

sactionswithonlystartaddressissued

4

.issuingofmultip

leoutstandingaddresses

5

.easyadditionof

registerstagestop

rovidetimingclosu

re.

23

AdvancedH

igh-perf

ormance

Bus(AH

B)

AHBisabusprotocolintroducedinAMBAversion2publish

edbyARMLtd

com

pany.

Ithasthefollowingno

tablefeatures:

.

2.

splittransactions

3.

severalbusmaste

rs

4.

bursttransfers

5.

pipelinedoperations

6.

single-cyclebusm

asterhandover

7.

non-tristateimplementation

8.

largebus-widths(64/128bit)

Asimpletransactiono

ntheAHBconsists

ofanaddressphas

eandasubsequen

t

24

dataphase(withoutw

aitstates:onlytwo

bus-cycles).Acces

stothetargetdevice

iscontrolledthrougha

MUX(non-tristate

),therebyadmittin

gbus-accesstoone

bus

-masteratatime

AHB-LiteisasubsetofAHBwhichisform

allydefinedinthe

AMBA3standard.

Thissubsetsimplifiesthedesignforabuswithasinglemaster

The

ARMAMBASuppo

rtFAQpageinclud

esnotesonhowto

integrateafullAH

B

masterintoanAHB-litesystemandvicev

ersa


13/14

A

dvanced

PeripheralBus(A

PB)

APBisdesignedforlowbandwidth

controlaccesses

Example

:registerinterfacesonsystemperipherals

s

us

asana

ressanatap

asesm

arto

,utamuc

r

educedlowcomplexitysignallist

Example

:nobursts.

Wecontin

uewithAMBASpecRev2.0

25

APBo

1.1

OverviewofAPB

o

2.4

APBSignalList

o

.

out

o

5.2.2

Fig.5.3WrTra

nsfer

o

5.2.3

Fig.5.4RdTran

sfer

o

5.4.1

Fig.5.5Interfa

ceDiagram&notePENBLESignal

o

5.4.2

APBBridge

o

5.4.3

Fig.5.6APBBridgeTransfer

o

5.5.1

Fig.5.7SlaveInterfaceDescript

ion

o

5.5.2

APBSlaveDescrition

26

o

5.5.3

Fig.5.8APBSlaveTransfer

o

5.6.1

Fig5.9RdTran

sfertoAHB&Fig

.5.10RdBurst

o

5.6.2

Fig.5.11WrTr

ansferfromAHB

&Fig5.12WrBu

rst


14/14

A

HBo1.1

OverviewofAH

B

o

2.2

AHBSignalList

o

3.1

AboutAHB

o

3.1.1

Fig.3.1AHBSystem

o

3.2

Fig3.2Bus-Mu

xInterconnection

o

3.4

Fig.3.3Simple

Transfer

Fig.3.4TransferwithWaitStates

Fig.3.5Multip

leTransfers

o

3.5

Fig.3.6TransferTypes

27

.

o

3.6.1

Fig.3.7Four-be

atwrappingburst

Fig.3.8Four-be

atincrementing

burst

Fig.3.9Eight-beatwrappingbur

st

Fig.3.10Eight-beatincrementin

gburst

2.sys bus arch

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