Introduction

2.CMOS Transistor Theory

Fu yuzhuo

outline

• PN junction principle

• CMOS transistor introduction

• Ideal I-V characteristics under static

conditions

• Dynamic Characteristics

• Non-ideal I-V effects

2/59

How could MOS device work?

outline

• PN junction principle

• CMOS transistor introduction

• Ideal I-V characteristics under static

conditions

• Dynamic Characteristics

• Non-ideal I-V effects

3/59

How could MOS device work?

• PN junction diffusion

• P-type hole concentration>>N-type hole concentration

• N-type electron concentration>>P-type electron

concentration

• Diffusion result

• Build up space-charge region(depletion)

• Stronger diffusion current, wider space-charge region

• Drift result

• Opposite to the diffusion current

• Resulting in a zero net flow

Diffusion&Drift activity

4/59

Depletion Region

http://en.wikipedia.org/wiki/P–n_junction 5/59

Depletion Region

http://en.wikipedia.org/wiki/P–n_junction

6/59

PN junction Energy Band

mV600≈)n

NNln(0.026=)

n

NNln(

q

kT=Φ

2

i

AD

2

i

AD

0

势垒区

Example an abrupt junction has doping densities of NA=1015 atoms/cm3,

and ND=1016 atoms/cm3, calculate the built-in potential at 300K, ni is the

intrinsic carrier concentration in a pure sample of semi and equals

approximately 1.5X1010 atoms/cm3

7/59

Forward-bias Mode

• Applied potential lowers the potential barrier

• Diffusion current dominates the drift component

8/59

Reverse-bias mode

• Potential barrier is raised

• Drift current becomes dominant

• The number of minority carriers in the

neutral regions is very small, so drift

current component can almost be ignored

9/59

Pn-juntion outline

• PN junction analysis

• PN junction current

• PN junction capacitance

10/59

Minority carrier concentration in the neutral

regions near the pn-junction under forward-

bias conditions

Diode static behavior

Minority carrier concentration

is supported by p-zone

majority carrier concentration

11/59

Diode static behavior

Minority carrier concentration in the neutral regions

near the pn-junction under reverse-bias conditions

12/59

How to calculate diffusion

current?

1)(e TD0 /ΦV

2

WW

pDqAI

n

n

pDDp

1)(e TD0 /ΦV

1

WW

nDqAI

p

p

nDDn

1)(e

1)(e)(

TD

TD00

/ΦV

/ΦV

21

S

n

n

p

p

p

nDDDD

I

WW

pD

WW

nDqAIII

np

13/59

Diode Current

VT = kT/q = 26mV at 300K

IS is the saturation current of the diode

SSSD IIII 48.23=1)(e=1)(e 0.026*/11.0/nVV TD

14/59

Models for Manual Analysis

VD

ID = IS(eVD/T – 1)+

–

VD

+

–

+

–VDon

ID

(a) Ideal diode model (b) First-order diode model

15/59

PN junction outline

• PN junction analysis

• PN junction current

• PN junction capacitance

16/59

Dynamic behavior of pn-junction

Junction capacitance/depletion capacitance -Cj

Diffusion capacitance/dope capacitance -Cd

dV

dQC

17/59

Junction capacitance

P N

+ －

+－

• The boundary of PN-junction could accumulate

charge when bias voltage was changed, which

show capacitance characteristic

• When forward voltage improved/decreased，more/less charges pass,just like these charges

are saved/leaved

18/59

Junction Capacitance

19/59

Diode Model

mD

j

T

DTdiode

V

CIC

0Φ1

0

ID

RS

CD

+

-

VD

More knowledage:

“Microelectronic Circuits:Analysis and

Design” Muhammad H.Rashid20/59

Junction and diffusion

capacitance• Forward-bias mode

• small RC effect for ignoring Junction cap.

• Diffusion cap. Is dominant

• Reverse-bias mode

• Minority carrier concentration is very small,

so its diffusion cap. Can be ignored

• large RC effect

• Junction cap. Is dominant

21/59

PN junction switching model

Vsrc

t = 0

V1

V2

VD

Rsrc

t = T

ID

Time

VD

ON OFF ON

Space charge

Excess charge

22/59

outline

• PN junction principle

• CMOS transistor introduction

• Ideal I-V characteristics under static

conditions

• Dynamic Characteristics

• Nonideal I-V effects

23/59

What is a Transistor?

VGS VT

Ron

S D

A Switch!

|VGS|

An MOS Transistor

24/59

Terminal Voltages

• Mode of operation depends on Vgs, Vgd, Vds

• Vds = Vd – Vs = Vgs - Vgd

• Source and drain are symmetric diffusion terminals

• source is terminal at lower voltage

• Hence Vds 0

• nMOS body is grounded. First assume source is 0 too.

• Three regions of operation

• Cutoff

• Linear

• Saturation

Vg

Vs

Vd

Vgd

Vgs

Vds

+-

+

-

+

-

25/59

nMOS threshold voltage

• nMOS Cutoff

• No channel，Ids = 0

• Vt>Vgs>0

• depletion region(inversion) is formed below

the gate

• Vgs=Vt

• A strong inversion is built up, the potential at

the silicon surface reaches a critical value

• Further increases the gate voltage produce

no further changes in the depletion layer

width26/59

outline

• PN junction principle

• CMOS transistor introduction

• Ideal I-V characteristics under static

conditions

• Velocity Saturation

• Dynamic Characteristics

• Nonideal I-V effects

27/59

28/59

Cut-off

Weak inversion

Strong inversion

29/59

Linear regime

Pinch off

Saturated state

nMOS Linear

• Channel forms

• Current flows from d to s

• e- from s to d

• Ids increases with Vds

• Similar to linear resistor

+-

Vgs

> Vt

n+ n+

+-

Vgd

= Vgs

+-

Vgs

> Vt

n+ n+

+-

Vgs

> Vgd

> Vt

Vds

= 0

0 < Vds

< Vgs

-Vt

p-type body

p-type body

b

g

s d

b

g

s dIds

30/59

nMOS in linear area

])([)( Tgsxoi VxVVCxQ Charge per unit area:

WxQxvI inD )()(dx

dVxExv nnn )()(

WVxVVCdx

dVI TgsxonD ])([

DSV

Tgsxon

L

D WdVVxVVCdxI00

])([

s./vcm1800=μs,./vcm3800=μ 2

p

2

n

]2

V-)V-V[(V

L

W]=k

2

V-)V-V[(V

L

WC=μI

2

DSDSTgs

'

n

2

DSDSTgsxonD

31/59

nMOS Saturation

• Channel pinches off

• Ids independent of Vds

• We say current saturates

• Similar to current source

+-

Vgs

> Vt

n+ n+

+-

Vgd

< Vt

Vds

> Vgs

-Vt

p-type body

b

g

s d Ids

32/59

I-V relation under Saturation

condition

• Vds＝Vgs-VT

ox

oxnoxn

'n

t

ε=C=k

2

)(

2)(

22

TGSnVVV

DSDSTGSnD

VVk

VVVVkI

Tgsds

33/59

I-V characteristic of saturation

])([)( Tgsxoi VxVVCxQ

WxQxvI inD )()(dx

dVxExv nnn )()(

WVxVVCdx

dVI TgsxonD ])([

TGS VV

Tgsxon

L

D WdVVxVVCdxI00

])([

Charge per unit area:

2TGS

'

nDsat V-V

L

W

2

k=I

34/59

Current-Voltage Relations

Long-Channel Device

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS

(V)

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VTQuadraticRelationship

35/59

Another method for giving I-V

Characteristics

• In Linear region, Ids depends on

• How much charge is in the channel?

• How fast is the charge moving?

36/59

Channel Charge

• MOS structure looks like parallel plate capacitor while operating in

inversion

• Gate – oxide – channel

• Qchannel = CV

• C = Cg = eox WL/tox = CoxWL

• V = Vgc – Vt = (Vgs – Vds/2) – Vt

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide

(good insulator, eox

= 3.9)

polysilicon

gate

Cox = eox / tox

37/59

Carrier velocity

• Charge is carried by e-

• Carrier velocity v proportional to lateral E-field between

source and drain

• v = E called mobility

• E = Vds/L

• Time for carrier to cross channel:

• t = L / v

38/59

nMOS Linear I-V

• Now we know

• How much charge Qchannel is in the channel

• How much time t each carrier takes to cross

DS

DS

TGS

DS

DS

TGSox

c

ds

)V2

VVk(V=

)V2

VV(V

L

WμC=

t

Q=I

--

--

L

w

t

εu=

L

wCu=

L

wk=k

ox

ox

noxn

'

nn

39/59

nMOS Saturation I-V

• If Vgd < Vt, channel pinches off near drain

• When Vds > Vdsat = Vgs – Vt

• Now drain voltage no longer increases current

Ids=k(Vgs-Vt-Vdsat/2)Vdsat=k(Vgs-Vt)2/2

40/59

summary

• Shockley 1st order transistor models

0 Vgs<Vt cutoff

• Ids= k(Vgs-Vt-Vdsat/2)Vdsat Vds<Vdsat linear

k(Vgs-Vt)2/2 Vds>Vdsat saturation

41/59

outline

• PN junction principle

• CMOS transistor introduction

• Ideal I-V characteristics under static conditions

• Velocity Saturation

• Dynamic Characteristics

• Nonideal I-V effects

42/59

Current-Voltage Relations

The Deep-Submicron Era

LinearRelationship

-4

VDS

(V)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation

43/59

Attention : velocity position

])([)( Tgsxoi VxVVCxQ Charge per unit area:

WxQxvI inD )()(dx

dVxExv nnn )()(

WVxVVCdx

dVI TgsxonD ])([

DSV

Tgsxon

L

D WdVVxVVCdxI00

])([

s./vcm1800=μs,./vcm3800=μ 2

p

2

n

)(2

)(2

DSATDSAT

DSATTGSoxnD VV

VVVL

WCI

44/59

Velocity Saturation

csat

c

c

n

v

v

for

for 1

x (V/µm)ξc= 1.5

un

(m/s

)

usat

= 105

Constant mobility (slope = µ)

Constant velocity

The critical field depends upon the doping levels and

the vertical electrical field applied(1-5V/um)

45/59

Velocity Saturation

)(2

)(

2)(

)(1

2

2

DSDS

DSTGSoxn

DSDSTGS

c

DS

oxnD

VV

VVVL

WC

VVVV

L

W

LV

CI

cLξV+1

1=κ(V)

46/59

Velocity Saturation

)(2

)()(2

DSATDSAT

DSATTGSoxnDSATGToxsatD VV

VVVL

WCVVWCI

GTGTDSAT VVV )(

Current definition Assuming VGS is high enough

47/59

WxQxvI inD )()(

L

VV

c

DSATDSAT

1

1)(

Perspective

IDLong-channel device

Short-channel device

VDSVDSAT VGS - VT

VGS = VDD

48/59

ID versus VGS

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VGS

(V)

I D(A

)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VGS

(V)

I D(A

)

quadratic

quadratic

linear

Long Channel Short Channel

49/59

Another two assumptions

csat

c

c

n

v

v

for

for 1

L

V

V

VVV

c

GT

GT

GTGTDSAT

1

)(

csat

cn

v

v

for

for

n

SATcVDSAT

LvLV

GT

50/59

VDSAT is nearly constant…

ξc =1.5v/um, L=2λ=0.06um,then ξc L=0.09

Linear area still using the same formula

Modify the velocity formula to be coherent with the

familiar long-channel equations

n

SATcDSAT

LvLV

2

)(2DSAT

DSATTGSoxnD

VVVV

L

WCI

51/59

ID versus VDS

-4

VDS

(V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10-4

VDS(V)

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

Long Channel Short Channel

Qua

dra

tic

depe

ndenc

e

Line

ar d

epen

denc

e

52/59

A unified model for manual analysis

S D

G

B

53/59

Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS

(V)

I D(A

)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

54/59

A pMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

-0.8

-0.6

-0.4

-0.2

0x 10

-4

VDS (V)

I D(A

)

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V

55/59

Assume all variables negative!

Summary

• Strong Inversion VGS > VT

• Linear (Resistive) VDS < VDSAT

• Saturated (Constant Current) VDS VDSAT

• Weak Inversion (Sub-Threshold) VGS VT

• Exponential in VGS with linear IDS

dependence

56/59