28 Feb 1982 22:30 G.DOC[SUN,AVB] Page 1

$UN Graphics Board Rev C

Documentation Package

Febru~ry 28, 1982

VLSI SYSTEMS INC,

TRADE SECRET NOTICE:

This document contain, unpublished, proprietary information and describes subject matter proprietary to VLSI SYSTEMS INC. This document may not be disclosed to third parties or copied or duplicated in any form without the prior written consent of an officer of VlSI SYSTEMS INC. Use of this information by third parties is governad by applicable license agreements .

• COPYRIGHT NOTICE:

If, and only if, this document is aCCidentally disclosed or released into the public domain, the following notice shall apply:

Copyright (c) 1982 VLSI SYSTEMS INC. All rights reserved.

PATENT RIGHT NOTICE:

An invention disclosure has been filed relating to the technology described herein. All patent rights reserved by VLSI SYSTEMS INC.

TRADEMARK NOTICE:

Multibus is a trademark of Intel Corporation.

28 Feb 1982 22:30 G.DOC[SUN,AVB] Page 2

SUN Graphics Board Table of Content

Table of Content

This is the engineering documention for the SUN graphics board. It includes:

Section

Table of Content Conventions Parts List Location Summary Signal Summary Bus Decoding Logic Schematics PROM Sources PROM Object

Page

2 3 4 5 6 7 Gl trough G7 GO.SAI,Gl.SAI,G2.SAI,G4.SAI,G6.SAI GO.HEX,Gl.HEX,G2.HEX,G4.HEX,G6.HEX

28 Feb 1982 22:30 G.DOC[SUN,AVB] Page 3

SUN Graphics Board Conventions

Conventions

The logic diagrams are best understood in conjunction with the wjrelist. The wirelist has two parts. Part one are the components listed by location and indicating on which logic drawing they are used. Part two are the signal nets sorted in alphabetical order and showing all components connected to a signal, as well as the electrical loading considerations.

Signal Definitions:

Negated logic signals. that ;s signals that are asserted active low, are indicated by a backslash "\" following the signal name.

For signals with multiple meanings or synonyms. the synonyms are listed separated by a slash "I". If a signal has multiple functions that are exclusive of each other, the names are listed separated by a vertical bar or "I".

For example, the signal name for a read-write signal that is active low for write is "READ/WRITE\". The inverted version of this Signal would be "READ\/WRITE". A ClOCK that is asserted either in state 3 or 5 will be marked: C.S315.

Often a group of signals share the same property. Such groups of 'signals typically share the same prefix, separated from a suffix with ".". For example. all signals driving the Multibus are prefixed with "B.".

Signals that are part of busses usually share the same prefix followed by a number. For example, the 16 data bus signals are labelled "DO". "D1", "D2", and so on up to "015".

Clock Signals names typically contain information about their nature as part of their signal name. Periodic clocks are labelled C##.##-##. where the first number is the clock period. the second number the beginning of the active clock phase. and the third number the end of the active clock phase.

Component Labels

Part Numbers consist of one letter followed by three digits. The letter indicates the type of component and ;s one of:

C discrete Capacitor J Jumper of Connector R discrete Resistor S single-in-line component U dual-in-line component

The three digits give the approximate component position on the board,

.'

28 Feb 1982 22:30 G.DOC[SUN.AVB] Page 3-2

with the first digit indicating the row position and the last two digits numbering the positio~·along each row.

28 Feb 1982 22:30 G.DOC[SUN"AVB] Page 4

SUN Graphics Board Parts list Prop rietary VLSI SYSTEMS INC. _

~-~---~--~-----~----~-------------------------~---~--~-----~-------~--~~~~~--~-GENERIC QTY BRAND PART NUMBER DESCRIPTION ---~----~~----~~--~-----------------~--------------~------~-------~--~~~~~--~-~

25LS09 3622 4164 -74LS393 74LS04 -74lS138 74LS145 74LS244 74LS251 74L5273 74L5374 74LS533 74LS670 74LS74 74S00 74S02 745139 745240 745283 74S288 745288 745299 74537 745374 745472 74574 AN25509 At·125S10 C DIPSW 051648 Kl114A R9.SIP

2 AMD 3 SIG-

16 ANY 3 TI 1 TI 1 TI 1 TI 4 Tl

16 TI 1 TI

-15 TI 6 Ar4D-6 TI 1 Tl 2 TI 1 11 2 TI 1 Tl 2 TI 1 TI 1 Tl 2 TI 1 TI 4 TI 2 TI 2 TI 1 AMD 8 AMD

38 AVX 1 CUTLER 4 NAT

AM25LS09PC N82S131 4164 SN74LS393N SN74LS04N sr~7 4LS138N SN74LS145N SN74LS244N SN74LS251N

: - SN74LS273N Stl74LS374N 5N74LS533N 5N74LS670N SN74LS74 SN74S00N SN74502N SN74S139N SN74S240N StJ74S283fJ TBP18S030N TBP18S030N SN74S299N

- SN74S37N 5N745374tJ TBP28S42N SrJ74S74N At425S09PC At·125S lOpe '·1DO 15C 104t,tAA Sf4-2AV-951-8 D51648

1 M010ROL 2 BURr·IS

K1114A 4310R-l01-103

FOUR-BIT REGISTER, INPUT MUX 512-BY-4 BIPOLAR PROM 64K-BY-l DYNAMIC RAM 150 NSEC DUAL 4-BIT BINARY COUNTER HEX INVERTER 3-TO-8 DECODER BOC-IO-DECIMAL DECODER OCTAL NONINVERTED BUFFERS 1-0F-8 DATA SELECTOR OCTAL D-TYPE fLIPFLOP WITH CLEAR OCTAL REGISTER OCTAL TRANSPARENT LATCH INVERTING 4-BY4 REGISTER Fi_ES-DUAL D-TYPE fLIPFLOPS QUAD 2-INPUT NAND GATES QUAD 2-INPUT NOR GATES DUAL 2-TO-4 LINE DECODER OCTAL INVERTING BUFFER 4-B IT ADDER . 32-BY-8 BIPOLAR PROM 32-BY-8 BIPOLAR PROM . 8-BIT UNIVERSAL SHIFT REGISTf1 QUAD 2-INPUT NAND BUF~ERS OCTAL O-TYPE LATCHES 512-BY-8 BIPOLAR PROM DUAL D-TYPE FLIPFLOP FOUR-BIT REGISTER, INPUT MUX SCHOTTKY FOUR-BIT SHIfTER, OIPGUARD CAPACITORS 0.1 UF DIPSWITCH WITH 8 POSITIONS QUAD MEMORY DRIVER CRYSTAL OSCILLATOR 31.25 MHZ RESISTOR SIP, 9 RESISTORS. lK

28 feb 1982 22:30 G.OOC[SUN,AVB] Page 5

SUN Graphics Board Location Summary Proprietary VLSI SYSTEMS INC.

--------------------------------------------------------------------------------LOC OIPTYPE BODY FILE P~S

~~~-~~------------------------------------------------ --------------------------

C5 C C 66 01 CIOI C C 66 01 CI03 C C G6 02 CI06 C C G6 02 Clll C C 66 01 C112 C C G6 02 C113 C C G6 02 C114 C C G6 03 el15 C C G6 03 C116 C C 66 04 C117 C C 66 04 C201 C C 66 02 C206 C C G6 02 C301 C C G6 03 C303 C C G6 03 C306 C C G6 03 C311 C C G6 05 C312 C C G6 05 C313 C C 66 06 C314 C C G6 06 C315 C C G6 06 C316 C C G6 07 C317 C C G6 07 C401 C C 66 04 C406 C C 66 03 C501 C C G6 04 C517 C C 66 01 C601 C C 66 05 C606 C C G6 04 C617 C C G6 02 C701 C C G6 05 C706 C C G6 04 CB06 C C G6 05 C811 C C G6 02 C813 C C G6 03 C815 C C G6 03 C917 C C G6 04 JI J.I0 J.I0 67 A7 J2 J.10 J.IO G7 C7 J3 J.4 J.4 G3 04 KIOI C C G3 86 KI02 C C G3 85 K901 C C G6 01 K902 C C G6 02 R1D6 R R 64 A7 R1D7 R R G4 A7 RID8 R9.SIP R9.SIP G4 C5 R3D8 R9.SIP R9.SIP G4 05

28 Feb 1982 22:30 G.DOC[SUN,AVB] Page 5-2

U3 74537 74537 G3 A7 G3 A7 G3 A7 G3 A7

U4 74L5374 74LS374 G3 C5 U101 7660 7660 G3 B5 UI02 10124Q 10124 G3 B7 UI04 3622 3622 G3 C4 UI05 3622 3622 G3 C4 U106 745374 745374 G4 A7 U107 74S288 745288 G4 A6 UI08 745472 745472 G4 Cl U109 74LS374 74L5374 G4 C3 U110 4164 4164 G1 Al U111 4164 4164 Gl A2 U112 4164 4164 G1 A3 U113 4164 4164 G1 A4 U114 4164 4164 G1 A5 U115 4164 4164 G1 A6 U116 4164 4164 G1 A7 U117 4164 4164 G1 A8 U202 74500 74500 G6 C5

G6 C6 G3 03 G3 82

U203 14 393 74LS393 G3 02 U204 74 393 74L5393 G3 C2 U205 74 393 74LS393 G3 C2 U210 74LS251 74L5251 G1 61 U211 74LS251 74L5251 Gl 82 U212 74LS251 74LS251 G1 83 U213 74LS251 74L5251 G1 64 U214 74LS251 74L5251 G1 85 U215 74LS251 74L5251 G1 66 U216 74LS251 74L5251 G1 67 U217 74LS251 74LS251 G1 88 U301 K1114A K1114A G3 06 U302 AM25S09 AM25509 G4 A4 U303 74LS74 74LS74 G6 06

G3 04 U304 OS1648 051648 G3 . C7 U305 051648 OS1648 G3 C7 U306 745374 74S374 G4 B7 U307 74S288 74S288 G4 B6 U308 745472 745472 G4 01 U309 74LS374 74LS374 G4 03 U310 4164 4164 G1 C1 U311 4164 4164 G1 C2 U312 4164 4164 G1 C3 U313 4164 4164 G1 C4 U314 4164 4164 G1 C5 U315 4164 4164 G1 C6 U316 4164 4164 G1 C7 U317 4164 4164 G1 C8 U402 74574 74574 G6 C6

28 Feb 1982 22:30 G.DOC[5UN,AVB] Page 5-3

G3 08 U403 745139 745139 G2 C8

G2 08 U404 OS16~8 051648 G4 07 U405 051648 OS1648 G4 C7 U410 74LS251 74lS251 Gl 01 U411 74LS251 7415251 Gl 02 U412 74LS251 74lS251 G1 03 U413 74LS251 7415251 G1 04 U414 74LS251 74lS251 G1 05 U415 74L5251 74lS251 G1 06 U416 74LS251 74lS251 Gl 07 U417 74lS251 74lS251 G1 08 U502 745139 74S139 G6 B8

G6 B8 U503 74S374 745374 G4 B7 U505 25L509 AM25L509 G4 Bl U506 74LS273 74lS273 G6 C5 U507 74LS374 74lS374 G2 05 U508 25LS09 AM25LS09 G4 B4 U509 74L5374 74lS374 G2 C5 U510 74L5374 74lS374 G2 A3 U512 74LS374 74LS374 62 A3 U514 74L5374 74LS374 62 B3 U516 74L5374 74LS374 G2 C3 U601 74L504 74LS04 G4 03

G4 06 G4 07 66 A4 G6 A4 66 A5

U602 74574 74574 G6 B6 G6 B6

U603 745283 745283 G4 B6 U604 745283 745283 G4 C6 U605 3622 3622 64 B4 U610 74L5244 74lS244 62 A8 U612 74LS244 74LS244 G2 A8 U614 74L5244 7415244 62 B8 U616 74lS244 74LS244 62 C8 U701 74500 74500 64 A6

66 A3 66 A5 66 07

U702 74502 74502\ 66 A2 74502 66 At 74502\ 66 A2

63 83 U703 74lS670 74LS670 65 86 U704 74LS670 74LS670 65 B6 U705 74LS670 74L5670 65 A6 U706 74L5374 74L5374 63 A2 U707 745299 745299 63 A3 U708 745299 745299 63 A3 U709 74L5374 74lS374 G3 A2

28 Feb 1982 22:30 G.DOC[SUN.AVB] Page 5-4

U7I0 AM25SI0 AM25S10 G2 A6 U712 AM25S10 AM25S10 G2 A6 U7I4 AM25SI0 AM25S10 62 B6 U716 AM25SI0 AM25SI0 62 B6 U800 J.16 J.16 G6 C3 U801 DIPSW DIPSW G6 C3 U802 74S240 745240 66 A7 U803 74LS670 74LS670 65 06 UB04 74LS670 74LS670 65 06 U805 74LS670 74LS670 G5 C6 UBI0 AM25S10 AM25SI0 62 A4 U8I2 A~125S10 AM25S10 G2 A4 U814 AM25S10 AM25SI0 62 64 U8I6 AM25S10 A~12 5S 1 0 62 64 U901 74LSI38 74LSI38 G6 C2 U902 74S374 74S374 G4 A1 U903 74LS533 74LS533 G5 C2 U904 74LS145 74L5145 G6 C8 U905 74LS533 74L5533 G5 B2 U906 74LS533 74LS533 62 03 U907 74LS533 74LS533 62 01 U908 74LS533 74LS533 62 C3 U909 74LS533 74LS533 62 C1 U910 74LS374 74LS374 62 At U9I2 74LS374 74LS374 G2 At U914 74LS374 74LS374 G2 61 U916 74LS374 74LS374 G2 C1 p CON

28 Feb 1982 22:30 G.oOC[SUN,AVB] Page 6

SUN Graphics Board Signal Summary Proprietary VLSI SYSTEMS INC.

--------------------------------------------------------------------------------Mnemonic Description ---------------~-------------------------------------- --------------------------

AD .. A 16 B.AD\ .. A19\ B.AACK\ B.BCLK\ B.BHEN\ B.BPRN\ B.BPRO\ B.BREQ\ B.BUSY\ B.CBRQ\ B.CCLK\ B.00\ .. 015\ B.INH1\ .. 2\ B.INIT\ B.INTO\ .. INT7\ B.INTA\ B.IORC\ B.IOWC\ B.MRDC\ B. r~WTC\ B.XACK\ BUSREAo BUSSEL C.SO C.S3 C.S7 C32.0-16 C64.0-32 CASO CASt CYCLED CYCLE1 00 .. 015 DISPEN OS EN.INT EN.VIDEO FUNO .. FUN7 GND GX600 .. GX617 HO •• He HQD .. HQ3 HRESET HSYNC\ INTO .. INT2 INT\ Jl. HSYNC Jl. VIDEO

on-board latched address Multibus address lines UNUSED. Multibus advanced acknowledge UNUSED. Multibus bus clock UNUSED, Multibus byte high enable UNUSED. Multibus priority in UNUSED. Multibus priority out UNUSED, Multibus bus request UNUSED, Multibus busy UNUSED, Multibus common bus request UNUSED, Multibus constant clock Multibus data lines UNUSED, Multibus inhibit lines Multibus init Multibus interrupt request UNUSED Multibus interrupt acknowledge UNUSED Multibus I/O read control UNUSED Multibus lID write control Multibus memory read control Multibus memory write control Multibus trasfer acknowledge READ*BUSSEL Bus Select Clock State 0 Clock State 3 Clock State 7 Pixel Clock System Clock Column-Address-Strobe 0 Column-Address-Strobe 1 Cycle Type 0 Cycle Type 1 Data Bus Display Enable Data Strobe Enable Interrupts Enable Video Function Register Ground Memory Controller Internals Horizontal Counter Outputs Horizontal State Machine Internals Horizontal Counter Reset Horizontal Sync Pulse Interrupt Level Select Interrupt ECL horizontal sync ECL video

28 Feb 1982 22:30 G.DOC[SUN,AVB]

Jl. VSYNC J2.HSYNC J2.VIDEO J2.VSYNC lD.BUF lD.PRT lD.REG\ lD.X\ LD.Y\ M.AO\ .. A7\ M.CASO\ .. CAS15\ M.DIO .. M.OI15 M.RAS\ M.WE\ MASKO .. MASK15 OE.PRT\ OE.SRX\ PU PUl RASAORS RASTEROP RAS ROSETO .. ROSETl READ REAOOP READREQ . REFRESH REGSElO .. l REQ SOO .. 5015 SETREQ\ SHIFTO .. 3 SRCO .. 15 SRSO .. 15 SRXO .. 15 STATEO .. 3 VO .. 10 VEND VBlANK VCC VCLOCK\ VCLOCK1\ VEE VIDEO VINT VODO VQO .. 3 VRESET VSYNC WO •• 3 WE.CTl\ WE.FUN\ WE.INT\ WE.MSK\ WE.RAM\

Eel vertical sync TTL horizontal sync TTL video TTL vertical sync Load Buffer Strobe load Data Port Strobe load Register Strobe Load X-Register Strobe load V-Register Strobe Memory Address Bus Memory Column Address Strobes Memory Data In Bus Memory Row-Address Strobe Memory Write Enable Strobe Mas k Reg; s te r Output Enable Data Port Output Enable Shifter Buffer Pullup Pullup 1 Row Address Select Raster Operation Bit Row-Address-Strobe Read-Set Select Read Strobe Read Operation Read Request Refresh Operation Regis.ter Select Request Shift Data Set Request Shift Amount Sou rce Reg is te r Source Register Shifter Internal Source Register Shifter State Vertical Counter Outputs Vertical Counter End Vertical Blank +5V Vertical Counter Clock Vertical Counter Clock delayed -5V Video Data Vertical Interrupt Vertical Odd (Interlace Toggle) Vertical Decode PROM Internals Vertical Reset Vertical Sync Width Write Enable Control Register Write Enable Function Register Write Enable Interrupt Flag Write Enable Mask Register Write Enable RAM

Page 6-2

28 Feb 1982

WE.SRC\ WE.STATUS\ WE.WIDTH\ WE WIDTHO .. 3 WRITE WRITEOP WRITEX XO •• 9 XACK XCASO •• 15 XSO •• 3 XX4 .. 9 XXX4 •• 9 YO •• 9

22:30 G.DOC[SUN,AVB]

Write Enable Source Register Write Enable Status Register Write Enable Width Register Write Enable Width Register Wri te Write Operation Write Latched X-Address Transfer Acknowledge Cas Decoder Internals X-Address of Source X-Address after adder X-Address after adder latched V-Address

Page 6-3

28 Feb 1982 22:30 G.DOC[SUN,AVB] Page 7

SUN Graphics Board Bus Decoding Proprietary VLSI SYSTEMS INC.

Decoding of Multibus Interface

00 .. 015 New 16-bit data, read or write

Al .. IO New X or Y address

All 0 -) X, 1 -) Y

Al2 .. 13 Selects one of the four sets of (x,y) registers

A14 .. 15 Select data register to be updated On @i(read cycles), data is supplied from frame buffer On @i(write cycles), data is supplied from processor

o -) No Register 1 -) Control Regist-ers 2 -) Source Register 3 -) Mask Register

Control register are further decoded with Al .. A2 as follows:

o -) Function Register 1 -) Width Register 2 -) Control· Reg i sters 3 -) Interrupt Acknowledge

Al6 Enable raster operation on frame buffer

o -) no update operation 1 -) execute update operation

Al7 .. 19 Module Select

MEMR IEEE-796 Read Strobe

MEMW IEEE-796 Write Strobe

XACK IEEE-796 Acknowledge

INTO .. 7 Interrupt request. Priority level selectable in software.

INIT Initialization. clears control register.

7;';"4 41 7i"tl ~ . [ill: 7ii4 7i'ii ~ It. ~O'

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28 feb 1982 Z2:07 GO.SAI[SUN.AVB] Page 1

comment This information proprietary to VLSI SYSTEMS INC.; begin "prmgen" require "prom.sai" sourcelfile; $512;

define

h5 h6 h3 h2 h4 h1 hO vsync vblank

h

hsync dispen hreset vclock

-[aO]. -(al]. -(a2]. -(a3]. -(a4]. -(a5]. -(a6]. -[a7]. -[a8].

"'[(cvb(hO)·dO + cVb{hl)·dl + cvb(h2)·dZ + cVb(h3)·d3 + cVb(h4)·d4 + cVb(h5)·d5 + cVb{h6)*d6)].

=[(53 ~ h < 59)]. =[«1 ~ h < 51) A ~vblank)J. z[(h • 63)]. -((h .. 'Z4) v (h • 56»];

prombegin

prom(O,dO. prom(O.dl. prom(O.d2. prom(O.d3.

hreset) : ...hsync): dispen): ~vc'ock):

promend; writeprom("gO".O): end;

28 Feb 1982 22:11 GO.HEX[SUN,AVB]

:lOOOOOOOOAOEOAOAOEOEOAOAOEOEOAOAOEOEOAOA34 :lOOOlOOOOEOEOAOA06000AOAOEOAOAOAOEOAOAOA3E :100020000EOEOAOAOEOEOAOAOEOEOAOAOEOEOAOAI0 :100030000EOEOAOAOE080AOAOE080AOAOEOAOAOAIO :l00040000EOEOAOAOEOEOAOAOEOEOAOAOEOEOAOAFO :l00050000EOEOAOAOE080AOAOE080AOAOEOAOAOAfO :100060000EOEOAOAOEOEOAOAOEOEOAOAOEOEOAOADO :100070000EOAOAOAOEOAOAOAOE080AOAOEOBOAOADl :100080000AOEOAOAOEOEOAOAOEOEOAOAOEOEOAOAB4 :100090000EO£OAOA06000AOAOEOAOAOAOEOAOAOABE :1000AOOOOEOEOAOAOEOEOAOAOEOEOAOAOEOEOAOA90 :1000BOOOOEOEOAOAOE080AOAOE080AOAOEOAOAOA90 :1000COOOOEOEOAOAOEOEOAOAOEOEOAOAOEOEOAOA70 :100000000EOEOAOAOE080AOAOE080AOAOEOAOAOA70 :1000EOOOOEOEOAOAOEOEOAOAOEOEOAOAOEOEOAOA50 :1000FOOOOEOAOAOAOEOAOAOAOE080AOAOEOBOAOA51 :100100000AOAOAOAOAOAOAOAOAOAOAOAOAOAOAOA4F :100110000AOAOAOA02000AOAOAOAOAOAOAOAOAOA51 :100120000AOAOAOAOAOAOAOAOAOAOAOAOAOAOAOA2F :100130000AOAOAOAOA080AOAOA080AOAOAOAOAOA23 :100140000AOAOAOAOAOAOAOAOAOAOAOAOAOAOAOAOF :100150000AOAOAOAOAOBOAOAOA080AOAOAOAOAOA03 :100160000AOAOAOAOAOAOAOAOAOAOAOAOAOAOAOAEF :100170000AOAOAOAOAOAOAOAOA080AOAOAOBOAOAEO :l00180000AOAOAOAOAOAOAOAOAOAOAOAOAOAOAOACF :100190000AOAOAOA02000AOAOAOAOAOAOAOAOAOADl :1001AOOOOAOAOAOAOAOAO~OAOAOAOAOAOAOAOAOAAF :1001BOOOOAOAOAOAOA080AOAOA080AOAOAOAOAOAA3 :1001COOOOAOAOAOAOAOAOAOAOAOAOAOAOAOAOAOA8F :1001DOOOOAOAOAOAOA080AOAOA080AOAOAOAOAOA83 :1001EOOOOAOAOAOAOAOAOAOAOAOAOAOAOAOAOAOA6F :1001FOOOOAOAOAOAOAOAOAOAOA080AOAOAOBOAOA60 :0000000000

Page 1

28 Feb 1982 22:01 G1.SAI(SUN.AVB] Page 1

comment This information proprietary to VLSI SYSTEMS INC.: begin "prmgen" require "prom.sai" sourcelfile; S512;

define

v2 v5 v3 v4 vl vO vl0 vodd hreset

adrs

vsync vblank vreset

vint

-[aO]. ·(al]. -[a2], =(a3], =(a4], =[a5]. ·(a6J. -[a7]. -[a8],

=[(cvb(vO}·dO + cvb(v1)·dl + cvb(v2}·d2 + cvb(v3}·d3 + cvb(v4}*d4 + cVb(v5)*d5 + cvb(vl0)*dlO)].

=[(vOdd A (1030sadrs<1036) v ~vodd A (1031sadrs<1037»]. =[(adrs ~ 1024)]. =[(hreset A va

v vodd A (adrs • 1076) v -vodd A (adrs .. 1078»].

-[(adrs z 1024)];

prombegin

prom(O.dO. prom(O.dl. prom(0.d2. prom(0.d3.

vreset); vint): vblank): -vsync);

promend: writeprom("gl".O); end:

28 Feb 1982 22:12 G1.HEX[SUN,AVB]

:100000000808080808080808080808080808080870 :100010000808080808080808080803080808080860 :10002000080808080808080808080a080808080850 :100030000808080808080808080808080808080840 :100040000EOCOCOC04040COCOCOCOCOCOCOCOCOCFE :100050000COCOCOC040COCOCOCOCOCODOCOCOCOCE7 :100060000COCOCOC040COCOCOCOCOCOCOCOCOCOC08 :100070000C040COC040COCOCOCOCOCOCOCOCOCOCOO :10008000080808080B080BOB0808080808080808FO :1000900008080808080808080B080B0808080808EO :1000A0000808080808080808080808D80808080800 :10008000080B0808080808080808080808080808CO :1000COOOOEOCOCOC040COCOCOCOCOCODOCOCOCOC75 :100000000C040COC040COCOCOCOCCCOCOCOCOCOC70 :1000EOOOOCOCOCOC040COCOCOCOCOCOCOCOCOCOC58 :1000FOOOOC040COC040COCOCOCOCCCOCOCOCOCOC50 :1001000008080808080a080808080808080808086F :100110000808080808080808080808D8080808085F :10012000090909090909090909090909090909093F :l0013000090909090909090909090909090909092F :100140000EOCOCOC04040COCOCOCOCOCOCOCOCOCFD :100150000COCOCOC040COCOCOCOCGCODOCOCOCOCE6 :100160000DODOOOD05000DODODODCDODODOOODODC7 :100170000D05000D050DODODODODGDODODODOOODBF :100180000BOB0808080a08080808C80808080808EF :10019000080BOaOa0808080808080808080a0808DF :1001A00009090909090909090909G90909090909BF :100lB000090909090909d9090909090909090909AF :1001COOOOEOCOCOC040COCOCOCOCOCODOCOCOCOC74 :1001DOOOOC040COC040COCocococacococOCOCOC6F :lOOlEOOOODODOOOD050DODODODODODODODOOODOD47 :1001FOOOOD05000D050DOOODODODODODODOOODOD3F :0000000000

Page 1

28 feb 1982 22:07 G2.SAI[SUN.AVB] Page 1

comment This information proprieta~y to VLSI SYSTEMS INC.; begin "prmgen" require ~prom.sa;" sourcelfile; $512;

define

xO xl x2 x3 wO wl w2 w3 cast

"'[aO]. .. [al]. -[a2]. =[a3J. -(a4], "[a5], "Ca6J, -(a7], =(a8J,

x w width en ( i)

=[(cvb(xO)·dO + cVb{xl)*dl + CVb(x2)*dZ + cvb(x3).d3)], =[(cvb(wO)·dO + cvb{wl)·dl + cvb(w2)·d2 + cvb(w3)*d3)]. x[(if w then w else 16)]. =[( (x ~ (15-;) < (x + width»

prombegin

prom(O.dO. prom(O.dl. prom(O.d2. prom(O.d3. prom(O.d4. prom(O.d5. prom(O.dS," prom(O.d7.

prom(l.dO. prom(l.dl. prom(1.d2. prom(1.d3. prom(1.d4. prom(1.d5. prom(1.d6. prom{ 1. d7.

promlnd;

v cas1 A ex ~ (15-;+16) < (x + width»)];

..en(14»;

..en{lO»; "en(6»; .. en(2»; "en(O)); ..en(4»; ... en(8)) ; -en(12»;

-en(15»; ..en(ll)}; -en(7»; ...en(3»; ..en(l»; "en(5)); ..en(9»; ...en(13»;

writeprom("g20".O): writeprom("g21",l): end;

28 Feb 1982 22:13 G20.HEX[SUN,AVB]

:100000000000010181818383C3C3C7C7E7E7EFEF26 :10001000FFFEFF7FFFFDFFBFFFFBFFDFFFF7FFEFEF :10002000FEFE7F1FFDFDBFBFFBFBDFDFF7F7EFEFDE :10003000FE7E7F7DFDBDBFBBFBDBDFD7F7E7EFEFCC :100040007E7E7D7DBDBDBBBDDBDBD7D7E7E7EFEFBA :100050007E7C7030BDB9BB9BOB03D7C7E7E7EFEF28 :100060007C7C3030B9B99B9B0303C7C7E7E7EFEF96 :100070007C3C3D39B9999B93D3C3C7C7E7E7EFEF02 :100080003C3C393999999393C3C3C7C7E7E7EFEF6E :100090003C38391999919383C3C3C7C7E7E7EFEF9A :1000A0003838191991918383C3C3C7C7E7E7EFEFC6 :1000B0003818191191818383C3C3C7C7E7E7EFEFEE :1000C0001818111181818383C3C3C7C7E7E7EFEF16 :1000D0001810110181818383C3C3C7C7E7E7EFEF1E :1000EOOOIOIOOI0181818383C3C3C7C7E7E7EFEF26 :1000F0001000010181818383C3C3C7C7E7E7EFEF26 :1001000000000000000000000000000000000000EF :10011000FFFEFF7FFFFOFFBFFFFBFFOFFFF7FFEFEE :10012000FEFE1F7FFDFDBFBFFBFBDFDFF7F7EFEFDD :10013000FE7E1F70FDBDBFBBFBDBDF07F7E7EFEECC :100140007E7E1D7DBDBDBBBBDBDBD7D7E7E7EEEEBB :100150007E7C7030BDB9BB9BDB0307C7E7E6EE6EAA :100160007C7C303089899B980303C7C7E6E66E6E99 :100170007C3C3039B9999B9303C3C7C6E6666E6C88 :100180003C3C393999999393C3C3C6C666666C6C17 :100190003C38391999919383C3C2C64666646C2C66 :1001A000383819199191a383C2C2464664642C2C55 :100180003818191191818382C242464464242C2844 :1001C0001818111181818282424244442424282833 :100100001810110181808202424044042420280822 :1001E0001010010180800202404004042020080811 :1001FOOOIOOOOI0080000200400004002000080000 :0000000000

Page 1

28 Feb 1982 22:13 G21.HEX[SUN,AVB]

:1000000000010181818383C3C3C7C7E7E7EFEFfF27 :10001000FEFf7FFFFDFFBFFFFBFFDFFFF7FFEFFFEf :10002000FE7f7FFDFDBFBFFBFBDFDFF7F7EFEFFFDD :100030007E7f7DFDBDBfBBFBOBDFD7F7E7EFEFFF~B :100040007E707DBDBDBBBBDBDBD7D7E7E7EFEFFF39 :100050007C7D3DBDB9BB9BDBD3D7C7E7E7EFEFFFA7 :100060007C303DB9B99B9B03D3C7C7E7E7EFEFFF13 :100070003C3039B9999B93D3C3C7C7E7E7EFEFFF7F :1000B0003C393999999393C3C3C7C7E7E7EFEFFFAB :1000900038391999919383C3C3C7C7E7E7EFEFFFD7 :1000A00038191991918383C3C3C7C7E7E7EFEFFFfF :1000B00018191191818383C3C3C7C7E7E7EFEFFF27 :1000C00018111181818383C3C3C7C7E7E7EFEFFF2F :1000DOOOI0110181818383C3C3C7C7E7E7EFEFFf37 :1000E00010010181818383C3C3C7C7E7E7EFEFFf37 :1000FOOOOOOI0181818383C3C3C7C7E7E7EFEFFF37 :1001000000000000000000000000000000000000EF :10011000FEFF7FFFFDFFBFFFFBFFDFFFF7FFEFFfEE :10012000FE7F7FFDFDBFBFFBFBDFDFF7F7EFEFFEDD :100130007E7F7DFDBOBFBBFBDBDF07F7E7EFEEFECC :100140007E7070BOBDBBBBDBDBD7D7E7E7EEEE7EBB :100150007C703DBDB9BB9BDBD3D7C7E7E6EE6E7EAA :100160007C303089899B9B0303C7C7E6E66E6E7C99 :100170003C3039B9999B93D3C3C7C6E6666E6C7C88 :100180003C393999999393C3C3C6C666666C6C3C77 :1001900038391999919383C3C2C64666646C2C3C66 :1001A00038191991918383C2C2464664642C2C3855 :1001B00018191191818382C242464464242C283844 :1001C0001811118181828242424444242428281833 :100100001011018180820242404404242028081822 :1001E0001001018080020240400404202008081011 :1001F0000001008000020040000400200008001000 :0000000000

Page 1

28 Feb 1982 22:07 G4.SAI[SUN.AVB] Page 1

comment This information proprietary to VLSI SYSTEMS INC.; begin "prmgen" require "prom.sai" sourcelfile; 5512;

define

xs2 -[aO], x3 =[a1], x2 -(a2], xs3 -[a3], xl -[a4], xsl -[a5]. readop_i"[a6], xsO =[a7], xO -[a8],

=[("'readop_i)], readop xs xd shift

=[(cvb(xsO)-dO + cVb(xs1)·dl + cVb(xs2)·d2 + cVb(xs3)*d3)]. =[(cvb(xO)·dO + cvb(xl)·dl + cVb(x2)*dZ + cvb(x3)-d3)], -[{if readop then (xs - 0) else (xs - xd»];

prombegin

prom(O.dO. shift prom(O.dl. shift prom(O.d2. shift prom(O.d3. shift

promend; writeprom("g4",O); end;

LAND dl): LAND dO): LAND d3): LAND d2);

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High-Performance Raster Graphics for Microcomputer Systems

Andreas Bcchtolsheim and Forest Baskett Computer Systems Laboratory

Stanford University Stanford, California 94305

A frame buffer architecture is presented that reduces the overhead of frame butTer updating by three means. First, the bit-map memory is (x,y) addressable, whereby a string of pixels can be accessed in parallel. Second, the pixel-change operation is perfonned by hardware in a single read-modiFy-write cycle. TIlird. mUltiple objects in the frame buffer are addressable simultaneously by a set of address registers. The remaining task of generating (x,y) addresses and providing new data can be managed rapidly by current microprocessors or DMA-devices.

With a modest expenditure of hardware, this architecture eliminates all the bit-shifting, bit-masking, and bit-manipulation conventionally associated with frame buffer graphics, while retaining the full generality of user-programmable control. The particular implementation described allows raster manipulation at full bit-map memory bandwidth. It can paint a 16X16 pixel character into the frame butTer in 16 microseconds and can modify a 1024X1024 pixel raster in 64 milliseconds.

Keywords: Raster-Scan Graphics, Frame ButTer, Bit-Map, Raster Operation, Functional Memory

This work has been supported in part by DARPA-MDA-903-79-C-0680. by Stanford Artificial Intelligence Laboratory, and by Stanford Linear Accelerator Center.

Penaission to copy without fee all or part of this material i. granted provided that the copies are not .. de or distributed for direct c~rcial advantaae, the ACM copyriabt notice aDd the title of the publication and it. date appear, and notice is liven that copyinl is by penaisaion of the AasociatioD for Cosputinl Hac:hiaery. To copy otherwi •• , or to republish, require. a fee and/or specific penaiuiou.

01980 ACM 0-89791-021-4/80/0700-0043 $00.75

43

1_ Introduction

The raster-scan graphics system described in this paper is part of a workstation being designed at Stanford University to support projects in design automation (VLS1) and advanced text processing (TEX). In bricf, the workstations conLains a powerful 16-bit microprocessor, a substantial main memory, and a local network interface for accessing centralized file servers or remote large-scale computing resources_ Each station also supports one or more high-resolution displays.

Using a commercial 16-bit microprocessor as the main processor of the workstation, it is difficult to achieve adequate frame buffer manipulation speed. TIle microcomputer processing bandwidth is simply insufficient to deal with the number of bits in a high­resolution frame buffer which is organized as a conventional memory.

OUf approach to this problcm is to organize the frame buffer in a different way. This architccture treats frame butTer updates as a a function with five parameters:

(X, y, Width, Operation, Data).

whereby X and Yare the address of a rectangle of size WidLhXl. to which the DaLa is applied with the specified Operation (see Figure 1).

x + Width

y

I 3it field to which Operation and Data

is applied

Figure 1. Functional Frame Buffer

In our implementation, width can range from 1 to 16 bits and the operation is a bit-wise boolean function. These five parameters are maintained in separate registers_ X and Y are loaded by referencing

windows in the main processor's address space; Width, Operation, and Data arc loaded from the data bus. In a single memory reference operation, the main processor then can provide a new address <x> or <y>, access a string of size <width> at location <x,y>, and perfonn the previously selected <operation> on the frame buffer with the new <data> provided.

This functional frame buffer architecture perfonns in hardware all bit-shifting, bit-masking. and bit-mampulation usually associated with frame buffers graphics. The only remaining task for the processor (or a DMA controller) is to generate the <x,y> addresses and transfer data to and from the frame buffer. Using the frame buffer function as a primitive, operations on rasters of arbitrary height and width can be implemented easily, such as RasterOP [1].

In our implementation, the frame buffer is a 64k by 16 bit (I024XI024) dual-port memory with sufficient bandwidth to allow one frame buffer modification (read-modify-write) cycle every microsecond. Any processor that can provide a new address and data at that rate fully utilizes the available frame buffer memory bandwidth. This means that:

painting a I6X16 pixel character takes 16 microseconds; vectors are drawn at a rate of 1 pixel per microsecond; a 1024X768 raster can be modified in 48 milliseconds; scrolling a 1024 X 768 rectangle in any direction takes %

milliseconds.

The speed of these operations eliminates special-purpose hardware for scrolling, vector generation, and cursor motion. Instead, a functional frame butTer architecture allows generalized manipulation of raster images in a truly interactive fashion.

2. The Problem: Band"idth

A frame buffer display system typically consists of an application program, a frame buffer, and a video monitor (Figure 2). The frame buffer contains the image in a raster (bit-pattern) representation. Two processes work on the frame butTer, one updating the frame buffer to change the image it represents, the other refreshing the video monitor.

The bandwidth of the refresh process is proportional to the number of pixels displayed. the bits per pixeL and the refresh rate, whereas the bandwidth of the update process depends on the response-time requirements of the application. As frame buffer sizes grow because of decreasing memory costs, the bandwidth requirements will increase proportionally.

For example, a high-resolution monochrome monitor with a display area of 1024 by 768 one-bit-pixels and 60 Hz non-interlaced refresh demands a bandwidth of approximately 64 MbitJsec; the same bandwidth is necessary for a standard video-monitor with a di~lay area of 640 by 480, four bits per pixel. and interlaced 60 Hz refresh. The frame butTer memory has to accomodate both processes. If the bit-map memory has an overall bandwidth of, say, 80 MbitJsec, then the refresh process leaves 16 MbitJsec for update purposes.

Application Update Frame Refresh Video -" ...

~

Program Process Buffer Process Monitor

Figure 2. Model of a Frame Buffer Graphics System

44

The ratio of refresh over update bandwidth indicates the number of display (refresh) times necessary to modify an entire frame buffer; in our case, four refresh times or 66 milliseconds. As this ratio gets larger. the interactiveness of the display decreases, limiting the usefulness of the display. Also, a slower update uses up a larger portion of the overall system resources, depleting the processing cycles remaining for the application program and other tasks.

Ideally, one would like to update the frame buffer at the full available bit-map memory bandwidth. However, it is difficult to provide such a high update rate. Each frame buffer operation is accompanied by the overhead of generating the frame buffer address, performing the raster operation, masking bits that shall remain unchanged, and loop control. The effective bandwidth of a processor performing all of these operations thus needs to be considerably higher than the update bandwidth alone. and far exceeds the bandwidth of currently available microcomputers. The problem thus is how to achieve fast frame butTer manipulation with a processor that is limited in speed.

3. Conventional Frame ButTer Graphics Architectures

Two frame buffer architectures can be distinguished: Those in which the frame buffer is part of main memory and those where it isn't. In both cases. the frame buffer is typically a dual POrt memory witll one port dedicated for refresh to unload the refresh bandwidth from the memory bus.

Figure 3.1. Frame Butfer in Memory

Figure 3.2. Frame Buffer Isolated

The frame buffer in main memory architecture (Figure 3.1) makes the frame buffer directly accessible to the main processor. However, it is almost always ineffIcient to manipulate the frame buffer with the main processor. except with processors that have special instructions for frame buffer manipulation. such as BitBll in the Alto computer rt). Thus one usually needs a peripheral "graphics processor" for high-speed frame buffer manipulation, which receives commands from the main processor. Because there is only a single memory bus, contention between the main processor and the graphics processor can result Typically a significant portion of the system resources must be dedicated for frame buffer manipulation in this architecture.

The frame buffer nol in main memory architecture isolates the frame butTer from the system by placing the frame buffer under exclusive control of a dedicated graphics processor (Figure 3.2). The graphics processor provides a standard set of frame buffer manipulation functions, receiving commands and data from the main processor.

An independent graphics subsystem has a number of advantages. First, with a sufficient rich set of graphics primitives, demands on system resources arc greatly reduced. Second, it is straightforward to meet given update bandwidth requir('ments with a specially-designed comroller. Third, a self-contained graphics subsystem can be interfaced to a variety of host computers. For all of these reasons most commercial high-performance raster-scan systems have adopted this architecture.

A difficulty introduced by the memory partitioning is the limited memory space in the graphics subsystem. Almost all frame butTer applications require memory space in addition to the visible bit-map, to store character sets, graphical objects, and so forth. If main memory were used for this purpose, data has to be moved across the graphics pr~essor interface. putting load back on the main processor system. This problem can partly be solved by making the frame butTer larger than the visible display area, and to use the excess invisible part as a software controlled cache for graphical objects such as the currently used character fonts. With the cache, communication bandwidth between host and graphics processor is reduced to the remaining miss-rate.

In the context of a low-cost microcomputer system, both architectures h~ve th~ disadvantage to require a graphics processor, typically a bit­~hce. mlcroprogrammable machine. Another, more subtle, problem mtroduced by a graphics processor is the constraint of predefined frame buffer operations. It will be difficult. if not impossible, for users to extend the graphics processor firmware. This is less a problem for well-defined applications such as vector drawing, but it limits the exploration of novel frame buffer operations (for example area ftll. grey scale backgrounds, and brushes), as discussed in Newman and Sproull [1].

4. The Functional Frame Ruffer Architecture

An ~1ternative approac~ to speed up frame buffer updating is to proVIde a more appropnate representation for raster manipulation at the hardware level.

45

4.1. Pixel Addressing

If the bit-map memory is organized just as other memory into physical memory words, the task of mapping the pixel-addressing into physical words has to be done in software or finn ware, a constant overhead for every frame buffer access. This overhead can be avoided if the frame buffer is (x,y) addressable. Since the desired frame buffer manipulation bandwidth can only be reached by working on multiple pixels in parallel. we shall access as many bits as the data-paths in the system can transfer, and have a facility to specify fewer bits if so desired. In our implementation, a lX16 rectangle can be accessed at an arbitrary (x,y) location. An alternative solution, implemented by Sutherland and Sproull, is to access 8XS rectangles [3).

4.2. Pixel Operation

For a one-bit per pixel frame buffer, a small set of boolean operations suffices for the actual frame butTer bit-change operation: Bit-Move, Bit-Or, Bit-And, and Bit-XOR, whereby the new data can be optionally inverted (1,2]. Executing this operation locally to the frame-butTer in a single read-modify-write memory cycle gains at least a factor of two in bandwidth over doing so in the main processor with separate read-write cycles. The source data is either supplied from the main processor or is accessed in an earlier frame buffer memory cycle.

4.3. Control

Control of frame buffer manipulation is retained by the main processor in a completely user-programmable fashion. When the raster operation and the width field have been set, the only remaining task is to provide (x,Y) addresses and to transfer data to or from the frame buffer. Making the (x,y) address registers independent windows in the processors address space, rectangular graphical objects can be accessed using autoincrementing addressing modes or DMA devices.

5. Implementation

We have implemented a functional frame buffer architecture with a frame butTer size of 1024X 1024 Bits or 128 kBytes. The aspect ratio can be reconfigured for a variety of visual display sizes such as 1170XS96 or 1024X768. In the latter case, invisible frame buffer space can be use for font storage. Memory planes can be stacked to provide up to eight bits per pixel.

5.1. Memory Organization

The 1024X1024 bits of memory are stored in 64 16k dynamic RAMs. This memory supports two organizations: for refresh purposes it consists of 16k 64-bit physical memory words which are aligned along horizontal scan lines. For update purposes, each 64-bit physical memory word is further divided into four 16-bit logical memory words, since the data paths are only 16 Bits wide (Figure 5.1.a).

For refresh cycles, all 64 RAM chips are read out in parallel into a 64 Bit buffer, whose content is shifted out to the video monitor (Figure 5.l.b). The timing of video refresh cycles depends on video bandwidth: high-resolution non-interlaced monitors require one refresh cycle every microsecond. Note that dynamic RAM refresh is done automatically by the video refresh.

15

31

48

63

S.2. Update Cycles

Figure 5.1.a

Memory Organization

Figure S.l.b

Refresh Cycle

Figure 5.1.c

Intraword Access

Figure S.l.d

Interword Access

Update cycles are read or read-modify-write cycles that alternate with refresh cycles. For bit-string addressing, 16 consecutive bits must be accessed starting on any bit boundary. Memory accesses can thus cross logical and physical word boundaries. The data is then aligned with a 16-bit shifter to appear normalized at the processor interface.

To access 16 bits within a physical word (Figure S.l.e), the appropriate memory chips are selected individually by controlling the row-address-strobe of each chip a function of the bit-address. All RAM chips receive the subsequent column-address-strobe, but only those selected with RAS will be enabled. The data-out from all logical words is ORed together before it is put on the data bus. If an update crosses a physical word boundary (Figure S.l.d), the memory chips in the next physical memory word must receive an address one higher than the other RAM chips. This is implemented by dividing the memory in two banks with separate address drivers (Figure 5.2). An adder increments the address for the lower bank by one if the access starts in the higher bank.

Adder Mux/Driver Bit Address<5>

Word Address<O: 13)

Decoder

Bit Address<O:5> I""t'I:: ';;;;;';';;';~~=-----~)~ASO .. 63

Figure 5.2. Memory Addressing

46

5.3. Function Unit

The function unit performs the actual bit-change operation in a single rcad-modify-write cycle. The bit-change operation is applied bit-wise to the source data and the old destination value to yield a new destination value. The source data can be either supplied by the main processor or by the frame buffer from a previous read cycle. The set of functions are:

Clear Ost ~ 0

Copy Dst ~ 8re Paint Ost ~ Dst OR 8re

Erase Ost ~ Dst AND NOT Sre

Invert Ost ~ Ost XOR Sre

Clear/ Cst ~ 1 Copyl Ost <- NOT 8re Paint! Ost ~ Dst OR NOT 8fC

Erase/ Dst <- Ost AND 8rc Invert/ Cst .. Os! XOR NOT 8re

The function unit is implemented as a programmable logic array (partitioned into four chips). The function has one more input, MASK, that inhibits the modification of the corresponding destination bits. causing these bits to be rewrinen with their old value. This is necessary if we desire to change fewer than 16 Bits at one time, for example when drawing vectors. The MASK is computed from the value of the WIDTH register and the destination address. The relation of the function unit to the rest of the graphic system is shown in Figure 5.3.

Address Bus

Data Bus {16}

Data·Out

(16)

Bit·map

Memory

1024T2

Address Bit -Address

logiC

.-----, Word·Adrs. Video

Control Sync

Figure 5.3. Data Paths in the Functional Frame Buffer

Video

5.4. The Graphics Controller Interface

TIle processor comm~l1icates with the graphics controller through a number of registers:

Data Data to and from the frame buffer X X coordinate Y Y coordinate Z Frame buffer plane Width Width of destination object OP Mode of function unit Control Data flow control

The X and Y registers are windows in the processor's address space, loaded as a sideeffect of readbg or writing frame buffer data within these windows. All other registers arc loaded explicitely from the data bus, since they are usually changed infrequently.

The processor uses read and write commands to initiate frame butTer read cycles and read-modify-write cycles. Whether the processor actually supplies or receives any 4ata in such an operation depends on the setting of tlle Control register.

The independent registers have the advantage that unchanged parameters need not be retransmitted, thereby reducing communication bandwidth between processor and graphics controller. On the other side, the registers must be changed for accessing and operating on different graphical objects. This problem is solved with a set of registers which is large enough to hold the working set required for frame buffer operations.

Most frame buffer operations, scrolling for example, involve two objects: a destination and a source. More complicated operations can involve three objects, for example when the source is first manipulated with a grey-scale pattern. Even more sets are useful to cache state information for objects that are refererenced often. For example, a cursor typically requires a cursor symbol object, a save area object, and a current location object For these reasons the design provides 16 complete register sets.

The details of the graphics controller interface will be usually invisible to application programs, which will interface to higher-level graphics packages.

6. Conclusions

High-resolution frame buffers require significant processing bandwidth for high-speed manipulation. Most current bit-map graphic systems organize the frame buffer just as ordinary memory. A functional frame buffer architecture was described that decomposes a frame buffer operation into pixel-access, pixel-operation, and control. By implementillg the access and operation function in hardware, one can greatly reduce the computation needed for frame buffer manipulation. A frame buffer was implemented that allows to access a lX16 rectangle at any (x,y) location and manipulate it with a preselected boolean function. In conjunction with a fast microprocessor or a DMA-controltcr, this frame buffer architecture allows raster manipulation at 32 Mbitlsec.

47

Figure 6.1. A sample 1024 by 768 image displayed on an interlaced monitor.

Figure 6.2. A prototype of the functional frame buffer. '!be large packages on the top center are the function unit PLAs.

7. References

[lJ W.M. Newman and R.F. Sproull, Principles of Interactive Computer Graphics. second edition, McGraw Hill, 1979.

[2J c.P. Thacker, et al., "Alto: A personal Computer", in D. Siewiorek, C.G. Bell and A. Newell, Computer Struclures: Readings and Examples. second edition, McGraw Hill. 1980.

[3J I.E. Sutherland, R.F. Sproull. S. Gupta. A. Thompson, personal communication.

[4] R.F. Sproull "Raster Graphics for Interactive Programming Environments", Xerox PARC Report CSL-79-6, June 1979.