· 2013-06-18 · revision: 2.63 december 2011 intel® 82576eb gigabit ethernet controller...

Revision: 2.63December 2011

Intel® 82576EB Gigabit Ethernet Controller Datasheet

LAN Access Division (LAD)

PRODUCT FEATURES

External Interfaces PCIe* v2.0 (2.5 GT/s) x4/x2/x1; called PCIe in this

document MDI (Copper) standard IEEE 802.3 Ethernet interface

for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab)

Serializer-Deserializer (SERDES) to support 1000Base-SX/X/LX (optical fiber) for Gigabit backplane applications.

SGMII for SFP/external PHY connections NC-SI (Type C) or SMBus for Manageability connection

to BMC. IEEE 1149.1 JTAG

Intel® I/O Acceleration Technology Stateless offloads (Header split, RSS) Intel® QuickData (DCA - Direct Cache Access)

Virtualization Ready Next Generation VMDq support (8 VMs) PCI-SIG Single Root I/O Virtualization (Direct

assignment) Queues per port: 16 TX queues and 16 RX queues

Full-Spectrum Security IPsec (256 SA’s) in 82576EB; IPsec not present in

82576NS [Non-Security] MACSec

Additional Product Details 25mm x 25mm Package Power 2.8W (max) Support for PCI 3.0 Vital Product Data Memories Parity or ECC Protection IPMI MC Pass-thru; Multi-drop NC-SI 802.1AS draft standard implementation Layout Compatible with 82575

Intel® 82576EB GbE Controller — Legal

Intel® 82576EB GbE Controller Revision: 2.63Datasheet December 20112

Legal

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Revisions — Intel® 82576EB GbE Controller

Revision: 2.63 Intel® 82576EB GbE ControllerDecember 2011 Datasheet 3

Revisions

Revision Date Comments

0.5 6/2007 Initial availability.

1.0 11/2007 Updates and corrections.

1.9 5/2008 PRQ release.

2.0 6/2008 SRA release.

2.1 7/2008 Maintenance update. Added checklist chapter.

2.2 11/2008 Maintenance update.

• ected device ID reference to 0x10C9.

• Section 3.3.1.7; Section 12.3.2.2.1 - EEPROM-less information updated; stronger statements about EEPROM-less design.

• Table 3-17 - Device ID corrected.

• GIO_PWR_GOOD updated to PERST# throughout.

• Section 6.1 - More PXE information documented. Entire section updated. See PXE listings on EEPROM map. Also, links added for entire EEPROM reference map.

• Section 7.10.3.5.1, Section 7.10.3.5.2- Notes added after VFRE filtering paragraphs in numbered list.

• Section 8.8.7, Section 8.8.8, Section 8.8.9, Section 8.8.10 - The ICR, ICS, IMS, IMC registers were corrected. See bit 3 in each.

• Chapter 10.0, System Manageability updated; organization changed; some additional information provided.

• Section 10.6.2.12 - Bit description in table updated (to 0x21).

• Table 10-10 - IPV4 and IPV6 filter parameter information corrected.

• Table 10-33 - List of supported commands has been updated.

• Table 11.4.2.1 - Current consumption data updated. See bold text in table. Also, see power data in summary on title page.

• Table 12-2 - Additional magnetics recommendation added.

2.3 12/2008 • Section 6.2.18 - Bit 15 information updated; Enable WAKE# Assertion.

2.4 4/1/2009 • Jumbo frame size consistently indicated at 9500 bytes (max).

• SKU 82576NS documented. The IPsec function is present in the 82576EB SKU. IPsec is not present in the 82576NS SKU. This is indicated throughout the document.

• Section 3.3.4.2, Flash Write Control - Typing correction. Note that attempts to write to the Flash device when writes are disabled (EEC.FWE=01b) should not be attempted.

• Section 3.4.2, Software Watchdog - Updated. Edited to describe the software interrupt (ICR[26]) and to reduce confusion.

• Section 3.5.6.5.1, Setting the 82576 to External PHY loopback Mode - Text added at the end of the section for clarity: The above procedure puts the device in PHY loopback mode. After using the procedure, wait for link to become up. Once PHY register 1 bit 2 is set (this can take up to 750ms), transmit and receive normally. If you are unable to get link after 750ms, reset the PHY using CTRL.PHY_RST and then repeat the above procedure. When exiting External PHY loopback mode, a full PHY reset must be done. Use CTRL.PHY_RST.

Intel® 82576EB GbE Controller — Revisions


• Section 4.4, Device Disable - The following phrase in the section has been changed: The EEPROM "Power Down Enable" bit (Section 6.2.7) enables device disable mode (hardware default is that the mode is disabled).

• Table 4-5, 82576 Reset Effects - Per Function Resets - Table updated. See the entries on PCI Configuration registers and the associated footnotes.

• Section 4.2.1.6.3, VF Software Reset - Replaced VFCTRL with VTCTRL (corrects a typo). Added information that indicates what happens when VTCTRL.RST is set. Setting VTCTRL.RST resets interrupts and queue enable bits. Other VF registers are not reset.

• Section 5.0, Power Management updated for clarity.

• Section 6.10.7.1, iSCSI Module Structure - Description of structure updated. Multiple errors were corrected

• Section 7.1.3.1, Host Buffers - Text added. For advanced descriptor usage, the SRRCTL.BSIZEHEADER field is used to define the size of the buffers allocated to headers. The maximum buffer size supported is 960 bytes..

• Section 8.2.4, MDI Control Register - MDIC (0x00020; R/W) - Description of bit 31 corrected.

• Section 8.10.2, Split and Replication Receive Control - SRRCTL (0x0C00C + 0x40*n [n=0...15]; R/W). Maximum 960 bytes now indicated for SRRCTL.BSIZEHEADER.

• Section 10.4.4.3, RMCP Filtering - Title of section updated.

• Section 10.5.10.1.4, Force TCO Command and Section 10.6.2.13.1, Perform Intel TCO Reset Command (Intel Command 0x22) - Added description of RESET_MGMT bit.

• Section 10.5.12, Example Configuration Steps - Added pseudocode describing the setup of common filtering configurations.

• Table 10-35, Command Summary - Commands added, see:

0x02 0x67/68 Set EtherType Filter/Packet Add. Ext. Filter0x03 0x67/68 Get EtherType Filter/Packet Add. Ext. Filter

• Section 10.5.10.2.1, Receive TCO LAN Packet Transaction. Description of packet structure added.

• Section 10.6.2.6.19, Set Intel Filters - Packet Addition Extended Decision Filter Command (Intel Command 0x02, Filter parameter 0x68). Text in section updated: Extended decision filter index range adjusted to 0..4.

• Table 11-5, Current Consumption Details - Added SGMII note to table. (3) To estimate power for SGMII mode, use the SerDes mode power numbers provided.

• Table 11-22, Package Height - Table added. Provides a summary of package height information.

2.41 4/8/2009

5/5/2009

• Section 7.1.4, Legacy Receive Descriptor Format and Section 7.2.2, Transmit Descriptors. Recommendation regarding legacy descriptors changed to ‘must not be used’ from ‘should not be used.’

2.42 7/5/2009 Internal release for test and review.

2.43 10/2/2009 MACSec capability exposed. You must have a MACSec-ready switch in order to com-plete the ecosystem and make use of MACSec functionality.Maintenance issues addressed:• Section 7.2.4.7.2, TCP/IP/UDP Headers for the Subsequent Frames and Section

7.2.4.7.3, TCP/IP/UDP Headers for the Last Frame updated to document UDP fields.

• Section 7.3.3.2, Interrupt Moderation and Section 8.8.12, Interrupt Throttle - EITR (0x01680 + 4*n [n = 0...24]; R/W) updated to correct minor issues; redundant data removed.

• Table 7-9, VLAN Tag Field Layout (for 802.1q Packet) - Note added to table that clarifies usage:

• NOTE: This table is relevant only if VMVIR.VLANA = 00b (use descriptor command) for the queue.




• Section 7.10.3.2.1, Filtering Capabilities - Typo corrected. In bullet, VM changed to VF. Below:

• Promiscuous multicast & enable broadcast per VF.

• Section 7.10.3.8, Offloads - Note added; text below:• NOTE: VLAN strip offload is determined based only on the L2 MAC address. In

order to make sure VLAN strip offload is correctly applied, all packets should be initially forwarded using one of the L2 MAC address filters (RAH/RAL, UTA, MTA, VMOLR.BAM, VMOLR.MPE.

• Two table titles corrected. Could have caused confusion. Minor edits also made to field descriptions.

• Table 7-35, TCP/IP or UDP/IP Packet Format Sent by Host • Table 7-36, TCP/IP or UDP/IP Packet Format Sent by 82576

• Section 8.10.7, Receive Descriptor Ring Length - RDLEN (0x0C008 + 0x40*n [n=0...15]; R/W) - Description updated. LEN text added: The maximum allowed value is 0x80000 (32K descriptors).

• Section 8.12.2, Transmit Control Extended - TCTL_EXT (0x0404; R/W) - Default value of COLD corrected (0x42) in text description.

• Section 10.5.10.1.4, Force TCO Command - Clarification note added to table. See below:

• NOTE: Before initiating a Firmware reset command, one should disable TCO receive via Receive Enable Command -- setting RCV_EN to 0 -- and wait for 200 milliseconds before initiating Firmware Reset command. In addition, the MCshould not transmit during this period.

• Section 10.5.10.2.1, Receive TCO LAN Packet Transaction - Receive TCO packet format table updated; numerous changes. For clarity.

• Section 10.7.10, Read Fail-Over Configuration Host Command - Both tables in section updated.

• Table 10-49, Commands to Read the Fail-Over Configuration Register - Last row in table deleted; was incorrect.

• Table 10-50, States Returned - Description column (byte 1) updated. Description was confusing.

• Section 10.5.12.3.1, Example 3 - Pseudo Code - Pseudo Code, step 5: MAC Address Filtering is bit 0, not bit 1. Also the MDEF value is 00000009 and not 00000040.

• Section 10.5.12.4.1, Example 4 - Pseudo Code - Step 5: Configure MDEF[0], MDEF value is 0000004 and not 00000040.

2.44 10/14/2009 • Section 9.6.4.3, PCIe SR-IOV Control Register (0x168; RW); Bit 4; ARI Capable Hierarchy. Text updated.

• Section 10.0, System Manageability; More information on MACSec parameters provided. See Section 10.5.10.1.6, Update MACSec Parameters and Section 10.8, MACSec and Manageability in particular.

• Section 10.5.10.1.3, Receive Enable Command; Section 10.5.10.2.5, Read Management Receive Filter Parameters. Bit order expression corrected in two tables. See bold text.

• References to BMC changed to MC if the reference is not programmatic.

2.45 10/30/2009 • Section 3.3.1.6, EEPROM Recovery. Section now exposed in the datasheet.

• Section 8.10.8, Receive Descriptor Head - RDH (0x0C010 + 0x40*n [n=0...15]; RO) and Section 8.12.11, Transmit Descriptor Head - TDH (0x0E010 + 0x40*n [n=0...15]; RO). Both registers indicated RW incorrectly. Changed to RO.

• Table 10-33, Supported NC-SI Commands and Table 10-34, Optional NC-SI Features Support. List of supported commands/functions updated to correct an error in our support statements. See bold text in both tables.


Intel® 82576EB GbE Controller — Revisions


2.46 12/1/2009 • Table 7-18, Table 7-39, Table 7-41. ‘Packet is greater than 1552 bytes; (LPE=1b).’ updated to ‘Packet is greater than 1518/1522/1526 bytes; (LPE=1b).’

• Chapter 8.0, Receive Control Register - RCTL (0x00100; R/W). Description of LPE field updated.

• Chapter 10.0, System Manageability. Changes and clarifications to list of NC-SI commands. Added the Get Ethertype and Get Intel Filters - Packet Addition Extended Decision Filter commands. Added the Set/Get Unicast/Broadcast/Multicast Packet Reduction filters. Added a recommendation to use the Packet Addition Extended Decision Filter commands (0x68) instead of the Packet Addition Decision Filter commands (0x61).

2.47 3/10/2010 • Chapter 5.0, Power Management. In tables where these fields occur, the following fields have been flipped to reflect this order. They were previously reversed in the tables.

• Possible VLAN Tag• Possible LLC/SNAP Header

• Chapter 5.0, Power Management. Table 5-5 through Table 5-10; offset and byte information has been updated.

• Section 6.10.6.1, Main Setup Options PCI Function 0 (Word 0x30). Description of Bit 5 updated to “IBD: iSCSI Boot Disable.”

• Section 6.10.6.7, iSCSI Option ROM Version (Word 0x36). Description of Word 0x36 added. Describes option ROM versions.

• Section 6.2.18, PCIe Control (Word 0x1B). Decription of Bit 12 updated to “Lane Reversal Disable”.

• Section 7.10.3.6.2, Replication Mode Disabled - The following list item was deleted: ‘3. Multicast or Broadcast - If the packet is a Multicast or Broadcast packet and was not forwarded in step 1 and 2, set the default pool bit in the pool list (from VT_CTL.DEF_PL).’

• Section 7.10.3.4, Size Filtering. This section added.

• Section 10.5.10.1.6, Update MACSec Parameters. Table rows in the section updated. See:

• Initialize MACSec RX • Initialize MACSec TX• Set MACSec TX Key• Enable MACSec

• Section 11.4.2.2, Digital I/O. Table Notes have been corrected in the table that resides in the section. Two notes weren’t referenced in the table correctly.

• Appendix A. Changes from the 82575. Appendix added (to datasheet).

2.48 6/14/2011 • NC-SI identified as Type C..

• Section 7.2.5.3, SCTP CRC Offloading. This note added to section: The CRC field of the SCTP header must be set to zero prior to requesting a CRC calculation offload.

• Section 8.17.23, Time Sync RX Configuration - TSYNCRXCFG (0x05F50; RW). The TRNSSPC description column was updated.

• LinkSec references corrected; to MACSec.

2.49 8/11/2010 • Table 2-8; JTAG Reset Input (AC5) described.

• Section 6.10.5, PBA Number Module (Word 0x08, 0x09). PBA format updated.

• Section 7.1.1.2, Rx Queuing in a Virtualized Environment. Corrected.

2.50 9/14/2010 • Table 2-9, Reserved Pins and No-Connects. Table corrected.

• Section 6.10.5, PBA Number Module (Word 0x08, 0x09). Language of section updated to address issues.

• Section 8.8.7, Interrupt Cause Read Register - ICR (0x01500; RC/W1C). Table was updated. See ICR.MDDET [bit 28].

• Table 11-14, NC-SI AC Specifications. Table corrected.




2.6 11/5/2010 • On Title page, in feature table, under additional product features: bullet updated to “Memories Parity or ECC Protection”.

• Chapter 6.0, Non-Volatile Memory Map - EEPROM. Chapter now includes example settings for sample EEPROM and makes hardware settings clear.

• Section 7.2.2.3.11, PAYLEN (18). Note text updated.

• Section 8.12.14, Tx Descriptor Completion Write–Back Address Low - TDWBAL (0x0E038 + 0x40*n [n=0...15]; R/W). Description clarified; see bits 32:2.

2.61 12/10/2010 • Indicated hardware defaults in Chapter 6.0, Non-Volatile Memory Map - EEPROM. Added loaded values for 82576_dev_start_No_Mgmt_Copper_A1 image, where applicable.

2.62 5/5/2011 • Section 1.0, Introduction. Simple block diagram of part added.

• Section 3.5.6.1, General and Section 3.5.6.2, MAC Loopback. Information added on MAC Loopback. Not used on this device.

• Section 6.10.2, OEM specific (Word 0x04). Definition updated.

• Section 6.10.6.1, Main Setup Options PCI Function 0 (Word 0x30). Word updated. See bits 5, 2-0.

• Section 7.1.1.5, L3/L4 5-Tuple Filters. Note added to clarify the filtering of fragmented packets.

• Section 7.1.2.1.1, Unicast Filter. Error corrected. There are 24 host unicast addresses, not 16 as previously stated.

• Section 9.5.5.12, Device Control 2 Register (0xC8; RW). Note added. Expresses write limitation.

• Section 11-11, External Clock Oscillator Connectivity to the 82576. Figure corrected (font problem).

2.63 12/9/2011 • Figure 11-5 . Random line removed from drawing.

• Section 3.5.8.2.1, Transition to SerDes/SGMII Mode. Procedure updated.

• Section 6.10.1, Compatibility (Word 0x03). Bit 14, SerDes Forced Mode Enable, description added.

• Section 6.8.7, NC-SI Configuration (Offset 0x6). Updated.

• Section 9.4.11.1, 32-bit Mapping ,Section 9.4.11.2, 64-bit Mapping without I/O BAR, Section 9.4.11.3, 64-bit Mapping Without Flash BAR; Prefetch Memory, Bit 3 description update. New text: “This bit should be set only on systems that do not generate prefetchable cycles.”


https://vthsd.intel.com/hsd/laddocs/#doc/default.aspx?doc_id=1939

Intel® 82576EB GbE Controller — Contents


Contents

1.0 Introduction .............................................................................................................................. 431.1 Scope ...................................................................................................................................... 441.2 Terminology and Acronyms......................................................................................................... 44

1.2.1 External Specification and Documents .................................................................................... 461.2.1.1 Network Interface Documents......................................................................................... 461.2.1.2 Host Interface Documents .............................................................................................. 471.2.1.3 Virtualization Documents ............................................................................................... 471.2.1.4 Networking Protocol Documents...................................................................................... 471.2.1.5 Manageability documents ............................................................................................... 471.2.1.6 Security Documents ...................................................................................................... 47

1.2.2 Intel Application Notes ......................................................................................................... 471.2.3 Reference Schematics .......................................................................................................... 471.2.4 Checklists........................................................................................................................... 48

1.3 Product Overview ...................................................................................................................... 481.3.1 System Configurations ......................................................................................................... 48

1.4 External Interface...................................................................................................................... 481.4.1 PCIe* Interface................................................................................................................... 481.4.2 Network interfaces .............................................................................................................. 481.4.3 EEPROM Interface ............................................................................................................... 491.4.4 Serial Flash Interface ........................................................................................................... 491.4.5 SMBus Interface.................................................................................................................. 491.4.6 NC-SI Interface................................................................................................................... 491.4.7 MDIO/2 wires Interfaces....................................................................................................... 491.4.8 Software-Definable Pins (SDP) Interface (General-Purpose I/O)................................................. 501.4.9 LEDs Interface .................................................................................................................... 50

1.5 Comparing Product Features ....................................................................................................... 501.6 Overview of New Capabilities ...................................................................................................... 54

1.6.1 IPsec Off Load for Flows ....................................................................................................... 541.6.2 Security ............................................................................................................................. 551.6.3 Transmit Rate Limiting (TRL) ................................................................................................ 551.6.4 Performance ....................................................................................................................... 55

1.6.4.1 Tx Descriptor Write-Back ............................................................................................... 551.6.5 Rx and Tx Queues ............................................................................................................... 551.6.6 Interrupts .......................................................................................................................... 551.6.7 Virtualization ...................................................................................................................... 56

1.6.7.1 PCI SR IOV .................................................................................................................. 561.6.7.2 Packets Classification..................................................................................................... 561.6.7.3 Hardware Virtualization.................................................................................................. 561.6.7.4 Bandwidth Allocation ..................................................................................................... 57

1.6.8 VPD................................................................................................................................... 571.6.9 64 bit BARs support............................................................................................................. 571.6.10 IEEE 1588 - Precision Time Protocol (PTP) .............................................................................. 57

1.7 Device Data Flows ..................................................................................................................... 571.7.1 Transmit Data Flow ............................................................................................................. 571.7.2 Receive Data Flow ............................................................................................................... 58

2.0 Pin Interface ............................................................................................................................. 612.1 Pin Assignment ......................................................................................................................... 61

2.1.1 PCIe ................................................................................................................................. 612.1.2 Flash and EEPROM Ports (8) ................................................................................................. 622.1.3 System Management Bus (SMB) Interface ............................................................................. 632.1.4 NC-SI Interface Pins ........................................................................................................... 632.1.5 Miscellaneous Pins .............................................................................................................. 642.1.6 SERDES/SGMII Pins ............................................................................................................ 642.1.7 SFP Pins ............................................................................................................................ 652.1.8 Media Dependent Interface (PHY’s MDI) Pins........................................................................... 65

2.1.8.1 LED’s (8) ..................................................................................................................... 652.1.8.2 Analog Pins ................................................................................................................. 66

Contents — Intel® 82576EB GbE Controller


2.1.9 Testability Pins ................................................................................................................... 662.1.10 Reserved Pins and No-Connects ............................................................................................ 662.1.11 Power Supply Pins ............................................................................................................... 68

2.2 Pull-ups/Pull-downs ................................................................................................................... 682.3 Strapping ................................................................................................................................. 712.4 Interface Diagram ..................................................................................................................... 722.5 Pin List (Alphabetical) ................................................................................................................ 732.6 Ball Out.................................................................................................................................... 75

3.0 Interconnects............................................................................................................................ 773.1 PCIe ........................................................................................................................................ 77

3.1.1 PCIe Overview .................................................................................................................... 773.1.1.1 Architecture, Transaction and Link Layer Properties ........................................................... 783.1.1.2 Physical Interface Properties........................................................................................... 793.1.1.3 Advanced Extensions..................................................................................................... 79

3.1.2 Functionality - General......................................................................................................... 793.1.2.1 Native/Legacy .............................................................................................................. 793.1.2.2 Locked Transactions ...................................................................................................... 793.1.2.3 End to End CRC (ECRC) ................................................................................................. 79

3.1.3 Host I/F ............................................................................................................................. 803.1.3.1 Tag IDs ....................................................................................................................... 80

3.1.3.1.1 TAG ID Allocation for Read Transactions........................................................................ 803.1.3.1.2 TAG ID Allocation for Write Transactions ....................................................................... 80

3.1.3.1.2.1 Case 1 - DCA Disabled in the System: .................................................................... 813.1.3.1.2.2 Case 2 - DCA Enabled in the System, but Disabled for the Request: ........................... 813.1.3.1.2.3 Case 3 - DCA Enabled in the System, DCA Enabled for the Request:........................... 81

3.1.3.2 Completion Timeout Mechanism...................................................................................... 813.1.3.2.1 Completion Timeout Enable ......................................................................................... 823.1.3.2.2 Resend Request Enable............................................................................................... 823.1.3.2.3 Completion Timeout Period.......................................................................................... 83

3.1.4 Transaction Layer................................................................................................................ 843.1.4.1 Transaction Types Accepted by the 82576 ........................................................................ 84

3.1.4.1.1 Configuration Request Retry Status .............................................................................. 853.1.4.1.2 Partial Memory Read and Write Requests ...................................................................... 85

3.1.4.2 Transaction Types Initiated by the 82576 ......................................................................... 853.1.4.2.1 Data Alignment.......................................................................................................... 853.1.4.2.2 Multiple Tx Data Read Requests ................................................................................... 86

3.1.4.3 Messages..................................................................................................................... 863.1.4.3.1 Message Handling by the 82576 (as a Receiver)............................................................. 863.1.4.3.2 Message Handling by the 82576 (as a Transmitter) ........................................................ 87

3.1.4.4 Ordering Rules ............................................................................................................. 873.1.4.4.1 Out of Order Completion Handling ................................................................................ 88

3.1.4.5 Transaction Definition and Attributes ............................................................................... 883.1.4.5.1 Max Payload Size ....................................................................................................... 883.1.4.5.2 Traffic Class (TC) and Virtual Channels (VC) .................................................................. 883.1.4.5.3 Relaxed Ordering ....................................................................................................... 883.1.4.5.4 Snoop Not Required ................................................................................................... 893.1.4.5.5 No Snoop and Relaxed Ordering for LAN Traffic.............................................................. 89

3.1.4.5.5.1 No-Snoop Option for Payload ................................................................................ 903.1.4.5.5.2 No Snoop Option for TSO Header ........................................................................... 90

3.1.4.6 Flow Control................................................................................................................. 903.1.4.6.1 82576 Flow Control Rules............................................................................................ 903.1.4.6.2 Upstream Flow Control Tracking................................................................................... 913.1.4.6.3 Flow Control Update Frequency.................................................................................... 913.1.4.6.4 Flow Control Timeout Mechanism ................................................................................. 91

3.1.4.7 Error Forwarding........................................................................................................... 913.1.5 Data Link Layer................................................................................................................... 91

3.1.5.1 ACK/NAK Scheme ......................................................................................................... 913.1.5.2 Supported DLLPs .......................................................................................................... 923.1.5.3 Transmit EDB Nullifying ................................................................................................. 93

3.1.6 Physical Layer..................................................................................................................... 93



3.1.6.1 Link Width ................................................................................................................... 933.1.6.2 Polarity Inversion.......................................................................................................... 933.1.6.3 L0s Exit latency ............................................................................................................ 933.1.6.4 Lane-to-Lane De-Skew .................................................................................................. 933.1.6.5 Lane Reversal............................................................................................................... 943.1.6.6 Reset .......................................................................................................................... 943.1.6.7 Scrambler Disable ......................................................................................................... 95

3.1.7 Error Events and Error Reporting ........................................................................................... 953.1.7.1 Mechanism in General.................................................................................................... 953.1.7.2 Error Events ................................................................................................................. 963.1.7.3 Error Pollution .............................................................................................................. 983.1.7.4 Completion with Unsuccessful Completion Status............................................................... 983.1.7.5 Error Reporting Changes ................................................................................................ 98

3.1.8 Performance Monitoring ....................................................................................................... 993.1.8.1 Leaky Bucket Mode ....................................................................................................... 99

3.1.9 PCIe Power Management.................................................................................................... 1003.1.10 PCIe Programming Interface ............................................................................................... 100

3.2 Management Interfaces ............................................................................................................ 1003.2.1 SMBus ............................................................................................................................. 100

3.2.1.1 Channel Behavior.........................................................................................................1003.2.1.1.1 SMBus Addressing.....................................................................................................1003.2.1.1.2 SMBus Notification Methods........................................................................................101

3.2.1.1.2.1 SMBus Alert and Alert Response Method ................................................................1013.2.1.1.2.2 Asynchronous Notify Method ................................................................................1023.2.1.1.2.3 Direct Receive Method.........................................................................................103

3.2.1.1.3 Receive TCO Flow .....................................................................................................1033.2.1.1.4 Transmit TCO Flow....................................................................................................1043.2.1.1.5 Transmit Errors in Sequence Handling..........................................................................1043.2.1.1.6 TCO Command Aborted Flow ......................................................................................1053.2.1.1.7 Concurrent SMBus Transactions ..................................................................................1053.2.1.1.8 SMBus ARP Functionality............................................................................................105

3.2.1.1.8.1 SMBus ARP in Dual-/Single-Address Mode..............................................................1063.2.1.1.8.2 SMBus ARP Flow.................................................................................................1063.2.1.1.8.3 SMBus ARP UDID Content....................................................................................107

3.2.1.1.9 LAN Fail-Over Through SMBus ....................................................................................1093.2.2 NC-SI .............................................................................................................................. 109

3.2.2.1 Electrical Characteristics ...............................................................................................1093.2.2.2 NC-SI Transactions ......................................................................................................110

3.3 Flash / EEPROM....................................................................................................................... 1103.3.1 EEPROM Interface ............................................................................................................. 110

3.3.1.1 General Overview.........................................................................................................1103.3.1.2 EEPROM Device ...........................................................................................................1113.3.1.3 Software Accesses .......................................................................................................1113.3.1.4 Signature Field ............................................................................................................1123.3.1.5 Protected EEPROM Space ..............................................................................................112

3.3.1.5.1 Initial EEPROM Programming ......................................................................................1123.3.1.5.2 Activating the Protection Mechanism............................................................................1123.3.1.5.3 Non Permitted Accessing to Protected Areas in the EEPROM............................................112

3.3.1.6 EEPROM Recovery........................................................................................................1133.3.1.7 EEPROM-Less Support ..................................................................................................113

3.3.1.7.1 Access to the EEPROM Controlled Feature.....................................................................1143.3.2 Shared EEPROM ................................................................................................................ 115

3.3.2.1 EEPROM Deadlock Avoidance .........................................................................................1153.3.2.2 EEPROM Map Shared Words ..........................................................................................115

3.3.3 Vital Product Data (VPD) Support ........................................................................................ 1163.3.4 Flash Interface.................................................................................................................. 117

3.3.4.1 Flash Interface Operation ..............................................................................................1173.3.4.2 Flash Write Control.......................................................................................................1183.3.4.3 Flash Erase Control ......................................................................................................118

3.3.5 Shared FLASH................................................................................................................... 1193.3.5.1 Flash Access Contention................................................................................................119



3.3.5.2 Flash Deadlock Avoidance .............................................................................................1193.4 Configurable I/O Pins ............................................................................................................... 120

3.4.1 General-Purpose I/O (Software-Definable Pins) ......................................................................1203.4.2 Software Watchdog ............................................................................................................120

3.4.2.1 Watchdog Re-arm ........................................................................................................1213.4.3 LEDs ................................................................................................................................121

3.5 Network Interfaces .................................................................................................................. 1213.5.1 Overview ..........................................................................................................................1213.5.2 MAC Functionality...............................................................................................................122

3.5.2.1 Internal GMII/MII Interface ...........................................................................................1223.5.2.2 MDIO/MDC..................................................................................................................122

3.5.2.2.1 MDIC Register Usage.................................................................................................1233.5.2.3 Duplex Operation with Copper PHY .................................................................................124

3.5.2.3.1 Full Duplex...............................................................................................................1243.5.2.3.2 Half Duplex ..............................................................................................................124

3.5.3 SerDes, SGMII Support .......................................................................................................1253.5.3.1 SerDes Analog Block ....................................................................................................1253.5.3.2 SerDes/SGMII PCS Block ..............................................................................................1253.5.3.3 GbE Physical Coding Sub-Layer (PCS).............................................................................125

3.5.3.3.1 8B10B Encoding/Decoding .........................................................................................1263.5.3.3.2 Code Groups and Ordered Sets ...................................................................................126

3.5.4 Auto-Negotiation and Link Setup Features .............................................................................1273.5.4.1 SerDes Link Configuration .............................................................................................127

3.5.4.1.1 Signal Detect Indication.............................................................................................1273.5.4.1.2 MAC Link Speed........................................................................................................1273.5.4.1.3 SerDes Mode Auto-Negotiation ...................................................................................1283.5.4.1.4 Forcing Link .............................................................................................................1293.5.4.1.5 HW Detection of Non-Auto-Negotiation Partner .............................................................129

3.5.4.2 SGMII Link Configuration ..............................................................................................1293.5.4.2.1 SGMII Auto-Negotiation .............................................................................................1293.5.4.2.2 Forcing Link .............................................................................................................1303.5.4.2.3 MAC Speed Resolution ...............................................................................................130

3.5.4.3 Copper PHY Link Configuration.......................................................................................1303.5.4.3.1 PHY Auto-Negotiation (Speed, Duplex, Flow Control) .....................................................1303.5.4.3.2 MAC Speed Resolution ...............................................................................................131

3.5.4.3.2.1 Forcing MAC Speed .............................................................................................1313.5.4.3.2.2 Using Internal PHY Direct Link-Speed Indication .....................................................131

3.5.4.3.3 MAC Full-/Half- Duplex Resolution ...............................................................................1323.5.4.3.4 Using PHY Registers ..................................................................................................1323.5.4.3.5 Comments Regarding Forcing Link...............................................................................132

3.5.4.4 Loss of Signal/Link Status Indication ..............................................................................1323.5.5 Ethernet Flow Control (FC) ..................................................................................................133

3.5.5.1 MAC Control Frames and Receiving Flow Control Packets ...................................................1333.5.5.1.1 Structure of 802.3X FC Packets...................................................................................1333.5.5.1.2 Operation and Rules ..................................................................................................1343.5.5.1.3 Timing Considerations ...............................................................................................135

3.5.5.2 PAUSE and MAC Control Frames Forwarding ....................................................................1353.5.5.3 Transmission of PAUSE Frames ......................................................................................135

3.5.5.3.1 Operation and Rules ..................................................................................................1363.5.5.3.2 Software Initiated PAUSE Frame Transmission ..............................................................136

3.5.5.4 IPG Control and Pacing .................................................................................................1373.5.5.4.1 Fixed IPG Extension ..................................................................................................1373.5.5.4.2 Limiting Payload Rate ................................................................................................137

3.5.6 Loopback Support ..............................................................................................................1373.5.6.1 General ......................................................................................................................1373.5.6.2 MAC Loopback .............................................................................................................1383.5.6.3 Internal PHY Loopback..................................................................................................138

3.5.6.3.1 Setting the 82576 to PHY loopback Mode .....................................................................1383.5.6.4 SerDes Loopback .........................................................................................................139

3.5.6.4.1 Setting SerDes loopback Mode....................................................................................1393.5.6.5 External PHY Loopback .................................................................................................139



3.5.6.5.1 Setting the 82576 to External PHY loopback Mode .........................................................1393.5.7 Integrated Copper PHY Functionality .................................................................................... 140

3.5.7.1 PHY Initialization Functionality .......................................................................................1403.5.7.1.1 Auto MDIO Register Initialization.................................................................................1403.5.7.1.2 General Register Initialization .....................................................................................1403.5.7.1.3 Mirror Bit Initialization ...............................................................................................141

3.5.7.2 Determining Link State .................................................................................................1413.5.7.2.1 False Link ................................................................................................................1423.5.7.2.2 Forced Operation ......................................................................................................1433.5.7.2.3 Auto Negotiation .......................................................................................................1433.5.7.2.4 Parallel Detection ......................................................................................................1433.5.7.2.5 Auto Cross-Over .......................................................................................................1443.5.7.2.6 10/100 MB/s Mismatch Resolution...............................................................................1443.5.7.2.7 Link Criteria .............................................................................................................145

3.5.7.2.7.1 1000BASE-T ......................................................................................................1453.5.7.2.7.2 100BASE-TX ......................................................................................................1453.5.7.2.7.3 10BASE-T..........................................................................................................145

3.5.7.3 Link Enhancements ......................................................................................................1453.5.7.3.1 SmartSpeed .............................................................................................................146

3.5.7.3.1.1 Using SmartSpeed ..............................................................................................1463.5.7.4 Flow Control ................................................................................................................1463.5.7.5 Management Data Interface ..........................................................................................1473.5.7.6 Low Power Operation and Power Management .................................................................147

3.5.7.6.1 Power Down via the PHY Register................................................................................1473.5.7.6.2 Power Management State...........................................................................................1473.5.7.6.3 AN1000_dis .............................................................................................................1473.5.7.6.4 Low Power Link Up - Link Speed Control.......................................................................148

3.5.7.6.4.1 D0a State ..........................................................................................................1493.5.7.6.4.2 Non-D0a State ...................................................................................................149

3.5.7.6.5 Smart Power-Down (SPD) ..........................................................................................1493.5.7.6.5.1 Back-to-Back Smart Power-Down .........................................................................150

3.5.7.6.6 Link Energy Detect....................................................................................................1503.5.7.6.7 PHY Power-Down State ..............................................................................................150

3.5.7.7 Advanced Diagnostics ...................................................................................................1513.5.7.7.1 TDR - Time Domain Reflectometry...............................................................................1513.5.7.7.2 Channel Frequency Response .....................................................................................151

3.5.7.8 1000 Mb/s Operation....................................................................................................1513.5.7.8.1 Introduction .............................................................................................................1513.5.7.8.2 Transmit Functions....................................................................................................152

3.5.7.8.2.1 Scrambler..........................................................................................................1523.5.7.8.2.2 Transmit FIFO ....................................................................................................1533.5.7.8.2.3 Transmit Phase-Locked Loop PLL ..........................................................................1533.5.7.8.2.4 Trellis Encoder ...................................................................................................1533.5.7.8.2.5 4DPAM5 Encoder ................................................................................................1533.5.7.8.2.6 Spectral Shaper..................................................................................................1533.5.7.8.2.7 Low-Pass Filter ...................................................................................................1543.5.7.8.2.8 Line Driver.........................................................................................................154

3.5.7.8.3 Receive Functions .....................................................................................................1543.5.7.8.3.1 Hybrid...............................................................................................................1553.5.7.8.3.2 Automatic Gain Control (AGC) ..............................................................................1553.5.7.8.3.3 Timing Recovery.................................................................................................1553.5.7.8.3.4 Analog-to-Digital Converter (ADC) ........................................................................1553.5.7.8.3.5 Digital Signal Processor (DSP) ..............................................................................1553.5.7.8.3.6 De scrambler .....................................................................................................1553.5.7.8.3.7 Viterbi Decoder/Decision Feedback Equalizer (DFE) .................................................1553.5.7.8.3.8 4DPAM5 Decoder ................................................................................................1563.5.7.8.3.9 100 Mb/s Operation ............................................................................................1563.5.7.8.3.10 10 Mb/s Operation ..............................................................................................1563.5.7.8.3.11 Link Test ...........................................................................................................1563.5.7.8.3.12 10Base-T Link Failure Criteria and Override............................................................1563.5.7.8.3.13 Jabber...............................................................................................................156



3.5.7.8.3.14 Polarity Correction ..............................................................................................1563.5.7.8.3.15 Dribble Bits........................................................................................................1573.5.7.8.3.16 PHY Address ......................................................................................................157

3.5.8 Media Auto Sense...............................................................................................................1573.5.8.1 Auto Sense Setup ........................................................................................................157

3.5.8.1.1 SerDes/SGMII Detect Mode (PHY is active)...................................................................1573.5.8.1.2 PHY Detect Mode (SerDes/SGMII is active)...................................................................158

3.5.8.2 Switching Between Media..............................................................................................1583.5.8.2.1 Transition to SerDes/SGMII Mode................................................................................1583.5.8.2.2 Transition to Internal PHY Mode ..................................................................................159

4.0 Initialization ............................................................................................................................1614.1 Power Up ............................................................................................................................... 161

4.1.1 Power-Up Sequence............................................................................................................1614.1.2 Power-Up Timing Diagram...................................................................................................162

4.1.2.1 Timing Requirements....................................................................................................1634.1.2.2 Timing Guarantees.......................................................................................................163

4.2 Reset Operation ...................................................................................................................... 1634.2.1 Reset Sources....................................................................................................................163

4.2.1.1 Internal_Power_On_Reset.............................................................................................1644.2.1.2 PE_RST_N...................................................................................................................1644.2.1.3 In-Band PCIe Reset ......................................................................................................1644.2.1.4 D3hot to D0 Transition .................................................................................................1644.2.1.5 Function Level Reset (FLR) ............................................................................................164

4.2.1.5.1 PF (Physical Function) FLR or FLR in non-IOV Mode .......................................................1644.2.1.5.2 VF (Virtual Function) FLR (Function Level Reset) ...........................................................1644.2.1.5.3 IOV (IO Virtualization) Disable ....................................................................................164

4.2.1.6 Software Reset ............................................................................................................1654.2.1.6.1 Full Software Reset ...................................................................................................1654.2.1.6.2 Physical Function (PF) Software Reset..........................................................................1654.2.1.6.3 VF Software Reset.....................................................................................................165

4.2.1.7 Force TCO...................................................................................................................1664.2.1.8 Firmware Reset ...........................................................................................................1664.2.1.9 EEPROM Reset.............................................................................................................1664.2.1.10 PHY Reset ...................................................................................................................166

4.2.2 Reset Effects .....................................................................................................................1674.2.3 PHY Behavior During a Manageability Session ........................................................................173

4.3 Function Disable...................................................................................................................... 1744.3.1 General.............................................................................................................................1744.3.2 Overview ..........................................................................................................................1744.3.3 Control Options..................................................................................................................176

4.3.3.1 PCI functions Disable Options ........................................................................................1764.3.4 Event Flow for Enable/Disable Functions................................................................................176

4.3.4.1 Multi-Function Advertisement ........................................................................................1774.3.4.2 Legacy Interrupts Utilization..........................................................................................1774.3.4.3 Power Reporting ..........................................................................................................177

4.4 Device Disable ........................................................................................................................ 1774.4.1 BIOS Handling of Device Disable ..........................................................................................178

4.5 Software Initialization and Diagnostics ...................................................................................... 1784.5.1 Introduction ......................................................................................................................1784.5.2 Power Up State ..................................................................................................................1784.5.3 Initialization Sequence ........................................................................................................1794.5.4 Interrupts During Initialization .............................................................................................1794.5.5 Global Reset and General Configuration.................................................................................1794.5.6 Flow Control Setup .............................................................................................................1804.5.7 Link Setup Mechanisms and Control/Status Bit Summary.........................................................180

4.5.7.1 PHY Initialization..........................................................................................................1804.5.7.2 MAC/PHY Link Setup (CTRL_EXT.LINK_MODE = 00)..........................................................180

4.5.7.2.1 MAC Settings Automatically Based on Duplex and Speed Resolved by PHY (CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b,) ..........................................180



4.5.7.2.2 MAC Duplex and Speed Settings Forced by Software Based onResolution of PHY (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b)..........................................180

4.5.7.2.3 MAC/PHY Duplex and Speed Settings Both Forced by Software(Fully-Forced Link Setup) (CTRL.FRCDPLX = 1b, CTRL.FRCSPD =1b, CTRL.SLU = 1b)...................................................................................................181

4.5.7.3 MAC/SERDES Link Setup (CTRL_EXT.LINK_MODE = 11b)......................................................................................181

4.5.7.3.1 Hardware Auto-Negotiation Enabled (PCS_LCTL. AN ENABLE = 1b;CTRL.FRCSPD = 0b; CTRL.FRCDPLX = 0)......................................................................181

4.5.7.3.2 Auto-Negotiation Skipped (PCS_LCTL. AN ENABLE = 0b;CTRL.FRCSPD = 1b; CTRL.FRCDPLX = 1)......................................................................182

4.5.7.4 MAC/SGMII Link Setup (CTRL_EXT.LINK_MODE = 10b).....................................................1824.5.7.4.1 Hardware Auto-Negotiation Enabled (PCS_LCTL. AN ENABLE = 1b,

CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b) ....................................................................1824.5.8 Initialization of Statistics .................................................................................................... 1834.5.9 Receive Initialization.......................................................................................................... 183

4.5.9.1 Initialize the Receive Control Register .............................................................................1844.5.9.2 Dynamic Enabling and Disabling of Receive Queues ..........................................................184

4.5.10 Transmit Initialization ........................................................................................................ 1844.5.10.1 Dynamic Queue Enabling and Disabling...........................................................................185

4.5.11 Virtualization Initialization Flow ........................................................................................... 1854.5.11.1 Next Generation VMDq Mode .........................................................................................185

4.5.11.1.1 Global Filtering and Offload Capabilities........................................................................1854.5.11.1.2 Mirroring Rules. ........................................................................................................1864.5.11.1.3 Per Pool Settings.......................................................................................................1864.5.11.1.4 Security Features......................................................................................................187

4.5.11.1.4.1 Anti spoofing......................................................................................................1874.5.11.1.4.2 Storm control.....................................................................................................187

4.5.11.1.5 Allocation of Tx Bandwidth to VMs ...............................................................................1874.5.11.1.5.1 Configuring Tx Bandwidth to VMs..........................................................................1874.5.11.1.5.2 Link Speed Change Procedure ..............................................................................188

4.5.11.2 IOV Initialization ..........................................................................................................1884.5.11.2.1 PF Driver Initialization ...............................................................................................188

4.5.11.2.1.1 VF Specific Reset Coordination..............................................................................1894.5.11.2.2 VF Driver Initialization ...............................................................................................1894.5.11.2.3 Full Reset Coordination ..............................................................................................1894.5.11.2.4 IOV Disable..............................................................................................................1904.5.11.2.5 VFRE/VFTE...............................................................................................................190

4.5.12 Transmit Rate Limiting Configuration ................................................................................... 1904.5.12.1 Link Speed Change Procedure........................................................................................1904.5.12.2 Configuration Flow .......................................................................................................1904.5.12.3 Configuration Rules ......................................................................................................191

4.6 Access to shared resources ....................................................................................................... 1914.6.1 Acquiring ownership over a shared resource.......................................................................... 1914.6.2 Releasing ownership over a shared resource ......................................................................... 193

5.0 Power Management................................................................................................................. 1955.1 General Power State Information ............................................................................................... 195

5.1.1 PCI Device Power States .................................................................................................... 1955.1.2 PCIe Link Power States ...................................................................................................... 1965.1.3 PCIe Link Power States ...................................................................................................... 196

5.2 82576 Power States................................................................................................................. 1965.2.1 D0 Uninitialized State (D0u) ............................................................................................... 197

5.2.1.1 Entry into D0u state .....................................................................................................1975.2.1.2 Exit from D0u state ......................................................................................................197

5.2.2 D0active State .................................................................................................................. 1985.2.2.1 Entry to D0a state........................................................................................................198

5.2.3 D3 State (PCI-PM D3hot) ................................................................................................... 1985.2.3.1 Entry to D3 State.........................................................................................................1985.2.3.2 Exit from D3 State .......................................................................................................1995.2.3.3 Master Disable Via CTRL Register ...................................................................................199



5.2.4 Dr State (D3cold)...............................................................................................................2005.2.4.1 Dr Disable Mode ..........................................................................................................2005.2.4.2 Entry to Dr State .........................................................................................................2015.2.4.3 Auxiliary Power Usage ..................................................................................................201

5.2.5 Link Disconnect..................................................................................................................2015.2.6 Device Power-Down State ...................................................................................................202

5.3 Power Limits by Certain Form Factors......................................................................................... 2025.4 Interconnects Power Management ............................................................................................. 202

5.4.1 PCIe Link Power Management ..............................................................................................2025.4.2 NC-SI Clock Control............................................................................................................2045.4.3 PHY Power-Management .....................................................................................................2045.4.4 SerDes/SGMII Power Management .......................................................................................204

5.5 Timing of Power-State Transitions.............................................................................................. 2055.5.1 Power Up (Off to Dup to D0u to D0a .....................................................................................2055.5.2 Transition from D0a to D3 and Back Without PE_RST_N ..........................................................2065.5.3 Transition From D0a to D3 and Back With PE_RST_N ..............................................................2075.5.4 Transition From D0a to Dr and Back Without Transition to D3...................................................209

5.6 Wake Up ................................................................................................................................ 2105.6.1 Advanced Power Management Wake Up ................................................................................2105.6.2 PCIe Power Management Wake Up .......................................................................................2115.6.3 Wake-Up Packets ...............................................................................................................212

5.6.3.1 Pre-Defined Filters .......................................................................................................2125.6.3.1.1 Directed Exact Packet ................................................................................................2125.6.3.1.2 Directed Multicast Packet ...........................................................................................2125.6.3.1.3 Broadcast ................................................................................................................2125.6.3.1.4 Magic Packet ............................................................................................................2135.6.3.1.5 ARP/IPv4 Request Packet ...........................................................................................2145.6.3.1.6 Directed Ipv4 Packet .................................................................................................2155.6.3.1.7 Directed IPv6 Packet .................................................................................................216

5.6.3.2 Flexible Filters .............................................................................................................2165.6.3.2.1 IPX Diagnostic Responder Request Packet ....................................................................2175.6.3.2.2 Directed IPX Packet...................................................................................................2175.6.3.2.3 IPv6 Neighbor Discovery Filter ....................................................................................218

5.6.3.3 Wake Up Packet Storage...............................................................................................218

6.0 Non-Volatile Memory Map - EEPROM ........................................................................................2196.1 EEPROM General Map............................................................................................................... 2196.2 Hardware Accessed Words ........................................................................................................ 221

6.2.1 Ethernet Address (Words 0x00:02).......................................................................................2216.2.2 Initialization Control Word 1 (Word 0x0A)..............................................................................2226.2.3 Subsystem ID (Word 0x0B) .................................................................................................2236.2.4 Subsystem Vendor ID (Word 0x0C) ......................................................................................2236.2.5 Device ID (Word 0x0D, 0x11) ..............................................................................................2236.2.6 Dummy Device ID (Word 0x1D) ...........................................................................................2236.2.7 Initialization Control Word 2 LAN1 (Word 0x0F)......................................................................2236.2.8 Software Defined Pins Control LAN1 (Word 0x10) ...................................................................2246.2.9 Software Defined Pins Control LAN0 (Word 0x20) ...................................................................2266.2.10 EEPROM Sizing and Protected Fields (Word 0x12) ...................................................................2276.2.11 Reserved (Word 0x13) ........................................................................................................2286.2.12 Initialization Control 3 (Word 0x14, 0x24) .............................................................................2296.2.13 PCIe Completion Timeout Configuration (Word 0x15) ..............................................................2316.2.14 MSI-X Configuration (Word 0x16).........................................................................................2316.2.15 PCIe Init Configuration 1 Word (Word 0x18) ..........................................................................2316.2.16 PCIe Init Configuration 2 Word (Word 0x19) ..........................................................................2326.2.17 PCIe Init Configuration 3 Word (Word 0x1A) ..........................................................................2326.2.18 PCIe Control (Word 0x1B) ...................................................................................................2336.2.19 LED 1,3 Configuration Defaults (Word 0x1C, 0x2A) .................................................................2346.2.20 Device Rev ID (Word 0x1E) .................................................................................................2366.2.21 LED 0,2 Configuration Defaults (Word 0x1F, 0x2B) .................................................................2366.2.22 Functions Control (Word 0x21).............................................................................................2386.2.23 LAN Power Consumption (Word 0x22)...................................................................................239



6.2.24 I/O Virtualization (IOV) Control (Word 0x25)......................................................................... 2396.2.25 IOV Device ID (Word 0x26) ................................................................................................ 2406.2.26 End of Read-Only (RO) Area (Word 0x2C)............................................................................. 2406.2.27 Start of RO Area (Word 0x2D)............................................................................................. 2406.2.28 Watchdog Configuration (Word 0x2E)................................................................................... 2406.2.29 VPD Pointer (Word 0x2F).................................................................................................... 2406.2.30 NC-SI Arbitration Enable (Word 0x40).................................................................................. 241

6.3 Analog Blocks Configuration Structures....................................................................................... 2416.3.1 Analog Configuration Pointers Start Address (Offset 0x17) ...................................................... 2416.3.2 PCIe Initialization Pointer (Offset 0, Relative to Word 0x17 Value)............................................ 2416.3.3 PHY Initialization Pointer (Offset 1, Relative to Word 0x17 Value) ............................................ 2426.3.4 SerDes Initialization Pointer (Offset 2, Relative to Word 0x17 Value) ........................................ 242

6.4 SerDes/PHY/PCIe/PLL/CCM Initialization Structures...................................................................... 2426.4.1 Block Header (Offset 0x0) .................................................................................................. 2426.4.2 CRC8 (Offset 1) ................................................................................................................ 2436.4.3 Next Buffer Pointer (Offset 2 - Optional) ............................................................................... 2436.4.4 Address/Data (Offset 3:Word Count).................................................................................... 243

6.5 Firmware Pointers & Control Words ............................................................................................ 2446.5.1 Loader Patch Pointer (Word 0x51) ....................................................................................... 2446.5.2 No Manageability Patch Pointer (Word 0x52) ......................................................................... 2446.5.3 Manageability Capability/Manageability Enable (Word 0x54).................................................... 2456.5.4 PT Patch Configuration Pointer (Word 0x55).......................................................................... 2456.5.5 PT LAN0 Configuration Pointer (Word 0x56) .......................................................................... 2456.5.6 Sideband Configuration Pointer (Word 0x57)......................................................................... 2466.5.7 Flex TCO Filter Configuration Pointer (Word 0x58) ................................................................. 2466.5.8 PT LAN1 Configuration Pointer (Word 0x59) .......................................................................... 2466.5.9 Management HW Config Control (Word 0x23)........................................................................ 246

6.6 Patch Structure ....................................................................................................................... 2476.6.1 Patch Data Size (Offset 0x0) ............................................................................................... 2476.6.2 Block CRC8 (Offset 0x1)..................................................................................................... 2476.6.3 Patch Entry Point Pointer Low Word (Offset 0x2) ................................................................... 2476.6.4 Patch Entry Point Pointer High Word (Offset 0x3)................................................................... 2476.6.5 Patch Version 1 Word (Offset 0x4)....................................................................................... 2486.6.6 Patch Version 2 Word (Offset 0x5)....................................................................................... 2486.6.7 Patch Version 3 Word (Offset 0x6)....................................................................................... 2486.6.8 Patch Version 4 Word (Offset 0x7)....................................................................................... 2486.6.9 Patch Data Words (Offset 0x8, Block Length) ........................................................................ 248

6.7 PT LAN Configuration Structure ................................................................................................. 2486.7.1 Section Header (Offset 0x0)................................................................................................ 2496.7.2 LAN0 IPv4 Address 0 LSB, MIPAF0 (Offset 0x01) ................................................................... 2496.7.3 LAN0 IPv4 Address 0 MSB, MIPAF0 (Offset 0x02) .................................................................. 2496.7.4 LAN0 IPv4 Address 1; MIPAF1 (Offset 0x03:0x04) ................................................................. 2496.7.5 LAN0 IPv4 Address 2; MIPAF2 (Offset 0x05h:0x06) ............................................................... 2496.7.6 LAN0 IPv4 Address 3; MIPAF3 (Offset 0x07h:0x08) ............................................................... 2496.7.7 LAN0 MAC Address 0 LSB, MMAL0 (Offset 0x09) .................................................................... 2496.7.8 LAN0 MAC Address 0 LSB, MMAL0 (Offset 0x0A).................................................................... 2506.7.9 LAN0 MAC Address 0 MSB, MMAH0 (Offset 0x0B) .......................................