2010-0010. verilog combinational blocks. wakerly chapter_06

7/24/2019 2010-0010. Verilog Combinational Blocks. Wakerly Chapter_06

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CombinationalCombinational

Logic andLogic and

VerilogVerilog


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Programmable ArrayProgrammable ArrayLogicLogic

PALPAL


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Example of PAL. GAL16V8CExample of PAL. GAL16V8C


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Figure 6!6. PAL16L8

PAL"PAL" 1. SOP2. Multi-level

3. Flip-flops

4. 10 Inputs

5. 8 Inputs/output


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Figure 6!8. General CPL# arc$itecture

Complex PL#


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%&' PLA in C()* logic%&' PLA in C()* logic


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A+# plane of EEPL# u"ing floatinggate ()*

tran"i"tor"

EEPL#"EEPL#"Floating gate

on-floating gate


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#ecoder"#ecoder"


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General *tructure of aGeneral *tructure of a

#ecoder circuit#ecoder circuit


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Example 1,Example 1,-rut$ table for a !-rut$ table for a !

to% binary decoder.to% binary decoder.

Example of a decoder circuitExample of a decoder circuit

enableenable


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!to% decoder in"ide!to% decoder in"ide

enableenable


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Verilog for !Verilog for !

to% decoderto% decoder*tructural type

of de"cription in

Verilog


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Example !,Example !,Po"ition encoding for a 'Po"ition encoding for a '

bit mec$anical encoding di"bit mec$anical encoding di"


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Example ! continued, /"ing a 'to8

decoder to decode a Gray code.


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Example ',Example ',

0%x1'8 'to80%x1'8 'to8

decoderdecoder


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Example ',Example ',0%x1'8 'to80%x1'8 'to8

decoderdecoder


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Example ' cont, 0%1'8 'to8

decoder


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VerilogVerilog

code forcode for

'to8'to8decoderdecoder

12..0


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Verilog for 'to8 decoderVerilog for 'to8 decoder

A3!4A3!4A314A314

A354A354

7L3547L354

7L3147L314

7L3!47L3!4

7L3'47L3'4

7L3%47L3%4

7L3247L324

7L3047L304


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0%1'80%1'8

#ecoder,#ecoder,Actie leelActie leel

$andling$andling


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0%x1'8 lie decoder 9it$

Actie leel $andling


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Actie $ig$ 'to8 decoder


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:e$aioral Verilog for 'to8 decoder:e$aioral Verilog for 'to8 decoder

E l ' t 0% 1'8 ' t 8 d d


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Example ' cont,0%x1'8 'to8 decoder

!efault signal

na"es

E l ' t * b l f 0% 1'8


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Example ' cont,*ymbol" for 0%x1'8

;ncorrect;ncorrect

becau"ebecau"e

of doubleof doublenegation"negation"

E l ' tE

l ' t 2 t '! d d f 0%1'8 $i2 t '! d d f 0%1'8 $i


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Example ' cont,Example ' cont,2to'! decoder from 0%1'8 c$ip"2to'! decoder from 0%1'8 c$ip"

#lo$al ena$le

goes to inputs

#1 an% #2&

'(ip sele)t

goes to input

#2*

E l ' tE

l ' t % t 16 d d i% t 16 d d i


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Example ' cont,Example ' cont, %to16 decoder u"ing%to16 decoder u"ing

0%1'80%1'8

3

E l ' tE

l ' t 0% 1'8 d d i GAL0% 1'8 d d i GAL


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Example ' cont,Example ' cont,0%x1'8 decoder u"ing GAL0%x1'8 decoder u"ing GAL

0%x1'8 decoder can be0%x1'8 decoder can be

built in "ingle GAL 16V8built in "ingle GAL 16V8

c$ipc$ip

Fi 6 %1 0% 1'8 li d d


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Figure 6%1. 0%x1'8lie decoder

E lE

l C i d d dC t i d d d


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ExampleExample, Cu"tomi


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Cu"tomi


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*een *egment*een *egment

#i"play and#i"play and

#ecoder#ecoder

* *


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*een *egment #i"play

* * # d


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*een *egment #ecoder


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Encoder"Encoder"+e al,ea% use%+e al,ea% use%en)o%e,s to %esignen)o%e,s to %esign

)ont,ol logi) fo, %ata)ont,ol logi) fo, %ata

pat( $lo)spat( $lo)s


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Encoder"Encoder"

!!nn re=ue"t"re=ue"t"


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PriorityPriorityEncoder"Encoder"


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Encoder"Encoder"

AnyAny"ub"et if"ub"et if

!!nn

re=ue"t"re=ue"t"

+umber n of+umber n of

prioriti


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Encoder"Encoder"

8 i t8 i t


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8input8input

PriorityPriorityEncoderEncoder

ena$le

12 i t P i it E d i PL#12 input Priority Encoder in PL#


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12input Priority Encoder in PL#12input Priority Encoder in PL#

outputsoutputsinputsinputs

Priority Encoder $andle '! re=ue"t"


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Priority Encoder > $andle '! re=ue"t"

8 i t P i it E d


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8input Priority Encoder


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-$ree "tate-$ree "tate

:uffer":uffer"

V i t$ t t b ff


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Variou" t$ree"tate buffer"

/"e of t$ree "tate buffer"/"e of t$ree "tate buffer"


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Eig$t "ource" "$aring a t$ree"tate party line

/"e of t$ree"tate buffer"/"e of t$ree"tate buffer"

-iming diagram for t$e t$ree"tate party line


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-iming diagram for t$e t$ree "tate party line

0%x2%10%x2%1 )ctal t$ree "tate buffer


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0%x2%10%x2%1 )ctal t$ree"tate buffer


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-$ree*tate buffer"-$ree*tate buffer"

ininmicroproce""or"microproce""or"

0% 2%10% 2%1


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0%x2%10%x2%1 a" a microproce""ora" a microproce""orinput port.input port.

Verilog module for a 0%x2%50%x2%5lie 8bit t$ree"tate drier


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g

0%x!%2 octal t$ree"tate tran"ceier0%x!%2 octal t$ree"tate tran"ceier


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0%x!%2 octal t$ree"tate tran"ceier0%x!%2 octal t$ree"tate tran"ceier

Verilog module for a 0%x!%20%x!%2lie 8bit tran"ceier


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g

:idirectional bu"e" and tran"ceier operation


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:idirectional bu"e" and tran"ceier operation

:u" "election code" for a four:u" "election code" for a four


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:u" "election code" for a four:u" "election code" for a four

9ay bu" tran"ceier9ay bu" tran"ceier

PL# input" and output" for a


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PL# input" and output" for a

four9ay? !bit bu" tran"ceier

Verilog module for a four9ay


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Verilog module for a four9ay?

!bit bu" tran"ceier


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(ultiplexer"(ultiplexer"

( ltiple er "tr ct re(ultiplexer "tructure


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(ultiplexer "tructure(ultiplexer "tructure

0%x1210%x121 8input 1bit mux8input 1bit mux


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0%x1210%x121 8input? 1bit mux8 input? 1 bit mux

0%x121 8input? 1bit mux


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0%x121 8 input? 1 bit mux

Combining 0%x121"


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g

to mae a '!to1

multiplexer

!e)o%ing an%!e)o%ing an%

ena$lingena$ling

0%x1200%x120 ! input % bit mux! input % bit mux


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0%x1200%x120!input %bit mux!input %bit mux

GAL16V8 u"ed a" a


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GAL16V8 u"ed a" a

0%x1200%x120 multiplexer

2 inputs ea)( 4

$its

:uffer" to $andle:uffer" to $andle


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:uffer" to $andle:uffer" to $andle

large fanoutlarge fanout

A mux driing a bu" and a demux receiing


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t$e bu"


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#ecoder" a"#ecoder" a"

demultiplexer"demultiplexer"

'to8 binary decoder a" a'to8 binary decoder a" a


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'to8 binary decoder a" a' to 8 binary decoder a" a

demultiplexerdemultiplexer


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GAL" a"GAL" a"

multiplexer"multiplexer"

Function table for a


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Function table for a

*PEC;AL;@E#*PEC;AL;@E# %input? 18bit

mux.

:e$aioral Verilog for a


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:e$aioral Verilog for a

"peciali


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g p

:e$aioral:e$aioral Verilog for a %Verilog for a %


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:e$aioral:e$aioralVerilog for a %Verilog for a %

input? 8bit mux.input? 8bit mux.

2010-0010. verilog combinational blocks. wakerly chapter_06

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