200701

SSCSSSCSSSCSSSCSIEEE SOLID-STATE CIRCUITS SOCIETY NEWS

The Impact of Dennard'sScaling Theory

Winter 2007 Vol. 12, No. 1 www.ieee.org/sscs-news

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We appre-ciate allof your

feedback on ourfirst issue in Septem-ber, 2006 on “TheTechnical Impact of

Moore's Law.” With the Winter, 2007issue, we are continuing our newpolicy of mailing a hard copy of theSSCS News to all 11,500 members.This issue is the first of four that SSCSplans to publish annually (one eachin Winter, Spring, Summer, and Fall).

The goal of every issue is to be aself-contained resource on a select-

ed topic, with background articles(that is, the ‘original sources’) andnew articles by experts whodescribe the current state of affairsin technology and the impact of theoriginal papers and/or patents.

The theme of the Winter 2007issue is “The Impact of Dennard'sScaling Theory.”

This issue contains one ResearchHighlights article: “Analog IC Designat the University of Twente,” byBram Nauta, Head of the IC DesignGroup at the University of Twente,The Netherlands. The issue alsocontains seven short feature articles

that address the theme:(1) “A 30 Year Retrospective on

Dennard's MOSFET ScalingPaper,” by Mark Bohr of IntelCorporation;

(2) “Device Scaling: The Treadmillthat Fueled Three Decades ofSemiconductor Industry Growth,”by Pallab Chatterjee of i2 Tech-nologies;

(3) “Recollections on MOSFETScaling,” by Dale Critchlow,the University of Vermont;

(4) “The Business of Scaling,” byRakesh Kumar, TCX, Inc. Tech-nology Connexions;

(5) “A Perspective on the Theoryof MOSFET Scaling and itsImpact,” by Tak Ning, IBM;

(6) “Impact of Scaling and theenvironment in which the Scal-ing developed

at that time," by Yoshio Nishi, Stan-ford University;

(7) "It's All About Scale," by HansStork, TI.

Three original papers by Den-nard, from 1972 (IEDM Conference),1973 (IEDM Conference), and 1974(IEEE Journal of Solid-State Cir-cuits), are also reprinted in thisissue.

Thank you for taking the time toread the SSCS News. We appreciateyour comments and feedback! Pleasesend comments to [email protected].

2 IEEE SSCS NEWSLETTER Winter 2007

President:Richard C. JaegerAlabama Microelectronics CenterAuburn University, [email protected]: +1 334 844-1888

Vice President:Willy SansenK. U. LeuvenLeuven, Belgium

Secretary:David A. JohnsUniversity of TorontoToronto, Ontario, Canada

Treasurer:Rakesh KumarTechnology Connexions Poway, CA

Past President:Stephen H. LewisUniversity of CaliforniaDavis, CA

Other Representatives:Representative to Sensors Council

Darrin YoungRepresentative from CAS to SSCS

Domine LeenaertsRepresentative to CAS from SSCS

Un-Ku Moon

Newsletter Editor:Lewis TermanIBM T. J. Watson Research Center [email protected]: +1 914 945-4160

Newsletter Coeditor:Mary Y. LanzerottiIBM T.J. Watson Research [email protected]: +1 914 945 1358

Elected AdCom Members at LargeTerms to 31 Dec. 07:

Bill BidermannDavid JohnsTerri FiezTakayasu SakuraiMehmet Soyuer

Terms to 31 Dec. 08:Wanda K. GassAli HajimiriPaul J. HurstAkira MatsuzawaIan Young

Terms to 31 Dec. 09:John J. CorcoranKevin KornegayHae-Seung (Harry) LeeThomas H. LeeJan Van der Spiegel

Chairs of Standing Committees:Awards David HodgesChapters Jan Van der SpiegelEducation CK Ken YangMeetings Anantha ChandrakasanMembership Bruce HechtNominations Stephen H. LewisPublications Bernhard Boser

For detailed contact information, see the Soci-ety e-News: www.ieee.org/portal/site/sscs

For questions regarding Society business, contact the SSCS Executive Office.

Contributions for the Spring 2007 issue of the Newsletter must be received by 8 February 2007 at the SSCS Executive Office. A complete media kit for advertisersis available at www.spectrum.ieee.org/mc_print. Scroll down to find SSCS

Anne O’Neill, Executive Director IEEE SSCS445 Hoes LanePiscataway, NJ 08854Tel: +1 732 981 3400Fax: +1 732 981 3401Email: [email protected]

IEEE Solid-State Circuits Society AdCom

Editor’s Column

Katherine Olstein, SSCS Administrator IEEE SSCS445 Hoes Lane, Piscataway, NJ 08854 Tel: +1 732 981 3410 Fax: +1 732 981 3401Email: [email protected]

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Winter 2007 IEEE SSCS NEWSLETTER 3

©Copyright IBM Corporation 2006.

All rights reserved.Reproduced by

permission of IBMCorporation.

Winter 2007 Volume 12, Number 1

Editor’s Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

President’s Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

20

51

56

RESEARCH HIGHLIGHTSAnalog IC Design at the University of Twente . . . . . . . . . . . . . . . . . .5

TECHNICAL LITERATUREA 30 Year Retrospective on Dennard’s MOSFET Scaling Paper . . .11Device Scaling: The Treadmill that Fueled Three Decades of Semi-conductor Industry Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Recollections on MOSFET Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . .19The Business of Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22A Perspective on the Theory of MOSFET Scaling and its Impact . .27The Impact of Scaling and the Scaling Development Environment 31It’s All About Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Design of Micron MOS Switching Devices . . . . . . . . . . . . . . . . . . . .35Ion Implanted MOSFET’s with Very Short Channel Lengths . . . . . . .36Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions 38

PEOPLEAn Interview with James Meindl - 2006 IEEE Medal of Honor Recipient 51Hugo De Man Awarded for Leadership in Integrated Circuit Design . .53Yannis P. Tsividis to Receive IEEE Kirchhoff Award . . . . . . . . . . . . . . . . . . .56IEEE Educational Innovation Award to Terri Fiez . . . . . . . . . . . . . . . . . . . . .5816 New Speakers Diversify SSCS Distinguished Lecturer Program . . . . . .61New Senior Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67Tools: How to Write Readable Reports and Winning Proposals . . . . . . . .67

CHAPTER NEWSSSCS Awards $35,000 in Chapter Subsidies . . . . . . . . . . . . . . . . . . . . . . . .69Far East Chapters Meet in Hangzhou, China . . . . . . . . . . . . . . . . . . . . . .70V. Oklobdzija Offers IEEE DL Talks in Western Australia . . . . . . . . . . . .71Denver Hosts Technical Seminars on Cutting-Edge CMOS Technology .72

CONFERENCESSecond A-SSCC Considers Challenges for the e-Life . . . . . . . . . . .74Solid-State Circuits Conference Will Focus on Nano-Era Synergy . .76Invitation from the ISSCC 2007 Chair . . . . . . . . . . . . . . . . . . . . . . . .75AACD Conference Will Convene on 27-29 March 2006 . . . . . . . . .78

NEWSSSCS AdCom Election for 2007-2009 Term . . . . . . . . . . . . . . . . . . . . . . .80IEEE Design Council Newsletter Completes Inaugural Year . . . . . . . . . .80IEEE Teaching Awards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Call for Nominations: SSCS Predoctoral Fellowships . . . . . . . . . . . . . . . .82

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Message from the President

In 2007, look for an unadvertised bonuswith your SSCS membership: A freesubscription to the brand new quarterlyNanotechnology Magazine. We believethat circuit experts need to be in touchwith this rapidly progressing technolo-gy. Some day it will be a fruitful area

for circuits development, and opportunities to con-tribute will arise.

The minimal subscription cost to the Society for thelaunch year of the new magazine prompted the AdComto join the Nanotechnology Council. We hope theCouncil’s magazine effort will be of comparable interestto its Transactions on Nanotechnology, which is justbeginning its sixth year and has among the highest ratesof citation as measured by the Thompson ISI. I wouldlike to receive feedback from you on how useful a toolthe new magazine is. Look for the first issue in thespring of 2007.

2007 is the Society’s 10th anniversary, havingevolved from the Solid-State Circuits Council that orig-inated in 1970. We’ve updated the SSCS logo for thisyear to draw attention to our progress. Since 1997, theJournal of Solid-State Circuits has increased coverage oftechnical articles by 40%, and the SSCS Newsletter by 21/2 times. The JSSC continues to be the most read inIEEE Xplore and the most cited in patents. Your SSCSmembership provides online access not only to theJournal but also to the digests of our five major solid-state circuits conferences and most of their historicrecord. Local chapters have grown from 2 to 59, with

the recent addition of Tainan (Taiwan) and SouthBrazil. Celebrate our anniversary by browsing yourtechnical articles online.

I’ve been active in the last quarter attending many ofthe conferences that SSCS cosponsors to sample theirquality, focus, and differences, as well as to increase theSociety’s visibility and support for these important gath-erings of technical experts. ESSCIRC in Montreux,Switzerland last fall was fully overlapped with the ESS-DERC device conference. One was able to move freelybetween the co-located meetings. The wide variety ofplenary topics covered by the two meetings was of par-ticular interest. Welcoming the Asian-Solid-State CircuitsConference in Hangzhou, China two months later, I wasable to talk with circuit experts from around the world,and by the time this issue reaches you, I will have cel-ebrated the opening of the 20th International Confer-ence on VLSI Design in Bangalore.

Thanks to all of our members who voted in our fallelection. Welcome to our new additions to AdCom,Kevin Kornegay from Georgia Tech and Harry Lee fromMIT. And welcome back to returning AdCom membersJohn Corcoran from Agilent Laboratories, Tom Lee fromStanford, and Jan Van der Spiegel from the University ofPennsylvania. The Society is beginning a review of itspriorities for 2007 and beyond. As Society members,please make your interests known to your AdCom rep-resentatives. Start a conversation and help the Societypoint to the future that you feel is coming.

Richard C. Jaeger

In the article entitled “Overview ofCMOS Technology Development inthe MIRAI Project,” by ToshiakiMasuhara and Masataka Hirose inthe September 2006 issue, the lastsentence in the Section entitled“New Circuits and System Technolo-gy - Post-fabrication AdaptiveAdjustment” contains an incorrectexpression, which is corrected as inthe underlined expression in the fol-lowing sentence:

“As shown in Fig. 3, the devel-oped tool successfully extracted the34 model parameters in 23 hourswith a PC and resulted in a meanRMS error of 1.83% for benchmarkMOSFETs.”

In the Section, “New Gate StackTechnology with High-k Materials”,

the caption for Figure 4 should read: Fig. 4 Gate leakage current in

MIRAI HfAlON formed by Layer-by-Layer Deposition and Annealing(LL-D&A) 4).

(a) Comparison of gate leakage cur-rent in MOSFETs with HfAlONgate insulator and HfSiON 5).

(b) Cross sectional TEM micrographof HfAlON/SiO2/Si gate stackformed by Layer-by-Layer Depo-sition and Annealing.

The following corrections pertainto the reprint of “Lithography andthe Future of Moore’s Law” (Moore,1995) in the September 2006 issue:

I have reproduced photomicro-graphs of the first planar transistor

and the first commercially-availableintegrated circuit in Figs 3 & 4. I amparticularly fond of the transistor,since it is one of the very few prod-ucts that I designed myself thatactually went into production.

Fig. 3. Photomicrograph of the firstcommercial planar transistor.

Corrections

continued on page 10

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RESEARCH HIGHLIGHTS

IntroductionThis article describes some recent research resultsfrom the IC Design group of the University of Twente,located in Enschede, The Netherlands.

Our research focuses on analog CMOS circuitdesign with emphasis on high frequency and broad-band circuits. With the trend of system integration inmind, we try to develop new circuit techniques thatenable the next steps in system integration innanometer CMOS technology. Our research fundingcomes from industry, as well as from governmentalorganizations. We aim to find fundamental solutionsfor practical problems of integrated circuits realized inindustrial Silicon technologies.

CMOS IC technology is dictated by optimal cost andperformance of digital circuits and is certainly notoptimized for nice analog behavior. As analog design-ers, we do not have the illusion of being able tochange CMOS technology, so we have to “live with it”and solve the problems by design. In this article sev-eral examples will be shown where problematic ana-log behavior, such as noise and distortion, can be tack-led with new circuit design techniques. These circuittechniques are developed in such a way that they dobenefit from modern technology and thus enable fur-ther integration. This way we can improve variousanalog building blocks for wireless, wire-line and opti-cal communication. Below some examples are given.

Thermal Noise Cancelling Noise is an important issue; in communication circuitsthe sensitivity of the receiver is limited by the noiselevel of the circuits. Especially, the noise of the firstamplifier in the receiving chain is of high importance,since after that amplifier the signal is stronger and theallowable noise levels are higher. For narrowbandreceivers the added noise of the amplifier can bereduced relatively easily. This is done by using reso-nant structures, built with - for example - integratedspiral inductors and capacitors which provide voltagegain of the narrowband signals and therefore needingless gain from “noisy” transistors. For wideband sys-tems, e.g. for TV tuners, UWB (Ultra Wide Band)communication and future software defined radio,several octaves of bandwidth are needed and simpleresonant structures cannot be used. For these appli-cations, low noise gain stages using noisy transistorshave to be used, which is quite a challenge. Apartfrom the gain and noise demands, additionaldemands, such as input impedance matching andgood linearity, need to be satisfied.

Figure 1a shows a wide band first amplifier stage,denoted as a common-source feedback amplifier.

The input impedance is 1/gm of M1, and must beequal to the source impedance Rs, usually 50 Ohms.With this in mind the gm of M1 is fixed by designresulting in poor noise behavior of the amplifier: The"noise figure" is always larger than 3dB. In order toreduce the noise one would like to increase the gm ofM1 (preferably gm>>1/Rs for minimal noise figure) butthen the input impedance does not match anymore.Conventionally, additional feedback techniques areused to break this paradox, but at the cost of stabilityand bandwidth issues.

PhD Student Federico Bruccoleri realized, howev-er, that generated noise can be cancelled by propercircuit design. If we take a look at Figure 1b, we cansee how the noise current of M1 flows in the circuit;this is indicated by the red arrow.

The noise current due to M1 flows in a loop,through Rs. This noise current generates a noise volt-age at nodes X and Y which are of different magni-tude but of the same phase. The signals nodes X andY are in anti-phase due to the inverting nature of thisamplifier. So somehow it should be possible to sepa-rate the signal from the noise!

By adding an additional amplifier “A,” as shown inFigure 2, we can construct an output signal in such away the wanted signals at nodes X and Y are addedand that the noise at nodes X and Y are cancelled [1].This way we can cancel the noise of M1, which holdsfor both thermal and 1/f noise. Of course amplifier“A” will now add additional noise, but this needs notto be a problem. The reason for this is that in contrastto M1, we can choose the gm of the input stage ofamplifier “A” relatively large, and thus make it low-

Analog IC Design at the University of TwenteBram Nauta, IC Design Group, University of Twente, Enschede, The Netherlands,[email protected]

Fig 1a: common source LNA with impedance matching,the signals at nodes X and Y have opposite sign.Fig 1b: The noise of M1 generates in-phase noise voltagesat nodes X and Y.

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noise. So we don't break the laws of physics: we stillhave to burn power (in amplifier “A”) to get a low-noise amplifier, but we have created a degree of free-dom by decoupling the input matching (gm1=1/Rs)and allowing a large gm ( gmA>>1/Rs) in the amplifierA. The noise of Ibias is cancelled as well. A prototypeamplifier has been realized on silicon and it workedwell: the noise figure was well below 3dB, whichproves the concept of noise canceling. Also therobustness to mismatch in the two noise paths is good[1]. Other topologies are also possible offering “balun”functionality [1,2].

Low Frequency noise reduction in MOSFETSLow frequency (LF) transistor noise, also denoted as1/f noise, is of great importance in today's circuitdesign. Especially, baseband circuits suffer from thisnoise phenomenon which can be dominant wellabove 10MHz. Also high-frequency oscillators sufferfrom LF noise, since this noise is up-converted andappears close to the carrier frequency of the oscillatordegrading the close-in phase noise.

A while ago, a MSc student Gian Hoogzaad didcalculations on the phase noise of CMOS inverter-based ring oscillators. These oscillators were freerunning, and we expected a large close-in phasenoise due to the low frequency noise of the MOS-FETs in the oscillator. Measurements, however,showed a much lower, (8dB less), close-in phasenoise than we expected from the LF noise of thosesingle transistors. The student and his supervisorSander Gierkink were very confident of his calcula-tions, and we were thus wondering what caused the8dB lower close-in phase noise.

Finally, we suspected that the large signal switch-ing behavior in the inverters caused the strange effectand we carried out measurements on stand-alonetransistors under normal bias and under “switchedbias”. Figure 3 illustrates these conditions.

One would expect 6 dB less noise from theswitched bias transistors compared to the normal one:3dB reduction due to the 50% duty-cycle of the noiseand another 3dB due to up-conversion of the LF noise.

Measurements however showed 6 + 8 = 14 dB reduc-tion for frequencies lower than the switching frequen-cy, as illustrated with the red curve in Figure 4.

This matched to the 8dB reduction of phase noisein the inverter ring-oscillator. This reduction takesplace for frequencies lower than the switching fre-quency. Later, we discovered that a similar noise phe-nomenon had been observed before in physicists'device experiments[3]; however, we could not find acitation to this paper.

So, in fact, all inverter based ring oscillators bene-fited already from this phenomenon while none ofthe designers apparently realized this. To a largeextent this is because the “switched bias” noise reduc-tion is not modeled in today's simulators. Also, theeffect can be masked by the very large spread whichis normally present in LF noise, especially for smallarea devices.

After a study carried out in the PhD projects byArnoud van der Wel and Jay Kolhatkar, the phenom-ena could be explained by the bias dependency ofthe emission and capture time constants which areresponsible for the trapping and de-trapping of oxide-charge in MOSFETs. This trapping and de-trapping

RESEARCH HIGHLIGHTS

Fig 2: Basic idea of noise cancelling; the noise due to M1is cancelled.

Fig. 3: MOSFET under constant bias (blue) and switchedbias (red)

Fig. 4: Measured LF noise of a MOSFET under constantbias (blue), expected 6 dB reduction under switched bias(red dashed curve) and measured behavior with intrinsicreduced noise (red)

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causes so-called random telegraph signals, whichdetermine the low frequency noise of the transistors.The reduction effect is found to be present in all tech-nologies investigated: from 10μm down to 0.12μm,both N and P MOSFETs and works for switching fre-quencies up to at least 3GHz.

For large-geometry transistors we generally see asignificant reduction, whereas for very small-sizedmodern devices the noise can decrease but alsoincrease. This is due to the very small number oftraps in the transistors (sometimes only one trap)while the phenomenon depends strongly on theenergy distribution of the traps. Details can befound in [4].

Other known techniques to reduce the effect of LFnoise in electronic circuits are chopping and correlat-ed double sampling. The LF noise can also bereduced by increasing gate area of the MOSFETS, atthe cost of area and/or power consumption. Theswitched bias technique offers an orthogonal methodto reduce the intrinsic LF noise in the transistor itself.It is beneficial especially in circuits where switchingalready occurs, such as oscillators and discrete timecircuits.

Distortion Cancelling using Poly-PhaseTechnique In deep submicron technology, distortion becomesan increasing problem. Large signals are requiredfor dynamic range reasons or simply because for agiven radio standard dictates the output power to bedelivered by a power amplifier. The transistors,however, have less voltage gain and exhibit verynon-linear behavior, which makes linear circuitdesign a challenge.

We know that in differential circuit the even har-monics are cancelled if the signals are in anti-phase.With this in mind, MSc student Eisse Mensink investi-gated whether it would be possible to use more than2 paths and multiple phases of the signal (poly-phase)and cancel more than 2 harmonics. The basic idea isshown in Figure 5, where the signal path is split in Nseparate parallel paths.

N=2 equals the well-known differential circuittopology to cancel even harmonics. If phase shiftersare available before and after the nonlinear circuit, thestructure of Fig. 5 can cancel the harmonics up to N-1 [5]. The problem is however that wide-band phaseshifters are very hard to implement with analog cir-cuits. For this reason, we choose to use mixers as sec-ond phase shifters, as shown in Figure 6.

The mixers each have a Local Oscillator (LO) inputwith each a different phase, equally divided over360/N degrees. Since we automatically get up-conver-sion of our input signal with these mixers, we strate-gically changed our plan and decided to build an RF

power up-converter. In this up-converter the firstphase shifters are assumed to be implemented in thedigital baseband, while in the up-conversion mixersall problematic harmonics due to nonlinearities of theN power amplifier stages can be cancelled via thepoly-phase technique in combination with a 1/3 duty-cycle LO-signal [6].

A silicon realization, designed by MSc Student

Rameswor Shrestha, is based on the circuit of Fig. 7with N=18 [6]. The colors in Figure 7 correspond tothe colors of the functional blocks of Figure 6.

Rameswor demonstrated a power up-conversionmixer, which is driven in compression while all har-monics and their sidebands, up to the 17th harmonic,still remain under -40dBc. Without this poly-phasetopology (i.e. for N=1) the harmonics would be belowonly -6dBc, which clearly demonstrates the effective-ness of the technique - 34 dB improvement. The RFfrequency could be varied from DC to 2.5GHz and thefinal accuracy of the technique was limited by timingof the LO phases.

Conventional RF up-converters require expensivepost-filters, dedicated for every RF frequency to filterout the harmonics and sidebands in order to satisfythe radio transmit mask. With this poly-phase up-con-verter the harmonics can be rejected and the filterdemands can be much relaxed. Applications of thispoly-phase up-converter can probably be found inwide band flexible up-converters and software radiotransmitters, where the actual RF frequency is a priori

RESEARCH HIGHLIGHTS

Fig. 5: N path poly-phase circuit can cancel up to the N-1th

harmonic.

Fig 6: Wide band phase shifters can be implemented withmixers, resulting in up-converter behavior.

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not known and is free to be chosen in a givenrange.

Pulse Width Modulation Cable EqualizerFor digital data communication over copper cables,electronic equalizer circuits are used to compensatefor the losses and reflections over the cables. Thanksto these electronic circuits, higher data rates can beachieved over relatively cheap cables. Examples areUSB and LAN.

A well known technique used at the transmitterside is pre/de-emphasis, effectively high-pass filteringthe transmitted signal. This way the low-pass charac-teristic of the cable is compensated for. These trans-mit pre-emphasis filters are generally implementedwith Finite Impulse Response (FIR) filters, most oftenwith just a few symbol spaced taps.

As an alternative to FIR filters Daniel Schinkel andJan-Rutger Schrader proposed Pulse Width Modula-tion (PWM) on a digitally coded signal [7,8]: If a ‘1’-bithas to be transmitted, a 1-0 pattern is transmitted inone bit time and if a ‘0’-bit has to be transmitted a 0-1 pattern is transmitted in one bit time. This is similarto Manchester coding but with adjustable, non-50%duty-cycle. The duty-cycle of the 1-0 and 0-1 patternis chosen in such a way that it compensates for thecable loss. This is illustrated in Figure 8, where theduty-cycle of a 1-0 pattern is varied and the corre-sponding cable responses are plotted.

Thus, by changing the duty-cycle, the transmittedspectrum, in which the lower frequencies are attenu-ated, is tuned for the high-frequency loss of the cable.In a real application an adaptive loop with return-channel communication takes care for this tuning,similar as in a conventional FIR approach. A test chipachieved 5Gb/s over 25m of RG-58U coaxial cable

which has a loss of 33 dB at the Nyquist frequency of2.5GHz [8] . The eye diagram for various duty-cyclesis shown in Figure 9: for this 10m long cable 66% isthe optimum duty-cycle.

The PWM technique can compensate for higherloss compensation (33 dB in contrast to approximate-ly 20dB for 2 tap symbol-spaced FIR) because theresulting spectrum has a better match to the skin-

effect and dielectric loss of the cable. Still only onetuning “knob” is required to fit the transfer function tothe cable. Moreover the technique is insensitive toslew-rate distortion and requires only two discreteamplitudes at the TX output (with a continuouslyadjustable duty-cycle), which makes it suitable formodern CMOS technologies. The technique was alsosuccessfully applied earlier for very long on-chip RClimited interconnects by Daniel Schinkel and EisseMensink [7].

Optical Detectors in Standard CMOSTraditionally, in optical communication extremelyhigh data rates have to be achieved over long dis-tances. Therefore optical communication is thedomain of expensive exotic technologies and the high

RESEARCH HIGHLIGHTS

Fig 7: Basic circuit of Power up-converter. Fig. 8: Transmitting a “1” using PWM pre-emphasis: tun-ing the duty-cycle of the 1-0 pattern can compensate forthe cable response.

Fig 9: 5Gb/s eye patterns of transmitted signals (TX) andreceived signals (RX) for duty-cycle settings of 100% (nor-mal data) , 66% (optimal PWM) and 50% (overcompen-sated PWM) over 10m RG-58CU cable.

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costs associated with it can be shared between manyusers. For optical communication over short distances(meters) or very short distances (optical interconnect),cost issues, however, do play a crucial role. There-fore, we started a project to integrate an optical detec-tor in standard CMOS technology; the optical data sig-nal can now shine directly on a digital CMOS chip.Due to the availability of low-cost high-speed laser at850nm wavelength and the compatibility with bothinexpensive plastic fibers and with photo-generationin silicon, our work mainly uses this 850nm.

An essential part of an optical detector in CMOS isthe integrated photodiode structure, shown in the left-most inset in Figure 10.

Incident photons are absorbed in the silicon at tensof microns deep, much deeper than any junction instandard CMOS. In the absorption process, electronsand holes are generated and most of them slowly dif-fuse to the pn-junctions where the actual detectiontakes place. The slow diffusion causes the -3dB band-width of the photodiode to be in the order of 5 MHz,which causes a serious speed problem. In literatureauthors generally modify the technology, e.g. to allowhigh voltages and very wide depletion layers to boostthe speed of the carriers, however this implies thatnon-standard CMOS has to be used. The maximalspeed reported in standard CMOS so far has been700Mbit/sec.

Ph.D. student Sasa Radovanovic implementedanother solution. Although the -3dB frequency isvery low, the roll-off per decade of frequencyappears to be very low as well; only 3 to 4 dB perdecade, up to in the low GHz region. Therefore, Sasaused an analog equalizer, with opposite frequencycharacteristic after the transimpedance amplifier fol-lowing the diode to get a flat overall response up toa few GHz. One might assume that the productionspread in time constants between the equalizer andthe diode itself might ruin the performance, but

thanks to the low roll off, even +/- 20% spread intime constants hardly affects the time pulses. Theresulting chip achieved 3Gbit/sec in standard 0.18μmCMOS, with a BER of 10-11 at an optical input powerof 25μW [9]. The speed limitation was in the elec-tronic circuit, and is expected to scale with technolo-gy. This result enables high speed optical inputs forstandard CMOS chips.

ConclusionSeveral examples of new design methodologies havebeen illustrated. These methodologies benefit frommodern CMOS technology and may be helpful forfuture system integration. More work can be found atthe URL: http://icd.ewi.utwente.nl

AcknowledgementsThe work described in this article has been carriedout by many students; however, without the supervi-sion or help from Eric Klumperink, Anne JohanAnnema, Ed van Tuijl, Ronan van der Zee, GerardWienk and Henk de Vries, these results would nothave been here. This work has been funded by: STW,FOM and MESA+. Philips and CERN are acknowledgedfor providing silicon access.

References[1] F. Bruccoleri, E.A.M. Klumperink, B. Nauta,

“Wide-Band CMOS Low-Noise Amplifier Exploit-ing Thermal-Noise Canceling”, IEEE Journal ofSolid-State Circuits, Vol. 39, No. 2, pp. 275 -282,February 2004.

[2] S. Chehrazi, A. Mirzaei, R. Bagheri, A. A. Abidi;“A 6.5 GHz wideband CMOS low noise amplifi-er for multi-band use”, 2005 IEEE Custom Inte-grated Circuits Conference18, pp. 801 - 804, Sep-tember 2005.

[3] I. Bloom and Y. Nemirovsky, “1/f noise reduc-tion of metal-oxide semiconductor transistors bycycling from inversion to accumulation”, AppliedPhysics Letters, vol. 58, no. 15, pp. 1664–1666,Apr. 1991.

[4] A.P. van der Wel , E.A.M. Klumperink , J. Kol-hatkar , E. Hoekstra, M. Snoeij , C. Salm, H.Wallinga and B. Nauta “Low Frequency NoisePhenomena in Switched MOSFETs”, IEEE Journalof Solid State Circuits, Vol. 42, No.3, March 2007.

[5] E. Mensink, E.A.M. Klumperink, B.Nauta, “Dis-tortion Cancellation by Polyphase Multipath Cir-cuits,” IEEE TCAS-I, pp. 1785-1794, Sept. 2005.

[6] R. Shrestha, E.A.M. Klumperink, E. Mensink, G.Wienk, B. Nauta, “A Polyphase Multipath Tech-nique for Software Defined Radio Transmitters”,IEEE Journal of Solid State Circuits, Vol. 41,No.12, Dec 2006.

[7] D. Schinkel., E. Mensink, E.A.M. Klumperink,A.J.M. van Tuijl, B. Nauta, “A 3Gb/s/ch Transceiver

RESEARCH HIGHLIGHTS

Fig. 10: Transmitting a “1” using PWM pre-emphasis: tun-ing the duty-cycle of the 1-0 pattern can compensate forthe cable response.

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for 10-mm Uninterrupted RC-Limited Global On-Chip Interconnects”, IEEE Journal of Solid StateCircuits, Vol. 41, No. 1, pp. 297- 306, Jan. 2006.

[8] J.H.R. Schrader, E.A.M. Klumperink, J.L. Vissch-ers, B. Nauta, “Pulse-Width Modulation PreEmphasis applied in a Wireline Transmitter,achieving 33dB Loss Compensation at 5-Gb/s in

0.13-μm CMOS”, IEEE Journal of Solid-State Cir-cuits, Vol. 41, No. 4, pp.990-999, April 2006.

[9] S. Radovanovic, A.J. Annema, B. Nauta, “A 3Gb/s optical detector in standard CMOS for 850nm optical communication” IEEE Journal ofSolid-State Circuits, Volume 40, No.8, Pg:1706 -1717, Aug. 2005.

RESEARCH HIGHLIGHTS

About the AuthorBram Nauta was born in Hengelo,The Netherlands. In 1987 hereceived the M.Sc degree (cumlaude) in electrical engineering fromthe University of Twente, Enschede,The Netherlands. In 1991 hereceived the Ph.D. degree from thesame university on the subject of

analog CMOS filters for very high frequencies.In 1991 he joined the Mixed-Signal Circuits and

Systems Department of Philips Research, Eindhoventhe Netherlands, where he worked on high speed ADconverters and analog key modules. In 1998 hereturned to the University of Twente, as full professorheading the IC Design group, which is part of the

CTIT Research Institute. His current research interestis high-speed analog CMOS circuits. Besides, he isalso part-time consultant in industry and in 2001 heco-founded Chip Design Works.

His Ph.D. thesis was published as a book: AnalogCMOS Filters for Very High Frequencies, (Springer, 1993)and he received the “Shell Study Tour Award” for hisPh.D. Work. From 1997-1999 he served as Associate Edi-tor of IEEE Transactions on Circuits and Systems -II; Ana-log and Digital Signal Processing, and in 1998 he servedas Guest Editor for IEEE Journal of Solid-State Circuits.From 2001 to 2006 he was Associate Editor for IEEEJournal of Solid-State Circuits and he is also member ofthe technical program committees of ISSCC, ESSCIRC,and Symposium on VLSI circuits. He is co-recipient of theISSCC 2002 “Van Vessem Outstanding Paper Award.”

Fig. 4. Photomicrograph of one of thefirst planar integrated circuits pro-duced by Fairchild Semiconductor inthe early 1960’s.

The unusual diameter of 764microns was chosen because wewere working in English units andthat is thirty thousandths of an inch,or 30mils. The minimum feature sizeis the three mil metal line makingthe circular base contact. Metal-to-metal spacing is five mils to allowthe 2.5mil alignment tolerance weneeded.

Interestingly enough at the timethe idea for the planar transistor wasconceived by Jean Hoerni in theearly days of Fairchild Semiconduc-tor, it had to sit untried for a coupleof years, because we did not havethe technology to do four alignedmask layers. In fact, we were devel-oping the technology to do twoaligned oxide-masked diffusionsplus a mesa etching step for transis-tors. The original step and repeatcamera that Bob Noyce designedusing matched 16mm movie cameralenses had only three lenses, so itcould only step a three-mask set.We had to wait until the first mesatransistors were in productionbefore we could go back and figureout how to make a four mask set toactually try the planar idea.

The first integrated circuit on thegraph is one of the first planar inte-grated circuits produced. It includ-ed four transistors and six resistors.

It has always bothered me that thepicture of this important devicethat got preserved was of the uglychip shown in Fig. 4. The circuithad six bonding pads around thecircumference of a circle formounting in an 8-leaded versionof the old TO-5 outline transistorcan. In this case only six of theeight possible connections wererequired. We did not think wecould make eight wire bonds withreasonable yield, so for these firstintegrated circuits we etched around die that let us utilize blobsof conducting epoxy to make con-tact to the package pins. For thedie in the picture, the etchingclearly got away from the etcher.

A prior version of “The Mytholo-gy of Moore’s Law,” by Tom R.Halfhill in the September 2006 issuewas published in MicroprocessorReport of December, 2004.

Corrections continued from page 4

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More than three decades have passed since theteam of Robert Dennard, Fritz Gaensslen,Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous

and Andre LeBlanc from the IBM T. J. Watson ResearchCenter wrote the seminal paper describing MOSFETscaling rules for obtaining simultaneous improvementsin transistor density, switching speed and power dissi-pation [1]. At the time of this paper (1974), commercial-ly available circuits were using MOSFETs with gatelengths of approximately 5 microns, but devices withshorter gate lengths were already being built in labora-tories that were demonstrating the benefits of furtherscaling. The scaling principles described by Dennardand his team were quickly adopted by the semicon-ductor industry as the roadmap for providing systemat-ic and predictable transistor improvements.

Table I is reproduced from Dennard’s paper andsummarizes transistor or circuit parameter changesunder ideal scaling conditions, where κ is the unitlessscaling constant. The tantalizing benefits of MOSFETdevice scaling immediately leap out from this table: astransistors get smaller, they can switch faster and useless power. But of course learning exactly how tomake transistors smaller in a way that could be donepractically in high volume manufacturing would taketime. It would take time to develop lithographic tech-niques to pattern smaller feature sizes, to grow thin-ner gate oxides, and to reduce defect levels at theseincreasingly challenging dimensions. But this papergave our industry a roadmap, a method for setting tar-gets and expectations for coming generations ofprocess technology. This paper gave us the more spe-cific transistor scaling formula needed to continueMoore’s Law, which was first articulated in a paper by

Gordon Moore in 1965 and was in effect being fol-lowed by the semiconductor industry since the early1960’s. (To read reprints of Gordon Moore’s 1965 and1975 papers along with recent commentaries onMoore’s Law, see the September 2006 issue of theIEEE Solid-State Circuits Society Newsletter.)

The ideas described in Moore’s and Dennard’spapers set our industry on a course of developing newintegrated circuit process technologies and products ona regular pace and providing consistent improvementsin transistor density, performance and power. Each newgeneration of process technology was expected toreduce minimum feature size by approximately 0.7x (κ~1.4). A 0.7x reduction in linear features size was gen-erally considered to be a worthwhile step to take for anew process generation as it provided roughly a 2xincrease in transistor density. During the 1970’s and1980’s the semiconductor industry was introducing newtechnology generations approximately every 3 years.This translates to transistor density improvements of ~2xevery 3 years, but this was also a period when averagechip sizes were increasing, resulting in transistor countincreases of close to 4x every 3 years (or 2x every 18months). Starting in the mid-1990’s our industry accel-erated the pace of introducing new technology genera-tions to once every 2 years and that pace continues tothis day (see Figure 1). The trend of increasing chip sizehas slowed due to cost constraints, so we have settledinto a trend of roughly doubling transistor density andtransistor count every 2 years (see Figure 2).

Even more surprising, from a MOSFET scaling per-spective, is that over the past 10 years MOSFET gatelengths have been scaling faster than other minimumfeature sizes (see Figure 1). Prior to the mid-1990’s,

TECHNICAL ARTICLES

A 30 Year Retrospective on Dennard’s MOSFETScaling PaperMark Bohr, Intel Corporation, [email protected]

Table I: Scaling Results for Circuit Performance (from Dennard)

Figure 1: Feature size scaling for Intel logic technologies

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gate lengths were roughly the same size as other min-imum process features, but starting with the 0.35 μmgeneration, gate lengths have been scaling faster than0.7x per generation to realize performance advan-tages, even though gate pitch has been scaling at thenormal rate. This has been a key factor in micro-processors achieving >3 GHz operating frequenciessooner than most experts thought possible even 10years ago. It is exciting to see in Figure 3 how far wehave taken Dennard’s scaling law by comparing the 1mm transistor described in his 1974 paper to the 35nm gate length transistor used in Intel’s 65 nm gener-ation logic technology that started high volume man-ufacturing in 2005 [2]. The Intel transistor shown inFigure 3 provides an example of an emerging trendamong semiconductor manufacturers: the introduc-tion of new structures and materials to extend transis-tor scaling. In this case the new feature is selectivelydeposited SiGe source-drains to provide strained sili-con for improved transistor performance [3].

Just as there have been questions about the end ofMoore’s Law, there have also been questions aboutthe end of MOSFET scaling. In both cases, the answeris that the end is not yet in sight, although we facegrowing challenges in their continuation. Voltage scal-ing has been an extremely important component ofMOSFET scaling because it maintains constant electricfield, which is important for reliability, and it lowerstransistor power, which is needed to maintain con-stant power density. But even in the early days ofMOSFET scaling it was difficult to follow ideal voltagescaling requirements because of the need to useindustry standard voltages, such as 12V, 5V, 3.3V, etc.Eventually we were able to deviate from standardvoltage levels on key products such as microproces-sors and were free to adjust product voltage levels tomeet specific performance and power targets. Morerecently, however, voltage scaling has run into lowerlimits imposed by threshold voltage (VT) scaling limits[4]. Dennard’s scaling law assumed that VT wouldscale along with operating voltage, and thus provide

improved performance and power. But this 1974work ignored the impact of transistor sub-thresholdleakage on overall chip power. Sub-threshold leakagewas relatively low in the 1970’s and was a tiny con-tributor to total power consumption on logic circuits.But after 30 years of scaling, VT has scaled to the pointwhere sub-threshold leakage has increased from lev-els of <10-10 amps/mm to >10-7 amps/μm. Due to leak-age constraints, it will be difficult to further scale VT

and thus it will also be difficult to scale operating volt-age.

Another key assumption in Dennard’s scaling lawwas the ability to scale gate oxide thickness. Gateoxide scaling has been a key contributor to scalingimprovements over the past 30 years, but this trend isalso slowing due to leakage constraints (see Figure 4).Intel’s 65nm generation transistors use a SiO2 gatedielectric with a thickness of 1.2 nm [2]. This dielectricis only about 5 silicon atomic layers thick and repre-sents what is likely the limit to which SiO2 can bescaled. Not only are we running out of atoms, but gateoxide leakage due to direct tunneling current is becom-ing a noticeable percentage of overall chip power.

Dennard’s scaling law assumed that channel dop-ing concentration could be continually increased toenable shorter channel lengths with the appropriateVT. When channel doping concentration gets too high

TECHNICAL ARTICLES

Figure 2: Transistor count trend for Intel microprocessors

Figure 3: MOSFET structure from Dennard’s 1974 paper(left) and from Intel’s 65 nm generation logic technologyin 2005 (right)

Figure 4: Gate oxide thickness trend for Intel logictechnologies

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two problems occur: 1) carrier mobility and perform-ance degrade due to increased impurity scattering, 2)source and drain junction leakage increases due todirect band-band tunneling. Junction leakage isalready a limiter for ultra-low power integrated cir-cuits and will eventually be a limiter for mainstreammicroprocessor products.

Although Dennard’s paper is best known for artic-ulating MOSFET scaling rules, less noticed was thepaper’s description of interconnect scaling results, asreproduced here in Table II. The key point of thistable is that scaled interconnects, unlike scaled tran-sistors, do not speed up. Scaled interconnects provideroughly constant RC delays because the reduction inline capacitance is offset by an increase in line resist-ance. This was not much of a concern in 1974 wheninterconnect delay was typically a small portion ofcircuit clock cycle times. But more modern logic tech-nologies have been wrestling with the constraintsimposed by interconnect delay and interconnect den-sity [5], and have been addressing these constraints byadding more metal layers, converting from aluminumto more conductive copper wires, and replacing SiO2

dielectrics with low-κ dielectrics to reduce capaci-tance (see Figure 5).

As briefly described above, scaling transistorsbeyond the 65 nm generation will clearly have morechallenges to contend with. It is also commonly rec-ognized that following the simple scaling rulesdescribed by Dennard and his team back in 1974 isnow no longer a sufficient strategy to meet futuretransistor density, performance, and power require-ments. But ours is a very inventive industry and newtransistor technologies such as strained silicon, high-κ

dielectrics, metal gates and multiple-gate devices havebeen or will be introduced to continue scaling. Soalthough the letter of “Dennard’s Law” can no longerbe followed, it has gotten us very far over the past 30years and the spirit is alive and well in transistor R&Dfacilities around the world.

References[1] R. Dennard, et al., “Design of ion-implanted

MOSFETs with very small physical dimensions,”IEEE Journal of Solid State Circuits, vol. SC-9, no.5, pp. 256-268, Oct. 1974.

[2] P. Bai, et al., “A 65nm logic technology featuring35nm gate lengths, enhanced channel strain, 8Cu interconnect layers, low-k ILD and 0.57 μm2

SRAM cell,” International Electron Devices Meet-ing Technical Digest, pp. 657-660, 2004.

[3] K. Mistry, et al., “Delaying forever: Uniaxialstrained silicon transistors in a 90nm CMOS tech-nology,” Symposium on VLSI Technology Digestof Technical Papers, pp. 50-51, 2004.

[4] Y. Taur and E. Nowak, “CMOS devices below 0.1μm: How high will performance go?” Interna-tional Electron Devices Meeting Technical Digest,pp. 215-218, 1997.

[5] M. Bohr, “Interconnect scaling - The real limiterto high performance ULSI,” International Elec-tron Devices Meeting Technical Digest, pp. 241-244, 1995.

About the AuthorMark Bohr is an Intel Senior Fellowand Director of Process Architectureand Integration. He is a member ofIntel’s Logic Technology Developmentgroup located in Hillsboro, Oregon,where he is responsible for directingprocess development activities forIntel’s advanced logic technologies.

He joined Intel in 1978 and has been responsible forprocess integration and device design on a variety ofprocess technologies for dynamic RAM, static RAM andmicroprocessor products. He is currently directing devel-opment activities for Intel’s 32 nm logic technology.

Bohr was born in Chicago, Illinois in 1953. Hereceived the B.S. degree in industrial engineering in1976 and the M.S. degree in electrical engineering in1978, both from the University of Illinois, Urbana-Champaign. In 1998 he received the DistinguishedAlumnus Award from the University of Illinois depart-ment of Electrical and Computer Engineering. Bohr isa Fellow of the Institute of Electrical and ElectronicsEngineers and was the recipient of the 2003 IEEEAndrew S. Grove award. In 2005 he was elected tothe National Academy of Engineering. He holds 42patents in the area of integrated circuit processing andhas authored or co-authored 40 published papers.

TECHNICAL ARTICLES

Table II: Scaling Results for Interconnect Lines (from Dennard)

Figure 5: Copper interconnects with low-_ dielectrics fromIntel’s 65 nm logic technology

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In 1974 Robert Dennard, etal1, wrote a paper thatexplored different methods of scaling MOS devices,and pointed out that if voltages were scaled with

lithographic dimensions, one achieved the benefits weall now assume with scaling: faster, lower energy, andcheaper gates. The lower energy per switching eventexactly matched the increased energy by having moregates and having them switch faster, so in theory thepower per unit area would stay constant. This set of lin-ear scaling principles of MOS technology has served asthe treadmill on which the entire Semiconductor Indus-try has grown for the past three decades.

Scaling in the 70’s: The Era of NMOSDynamic Random Access MemoriesThe late 70’s NMOS based DRAMs led the technologyscaling charge in a world that was still largely bipolar anddominated by TTL logic chips. The first rounds of theapplication of scaling theory were focused on DRAMs.Unique clock design schemes for DRAMs devised atMostek and technology from Intel and IBM ushered inthe 16k bit VLSI DRAM, the pride of the late 70’s.

Japan’s MITI created the VLSI Technology Project2,a consortium of five top Japanese microelectronicscompanies: Hitachi, NEC, Fujitsu, Mitsubishi andToshiba. This consortium developed a complete tech-nology infrastructure for the 256K DRAM andlaunched into the 1 micron VLSI era with strongprogress in ultra clean technologies which gave Japanthe lead in VLSI manufacturing in the early 80’s.

The Early 80’s: Crossing the Micron Barrier Even though the scaling charge was led by NMOS,power and ease of design considerations favoredCMOS Technology as the industry workhorse. Theworld, however, was stuck at the TTL voltage andlogic level standard or 5V. The resistance to scalingvoltage in the early 80’s from system designers backedinto the semiconductor world. This led me to proposea quasi constant voltage scaling3.The emergence ofvoltage tolerant device structures like the lightly dopedrain (LDD) transistor, silicide clad source drain, andhot electron defense resulted from this. These tech-nologies provided some of the keys to continue scal-ing feature sizes slower than voltage and continuingthe treadmill for the Semiconductor Industry.

ASIC and CAD Transforms the Chip DesignIndustry Carver Meade and Lynn Conaway in their classicbook, ‘Introduction to VLSI Systems’, used the notion

of linear relationships between different devicegeometries to simplify the “design rules” that abstract-ed the manufacturing constraints from design. Lineardevice scaling theory also allowed simplification of avery complex interaction of process and devicephysics with design.

Device models to represent the complex physics ofCMOS devices in circuit simulators, like SPICE, providedthe abstraction between circuit theory and devicephysics. Based on these abstractions the industry wasable to rapidly develop design tools and systems. TheUniversity of California, Berkeley4 was a leader in devel-oping a suite of design tools that connected logic leveldesign to circuit design to physical design and verifica-tion tools to check for design rules. The entire ASICworld of semi-custom chips opened up based on this setof abstractions and made scaling applicable to all chips.

The Emergence of TCAD: Systematic Technology Design The notion of creating generations of process tech-nology that could be used for a variety of applicationswas emerging simultaneously with the ASIC move-ment to systematize chip design. Linear scaling factorsbegan to be used as the names of the generation oftechnology and an informal time table started beingdiscussed across the industry. A team at Stanford Uni-versity initiated a whole new field of technology CAD5

with Process Simulators and Device Simulators. Thisallowed systematic design of process and devicesusing formal design of experiment methods.

Manufacturing yield and defect analysis did not comeunder the purview of scaling theory and threatened tostop the scaling treadmill. Redundancy and repair tech-niques based on laser links were the initial answer tocontinue memory scaling beyond 256 Kbit. This wasfollowed by yield analysis tools that were developed atCarnegie Mellon University6. Defect measurement toolsoffered by KLA, systematic yield analysis and rampprocesses made the technology treadmill continue tomove down the linear scaling path.

Single Wafer Manufacturing Systems forScaling to Larger Wafers with Sub HalfMicron FeaturesFrom 1988 through 1993 Texas Instruments partneredwith DARPA, the U.S. Air Force, semiconductor equip-ment makers, and university researchers in the Micro-electronics Manufacturing Science and Technology(MMST) Program7. Its purpose was to develop advancedIC manufacturing technologies enabling dramatic

TECHNICAL ARTICLES

Device Scaling: The Treadmill that Fueled ThreeDecades of Semiconductor Industry GrowthPallab Chatterjee, i2 Technologies, Inc.

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TECHNICAL ARTICLESimprovements in process control, cycle-time, and overallflexibility and continue the scaling of devices to deepsubmicron to cost effectively. In particular, the MMSTProgram demonstrated the technical feasibility of 100%single-wafer processing, dynamic/object-oriented Com-puter-Integrated-Manufacturing (CIM), real-time/model-based process control, in-situ sensors, 95% dry process-ing, and integrated mini environments.

At that time, state-of-the-art commercial wafer fabsused a mix of approximately 60% single-wafer and40% batch processing equipment. Since then, com-plete sets of commercial single-wafer process toolshave become available and are the norm for deepsubmicron manufacturing.

The most significant contribution of MMST to sin-gle-wafer processing was in the area of Rapid ThermalProcessing (RTP). In contrast to large furnaces forthermal processing, the MMST program developedprocessing chambers in which single wafers wereheated by lamps under multi-zone, closed-loop wafer-

temperature control. Some of the initial MMST workon RTP lamps was performed in collaboration withStanford University. Applied Materials, Inc. subse-quently introduced RTP on their Centura HT™ clustertool. MMST also created the first lithography clustertool and the concept of the vacuum carrier which ismore popularly knows as the SMIF box.

SIA Industry RoadmapIn November 1992, 179 of the key semiconductor tech-nologists of the US gathered in Irving, Texas for a his-toric workshop to create a common vision for the courseof the semiconductor industry for the next 15 yearsbased on scaling technology8. The group consisted pri-marily of scientists and engineers from the US Semicon-ductor Industry and a liberal sprinkling of academics,government agencies and national laboratories. Theworkshop, sponsored by the Semiconductor IndustryAssociation and coordinated by Semiconductor ResearchCorporation and Sematech, created the roadmap below.

1992 SIA Overall Roadmap Technology Characteristics

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Five areas of critical challenges that could decreasethe rate or even stop the progress of scaling of Semi-conductor technology were identified:• Patterning material and processes for device

structures below 0.25μm • Electrical interconnections, both on and off chip• Electrical test, time cost and capability• Design, modeling, simulation capability for all

elements of IC technology and products• Software capability, availability and quality for all

aspects of IC technology and production.As we look back at the last 15 years now at the end

of 2006, this roadmap has truly focused the invest-ment and made most of the predictions come true.

Emergence of Foundry ManufacturingCompaniesAs the process technology scaling became more sys-tematic the disaggregating of IC manufacturingbecame a reality. Since the establishment of TSMC in1987 to satisfy customers’ needs under the disintegra-tion trend, the pure play foundry industry has grownto a multi-billion business. In turn, the pure playfoundry business model has further accelerated thedisintegration trend in the semiconductor industry.

In the past decade, leading foundry companies havecaught up with the leading IDMs (Integrated DeviceManufacturers) in process technology prowess. Thetechnological challenges of foundry companies in thenext decade will be even more challenging than thoseof leading IDMs because of the need to emphasizemore on process versatility, cost effectiveness and easyadoption by diversified customers.

The specific technology development challenges ofa successful foundry company in the next decadeinclude: (1) aggressive scaling of transistors, intercon-nect, and design rules for both performance and den-sity; (2) embedded technologies for SOC solutions; (3)cost effective and manufacturability process technolo-gy; (4) a versatile technology portfolio; and (5) easyintegration among customers, design service/IPproviders and the foundries.

In the next decade, the foundry paradigm isexpected to play an even more important role asfoundry companies continue to build their core com-petencies, including leading-edge process technolo-gies, advanced and flexible manufacturing capabili-ties, and customer-oriented services systems. Thestrong entrenchment of the foundry industry will fur-ther move the semiconductor industry in the directionof complete disintegration.

Scaling continues to be the Treadmill of theSemiconductor IndustryLooking back at the last few years since the first SIAworkshop, the ability to marshal and focus the invest-

ments of the entire industry on the key technologyissues has indeed been an enabler for scaling downto 90nm. The top three among these are:

1. Sub-wavelength optical lithography (includingOPC/Resolution Enhancement Techniques):

Advances in scanners and resist technologyenabled printing features less than one-half of thelight wavelengths. Chemically amplified resists,light polarization, phase shifting techniques (alter-nating apertures and attenuated), as well as com-prehensive Model Based Optical Proximity Correc-tions of critical layer layouts, are the key enablers.

2. Extending bulk CMOS by several performanceboosters - stress/strain, ultra shallow junctions, andox nitrides:

Conventional bulk CMOS device architectures havebeen extended to 90 nm and below technologynodes by employing several performance boosterssuch as:

- bi-directional stress/strain layers to enhancecarrier mobility for both electrons andholes,

- ultra-shallow junctions obtained by verylow energy implants and flash/laseranneal

- very thin (1.2 nm) gate ox nitride layers thatprovide uniform layers, good interface toboth substrate and polysilicon gate and pre-vent Boron penetration.

3. Multilevel Cu interconnect including CMP:

Up to 12 layer of Cu interconnect layers have beenachieved thanks to Double Damascene Cu deposi-tion/patterning technology and improvement in chem-ical mechanical polishing. Dishing/erosion effectshave been reduced by applying smart dummy fill andadditional manufacturability layout design rules toeliminate wide lines/small spacing patterns and dras-tic density variations within each interconnect layer.

As we look forward to the continuation of these 30years of scaling progress, there are similar chal-lenges to overcome to scale to 45nm and below:

1. Device/process variability9:

Process variability sources can be categorized basedon the spatial hierarchy: lot-to-lot, wafer-to-wafer,within-wafer or within-die, or root causes (randomor systematic). These sources create a complicateddistribution of parameters that must be addressed

TECHNICAL ARTICLES

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TECHNICAL ARTICLESby circuit designers. One of the key parameters ispoly linewidth, since it has the dominant effect onMOS transistor electrical performance. For 90nmtechnologies, more than 50% of the variance in polyline width comes from within-die (within field) vari-ations. The next component is die-to-die. The per-centage of systematic variations increases withdevice scaling. For 90nm NMOS transistors, it reach-es 40% of the overall Across Chip Variance (ACV).

Transistors behave differently based upon theneighborhood layout pattern due to printability andstress/strain effects. Moreover, printability andChemical Mechanical Polishing (CMP) cause signif-icant variations in interconnect parameters such asresistance and capacitance.

2. New device architecture (UTB, dual gates) lessdependent on channel doping fluctuations:

Despite quite a few novel device architectures pro-posed in recent years (FinFET, Ultra Thin BodyTransistor, Inverted T FET), the bulk CMOS devicearchitecture is used virtually exclusively at 45 nm.It will most likely dominate the 32 nm nodes,although SOI substrates are gaining more accept-ance. This leaves the device performance variationsvery susceptible to random dopant fluctuations.Performance boosters are additive and help, butalso create additional variability sources whichforces circuit designers to accept much higher vari-ability and as well as leakage currents.

3. Material improvements: high-k for gate dielectrics,porous low-k for interconnects:

Several candidates for high-k materials have beenexplored; but although Hf or Zr based oxides/sili-cates provide attractive dielectric constant valuesand are stable, they do require interfacial SiO2 lay-ers between high-k layers and substrate/polysili-con. The final stack is not as beneficial anymore.Hence, high-k gate dielectrics are not employed inthe vast majority of 45 nm technologies and only incombination with metal gates do they have achance at 32 nm.

4. Advanced process control (especially feed forward):

Given the increasing complexity and small processwindows, yield variability is a very significant prob-lem. Baseline process variability keeps on increas-ing (tails of wafer yield distributions) and the pres-ent metrology/inspection static sampling plans failat detecting excursions in-line. New approaches foryield relevant SOC and APC are needed to takeadvantage of the increased process observables

due to in-situ equipment sensor/FDC deployment.

5. Compact device models:

Below 100 nm, compact device models mustaccommodate microscopic (i.e., “non-bulk”) physi-cal effects with minimal impact on overall compu-tational complexities. BSIM has filled this role formany technology generations as the workhorse,both for model characterization and node-to-nodetechnology predictions. It continues to have theconfidence of industry and seems likely to remainin service (with the possible exception of RF) downto about 45 nm.

More recent MOS models are formulated as func-tions of surface potential, rather than thresholdvoltage, in the channel and s/d edges. Surfacepotential is directly linked to intrinsic channelcharge dynamics and enables addition of importantphysical effects with an economy of model com-plexity. The formulation admits an expression fortransistor drive current that is continuous fromaccumulation to saturation, thereby avoiding thenecessity of matching multiple regions.

Compact models at 65 nm have high priority needsfor improvement:

(a) scalability of sub-threshold currents and outputresistance from short-to-long channel lengths,due largely to lateral doping non-uniformities

(b) dependence of noise on voltage and geometry;i.e., considering 1/f noise dependence on ran-dom noise trap occurrences

(c) capabilities for handling geometrical statisticalfluctuations which affect noise, threshold volt-age and drive current.

The above problems become more severe at 45 nm,along with the following additional priorities:

(1) gate current scaling and dependences on novel(e.g., multi-layer) gate stacks,

(2) carrier mobility in the channel due to layout-induced stress/strain,

(3) statistical variations stemming from randomdopant placements,

(4) ballistic transport of carriers in intrinsic channeland,

(5) quantum mechanical effects due to confine-ment in thin films.

SummaryScaling theory has been the organizing principle of theprogress of the semiconductor industry throughoutthree decades. It has created a framework for contin-ued improvement in density and cost performanceand facilitated the desegregation of the entire industry

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TECHNICAL ARTICLES


around design and manufacturing. Few concepts inour time have had as much influence on the economy.

AcknowledgementI would like to thank Ping Yang, Bob Doering,Andrzej Strojwas, Robert Dutton, Bill George,Lawrence Arledge, and Alberto Sangiovanni-Vincen-telli for providing perspectives on the various aspectsof impact of scaling on the semiconductor industry forthis paper.

References[1] R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E.

Bassous, andA.R. LeBlanc, “Design of Ion-Implanted MOSFET’s with Very Small PhysicalDimensions,” IEEE Journal of Solid-State Circuits,Oct. 1974.

[2] Cheney, D.W. and Grimes, W.W. Japanese Tech-nology Policy: What’s the secret (February 1991),Council on Competitiveness, pp. 1-26.

[3] P. K. Chatterjee, W. R. Hunter, T. C. Holloway,and Y. T. Lin, “Technology Induced Non-Con-stant Field Scaling and its Impact on SubmicronDevice Performance,” Dev. Res. Conf., Cornell,June 1980

[4] Alberto Sangiovanni-Vincentelli, Editorial, Spe-cial Issue on CAD of VLSI, IEEE Transactions ofCircuits and Systems, July 1981. and RichardNewton, Donald O. Pederson, Alberto Sangio-vanni-Vincentelli, and Carlo Sequin, Design Aidsfor VLSI: The Berkeley Perspective, IEEE Transac-tions on Circuits and Systems, Vol. CAS-28, No.7, pp. 660-680, July 1981

[5] D. A. Antoniadis and R. W. Dutton, Models forComputer Simulation of Complete IC FabricationProcess. IEEE J. Solid-State Circuits, SC-14(2):412-430, and Robert Dutton: Father of TCAD-http://www10.edacafe.com/nbc/articles/view_article.php?articleid=315936

[6] W. Maly, A.J. Strojwas and S. W. Director, “VLSIYield Prediction and Estimation - A UnifiedFramework,” IEEE Trans. on CAD of ICAS, Spe-cial Issue on Statistical Design, Jan.1986

[7] R.R. Doering and D.W. Reed, “Exploring the Lim-its of Cycle Time for VLSI Processing,” TechnicalDigest of the 1994 Symposium on VLSI Technol-ogy, pp. 31-32, Honolulu, Hawaii, June 7, 1994.

[8] Semiconductor Technology Workshop Conclu-sions Report 1992. Linda Wilson, InternationalTechnology Roadmaps for SemiconductorsSematech and http://www.reedelectronics.com/semiconductor/article/CA490081

[9] A. J. Strojwas, “Conquering Process Variability: AKey Enabler for Profitable Manufacturing inAdvanced technology Nodes”, Keynote Paper,ISSM 2006, Tokyo, Japan, September 2006

Dr. Pallab Chatterjee is ExecutiveVice President, Solutions Officer andChief Delivery Officer of i2 Tech-nologies, Inc.

He is responsible for SolutionsOperations, which includes Solu-tion business units for SRM andMDM, Research and Development,

Information Technology, Global Solution Center,Global Customer Solution Management and i2’sIndia Operations.

During his tenure at i2 Dr. Chatterjee has overseen theevolution of i2’s industry-leading solutions, including thedevelopment and delivery of the i2 Agile BusinessProcess Platform and the company’s new-generationsupply chain management solutions. His extensive glob-al management experience and an in-depth understand-ing of i2’s market-leading supply chain solutions from acustomer's perspective have made him a valuable addi-tion to the i2 team since his arrival in January 2000.

Chatterjee worked at Texas Instruments from 1976-2000. During his tenure there he held various execu-tive positions. Under his leadership as senior vicepresident of Research and Development and chieftechnology officer, the Texas Instruments TechnologyLabs became known as a standard for excellenceacknowledged by both academia and industry. As TI’ssenior vice president and chairman of the Manufac-turing Excellence team, he was responsible for man-ufacturing improvements which delivered hundredsof millions of dollars in bottom-line improvement. Aspresident of TI’s Personal Productivity Products (cal-culators and PC business), he contributed to increas-ing Texas Instruments’ market share and managedmore than $1.5 billion worldwide. In the role of chiefinformation officer, he led the global i2 and SAPimplementation and process transformation for TexasInstruments.

During Chatterjee’s tenure at Texas Instruments, hewas a TI senior fellow in 1985, an IEEE fellow in 1986,and received the IEEE J. J. Ebers award in 1986. Hewas elected a member of the National Academy ofEngineers in 1997.

Chatterjee has been awarded numerous patents andhas written several publications on the high technolo-gy industry. He earned a Bachelor of Technologydegree in electronics and communication engineeringfrom the Indian Institute of Technology, Kharagpur,India. As a student there, he was awarded the Presi-dent of India Gold Medal as the class valedictorian andthe B.C. Roy Memorial Gold Medal for extracurricularexcellence. He received his master's and doctoratedegrees in electrical engineering from the University ofIllinois, and was awarded a honorary Doctor of Sci-ence Degree from Indian Institute of Technology,Kharagpur, India.

About the Author

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The BeginningsBy 1970 the MOSFET technology was finding its wayinto manufacturing in a number of companies.1 BobDennard and I were part of the team that developed theNMOS technology (2) in the T. J. Watson IBM ResearchLaboratories in the 1960s. The first IBM NMOS MOSFETproduct, which was entering large scale manufacturing,was a high-speed main-memory with a 50ns typicalaccess time (100ns spec) at the board level. It used 1Kbchips (soon replaced with 2Kb chips) with a six-devicecell using off-chip bipolar sense amplifiers and highlevel decoders proposed by Peter Pleshko and LewisTerman (3). These chips replaced the bipolar main-memory technology which had been introduced a cou-ple of years earlier to replace ferrite core memory.

In mid-1970, IBM Research management was search-ing for a technology to fill the “file gap” between move-able head magnetic disks and random access main-mem-ory for transaction based systems. This performance gapwas being filled by expensive fixed head HDDs whichhad much smaller latency time than the moveable headHDDs. Don Rosenheim (Manager of Applied Research)and Sol Triebwasser challenged my department to devel-op a proposal for a “monolithic file” with a cost/bit ofabout 1 millicent/bit or 1/1000 of the projected main-memory cost. Bob Dennard was manager of a smallgroup including Fritz Gaensslen and Larry Kuhn whichreported to me. There were a number of options includ-ing shift registers and CCDs, but Dennard as the inven-tor was keen on pursing the one-transistor DRAM cell.Bob did some preliminary analyses, and concluded thatwe would need feature sizes of about 1μm, a 5X shrinkfrom those in manufacturing, to achieve our goals.

We realized that we would have to scale the verticaldimensions (oxide thickness and junction depth) andadjust the doping level of the substrate to maintain usabledevice characteristics. Further, we would have to scalethe operating voltages as well to preserve reliability andlimit power dissipation. In fact, we had done this twicebefore in the 1960s, first from 24V to 12V and then to 6Vusing rudimentary scaling to guide our designs. (Engi-neers of that era, before the advent of computer simula-tion, were well versed in design by similitude or scaling.)We observed that our current transistors with channellengths of 5μm and gate oxide thickness of 100nm couldbe operated at 20V. Therefore, we could scale to a 4Vpower supply with a 1um, 20nm transistor. We noted thatthe circuits would consume less power and be faster.Within a few days Bob, Fritz and Larry had formalizedthe constant-field scaling theory and its limitations.

The implications of scaling were remarkable. If alldimensions, voltages (including threshold voltage) and

doping levels were scaled by a constant factor κ: a) thecircuit delay was decreased by κ, b) the power/circuit wasdecreased by κ2, and c) the power delay product wasreduced by κ3. Further, the power/unit area of siliconremained constant! These were exactly the results weneeded to develop a competitive low cost memory. Onthe down side, there were questions about the scalabilityof the threshold voltage and the fact that the IR drops andRC time constants of the interconnects become moresevere with scaling. Of course, there were a host of tran-sistor design, process and reliability challenges.

At that point, we were convinced that MOSFET mem-ory would replace fixed head files. Further, we speculat-ed that it may also replace moveable head disk storagefor some applications. We also started to believe that theMOSFET would someday replace the bipolar transistor inhigh-performance logic and memory applications.

Driving the Demonstration and Implementation of Scaling was KeyBob Dennard’s most profound contributions were todemonstrating the feasibility of MOSFET scaling, andthen leading the way into implementation in real prod-ucts. He worked with a succession of very talented engi-neers over several decades, providing guidance as wellas continuing to make significant technical contributions.

The principles of scaling were first presented at the1972 IEDM (4) along with the design and experimen-tal characteristics of an ion-implanted 1μm transistorwith a 20nm gate oxide2 which had been optimizedfor scaling. One of the original slides used to describescaling is shown in Fig. 1. (Bob remembers a highdegree of skepticism about the feasibility of 20nm

TECHNICAL ARTICLES

Recollections on MOSFET ScalingBy Dale L. Critchlow, IBM Fellow, Retired; [email protected]

Fig. 1 Slide from 1972 IEDM showing some of the scalingprinciples.

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oxides from the audience many of whom were strug-gling with making reliable 100nm oxides.) This wassoon followed with a 1973 IEDM paper (6) utilizingion-implantation to allow improved scaled transistors.The paper normally considered the “scaling paper”was published in 1974 (7). In 1975 Dennard, with oth-ers, proceeded to demonstrate scaling on a complexchip by scaling an existing 8Kb PMOS chip (original-ly designed in 3.75μm ground rules) by 3X and fabri-cating it with 1.25μm feature sizes using electronbeam lithography (8). A photo of several cells andsupport circuits is shown in Fig. 2. Hwa Yu developedan anisotropic dry etching process which made it pos-sible to delineate the 1.25μm features. The success ofthis experiment had a major impact on how seriouslypeople took scaling both inside and outside IBM.

Attention was then turned to high-speed logic andSRAM. One of our goals was to lay the groundwork forreplacing bipolar transistors in mainframe computers.This culminated in a series of eight papers (9) describ-ing a 1μm technology that took advantage of the scalingprinciples. Bob was coauthor of several of the papers.

Bob continued to push the envelope with a large num-ber of publications in cooperation with a succession ofyoung researchers. Describing these papers is wellbeyond the scope of this paper. However, a few keypapers stand out. In 1984, with Giorgio Baccarani andMatt Wordeman, he generalized the scaling theory to takeinto account the parameters which did not scale well (10).In 1985, he co-authored a definitive paper on 1μm CMOS(11) with Yuan Taur and others. In 1995, a paper layingthe groundwork for a 0.1mm CMOS on SOI technologywas published by Ghavam Shahidi and others (12).

In addition, Dennard furthered the cause and pre-sented the challenges of MOSFET scaling to technicalaudiences outside the IEEE organization. For exam-ple, he published a paper in 1981 in the Journal of

Vacuum Science and Technology (13) which showedthe practicality of scaling to submicron devices anddescribed the hierarchical wiring system needed totake advantage of scaling. In 1985 he published anauthoritative paper on scaling to deep sub-microndimensions in Physica (14).

Although he was not listed as an author, Bob had amajor influence on the keystone 1988 paper (15) by BijanDavari, et al, which described the 2.5V, 0.25μm CMOStechnology which was key to the replacement of bipolartechnologies for high-speed main-frame computers andmicroprocessors.

Technical Challenges and Advances toMake Scaling FeasibleEven though the principles of scaling, and the under-standing that the MOSFET could be scaled existed inthe early 1970s, the benefits of scaling could not havebeen accomplished without many other technicaladvances in the industry over the decades. There wereremarkable improvements in optical lithography, dryetching, ion implantation, insulators, polycide and sili-cided contacts, multilevel metal, planarized BEOL, cop-per wiring, shallow trench isolation, packaging, designtechniques, testing and characterization, design toolsand system architecture. The switch to CMOS was criti-cal to containing the level of chip power.

These improvements allowed scaling of the MOS-FET technology to meet the expectations of the indus-try following the trends popularized in recent decadesas Moore’s Law (16).

The Long Delay before Switching to LowerPower Supply VoltagesWhile the advantages of scaling were apparent to manypeople, it was two decades before the power supplywas scaled for mainstream products, Fig. 3. The indus-

Fig. 2 Photograph of portion of experimental 8Kb DRAMchip using 1.25μm features which was scaled from a3.75μm design.

Fig. 3 Transition of mainstream MOSFET products from 5Vto scaled voltages occurred two decades after scalingprinciples were defined.

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TECHNICAL ARTICLEStry settled on 5V supplies in the early 1970s to be com-patible with bipolar TTL. In fact, this was a lower volt-age than what could have been possible for the dimen-sions being used. Consequently, the improvements intransistor design and chip fabrication were applied to5V technologies, significantly improving componentpacking density and performance over several genera-tions. Further, the LDD device (17) allowed reliableoperation and high performance at 5V. The tighter tol-erances necessary to make scaling practical improved5V designs as well, reducing the performance advan-tage of full scaling. Most importantly, the whole com-puter industry was optimized around a 5V power sup-ply and very successful products were being delivered.An earlier switch to a lower voltage would have beengreatly disruptive to the designers, the manufacturersand in the marketplace.

The 5V standard finally collapsed in the late 1980sdue to three major forces:

1) The power dissipation at 5V became untenable,especially as the circuits were driven to higherspeeds.

2) The portable, battery-powered applications weredemanding higher performance, low power andcompatibility with battery voltages.

3) The inherent speed advantages of scaled transis-tors, as tolerances improved, were needed forhigh-speed applications.

Once the dam broke there was tremendous changewithin a few years, first to 3.3V then to 2.5V, etc.

The Impact of MOSFET Scaling has beenMonumentalScaled CMOS has become the dominant technologyfor digital and many analog applications and will con-tinue to be a fundamental driving force of the indus-try for years to come.

By the late 1980s, DRAM had long displaced fixedhead files in the file gap. In recent years, we havebeen seeing flash memory replacing disk drives inmany portable applications.

The 2.5V CMOS technology (15) was the deathknell for high performance silicon bipolar technolo-gies in high-end computers. BiCMOS had gatheredsome momentum, but when designers came to real-ize that very effective off-chip drivers could be madeusing MOSFET circuits, BiCMOS soon faded. By theearly 1990s, the high-end computers were beingdesigned using low-voltage scaled CMOS (18) replac-ing bipolar chips. Bipolar and BiCMOS have foundnew applications for very high-speed applicationsusing more exotic technologies.

AcknowledgementsThe author is indebted to B. Davari, R. H. Dennard,E. J. Nowak and L. M. Terman for providing informa-tion for this paper. He also wishes to acknowledge a

large number of outstanding engineers in IBM, othercompanies and Universities who shared an incredible40 year journey in MOSFET technology.

References[1] To the Digital Age: Research Labs, Start-Up Compa-

nies, and the Rise of the MOS Technology; Ross KBassett, The John Hopkins University Press, 2002.

[2] “Design and characteristics of n-channel Insulated-gate Field-Effect Transistors”; D. L. Critchlow, R. H.Dennard, S. E. Schuster; IBM Journal of Researchand Development, vol. 17, no. 5, p. 430, 1973.

[3] “An investigation of the potential of MOS transistormemories”; P. Pleshko and L. M. Terman; IEEETransactions on Electronic Computers, vol. EC-15,No. 4, pp. 423-427, August 1966.

[4] “Design of micron MOS switching devices”; R. H.Dennard, F. H. Gaensslen, L. Kuhn, H. N. Yu; IEDMTech. Dig., pp. 168 - 170, December 1972.

[5] “Fundamental limitations in microelectronics – 1.MOS technology”; B. Hoeneisen and C. Mead, SolidState Electronics, vol. 15, no. 7, pp. 819-829, July 1972.

[6] “Ion implanted MOSFETs with very short channellengths”; R. H. Dennard, F. H. Gaensslen, H. N. Yu,V. L. Rideout, E. Bassous, A. LeBlanc; IEDM Tech.Dig., pp. 152 - 155, December 1973.

[7] “Design of ion-implanted MOSFET's with very smallphysical dimensions”; Robert H. Dennard, Fritz H.Gaensslen, Hwa-Nien Yu, V. Leo Rideout, ErnestBassous, Andre R. LeBlanc; IEEE Journal of Solid-State Circuits, vol. 9, pp. 256 - 268, October 1974.

[8] “Fabrication of a miniature 8-Kbit memory chipusing electron beam exposure”; H. Yu, R. Dennard,T.H. P. Chang, C. Osburn, V. DiLonardo and H.Luhn; J. Vac. Sci. Technol., vol. 12, no. 6, p.1297.Nov./Dec. 1975.

[9] “1 mm MOSFET VLSI technology: Parts I-VIII”; IEEEJournal of Solid-State Circuits, vol. SC-14, pp. 240-301, April 1979.

[10] “Generalized scaling theory and its application to a_ micrometer MOSFET design”; Giorgio Baccarani,Matthew R. Wordeman, Robert H. Dennard; IEEETrans. Electron Devices, vol. 31, pp. 452 - 462, April1984.

[11] “A self-aligned 1-μm-channel CMOS technologywith retrograde n-Well and thin epitaxy”; YuanTaur, Genda J. Hu, Robert H. Dennard, Lewis M.Terman, Chung-Yu Ting, Karen E. Petrillo; IEEEJournal of Solid-State Circuits, vol. 20, pp. 123 - 129,February 1985.

[12] “A room temperature 0.1μm CMOS on SOI”; G. G.Shahidi, C. A. Anderson, B. A. Chappell, T. I. Chap-pell, J. H. Comfort, B. Davari, R. H. Dennard, R. L.Franch, P. A. McFarland, J. S. Neely, T. H. Ning, M.R. Polcari, J. D. Warnock; IEEE Transactions onElectron Devices, vol. 41, issue 12, pp. 2405-2412,Dec. 1994.

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[13] “CMOS scaling for high performance and lowpower – The Next Ten Years”; B. Davari, R. H.Dennard, and G. G. Shahidi; Proceedings of theIEEE, Vol. 83, No. 4, pp. 595-606, April, 1995. Earli-er version published in Nikkei Microelectronics, pp.144-1`54, September 1994.

[14] “MOSFET miniaturization – From one micron to thelimits”; R. H. Dennard and M. R. Wordeman; Physi-ca B + C, vol. 129, pp. 3-15, 1985.

[15] “A high performance 0.25 μm CMOS technology”;B. Davari, W. H. Chang, M. R. Wordeman, C. S. Oh,Y. Taur, K. E. Petrillo, D. Moy, J. J. Bucchignano, H.Y. Ng, M. G. Rosenfield, F. J. Hohn, M. D. Rodriguez;IEDM Tech. Dig., pp. 56 - 59, December 1988.

[16] Research Highlights with focus on Moore’s Law;IEEE Solid-State Circuits Society Newsletter, vol. 20,no. 3, September 2006.

[17] “Fabrication of high-performance LDDFET's withoxide sidewall-spacer technology”; Paul J. Tsang,Seiki Ogura, William W. Walker, Joseph F. Shepard,Dale L. Critchlow; IEEE Trans. Electron Devices, vol.29, pp. 590 - 596, April 1982.

[18] “Possibilities of CMOS Mainframe and its Impact onTechnology R&D”: A. Masaki, Symposium on VLSITechnology, May 28-30, 1991, pp. 1-4.

About the AuthorDale Critchlow is a retired electricalengineer with 35 years experienceat IBM and 15 years in academia.He received his Ph.D. in ElectricalEngineering from Carnegie Instituteof Technology in 1956. After teach-ing at CIT for two years, he joinedIBM Research. He became one the

early members of the NMOS MOSFET project in theT. J. Watson Research Center in 1964, where hemanaged the MOSFET device and circuit designwork through 1976. Next he transferred to the IBMComponents Division, first in East Fishkill, NY, andthen in Essex Junction, VT where he managed agroup responsible for the advanced development ofMOSFET logic and memory technologies. He retiredfrom IBM in 1993 and was faculty member at theUniversity of Vermont until 2005. He has active inIEEE activities and has published a number ofpapers and patents.

Dr. Critchlow is a Life Fellow of the Institute ofElectrical and Electronic Engineers, an IBM Fel-low and a member of the National Academy ofEngineers.

The Business of ScalingRakesh KumarTCX Inc., Technology ConnexionsSan Diego, [email protected]

In addition to technical challenges, managing the eco-nomics of scaling and increasing demand have beenkey factors in driving the semiconductor industry to

nearly $250B over the last 40+ years. The functionality perchip has increased 2x every two years1,2. Although the costof wafer fabs and manufacturing has increased significant-ly over the years, the semiconductor industry has main-tained a reduction of about 29%/year in the cost per func-tion (CPF)3. This translates to a halving of the CPF everytwo years1. In this paper we will provide an overview ofsalient business aspects and economics of scaling.

1. IntroductionSince the introduction of the first commercial integrat-ed circuit in 1961 and the introduction of the firstmicroprocessor in 1971, the semiconductor industryhas experienced a healthy growth of approximately15% CAGR4. In the mean time semiconductor saleshave grown more rapidly than the worldwide elec-tronics sales and the worldwide GDP and are now

roughly 20% of worldwide electronics sales and about2% of the worldwide GDP4. Fueling the growth hasbeen increasing demand for components for personalcomputers, automotive, mobile wireless and consumer

Figure 1 Worldwide semiconductor sales

1 Ross Bassett wrote an excellent Ph.D. thesis and published a book [1] on the early history of the MOSFET technology. The appendices have a wealth ofauthoritative historical information.

2 Concurrently, B. Hoeneisen and C. Mead published a theoretical paper [5] projecting that a 0.4mm transistor with 14nm oxides and 2V operation couldbe built.

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products. Although the growth rate is predicted to slowdown, the industry has demonstrated much resiliencein combating technical and business challenges.

Taking advantage of scaling, the industry hasincreased the number of components per chip steadily,as shown in Figure 2. This figure shows the historicalincrease in the number of transistors per chip (39% peryear average) in industry leading microprocessors4. Thistrend shows a doubling of the transistors per chip everytwo years. This trend was predicted by Gordon Mooreand has become known as “Moore’s Law”1,2. The figurealso shows the reduction of minimum feature size at anaverage rate of 12% per year. The number of transistorsper chip has increased 6 orders of magnitude while theminimum feature size has been scaled down over twoorders of magnitude during the last 35 years.

2. The Basic Cost EquationsThe basic equation for predicting the cost of an inte-grated circuit die (or “chip”) is:

where wafer cost is determined by factors such asfacilities and equipment depreciation, materials, laborand processing cost, and

Yield is a function of defectivity (or defect density)and critical area. Contributors to defectivity are usuallycategorized as systematic (or gross) and randomdefects3. Many different yield models have been used inthe industry. Simple models, such as the Poisson andthe Murphy models using the die area as the criticalarea were prevalent in the early days. The Bose-Einsteinmodel using die area but identifying a defectivity percritical layer has been used extensively in recent years8,9.Custom models exist at captive suppliers. More recent-ly, sophisticated calculations of critical area based oninformation embedded in the design database are being

used to estimate yield. Examples are the number ofvias and contacts in a design, the number of metal layercross-overs, and the like. A detailed discussion of theseis beyond the scope of this paper.

3. Overall Cost ReductionA key factor in managing the business feasibility of scal-ing is the semiconductor industry’s ability to maintain anoverall CPF reduction of 29%/year3 to 35%/year4. Withinany given process technology node the die cost and CPFare reduced due to the manufacturing and defectivitylearning curves. This is shown graphically in a concep-tual chart, Figure 3. As the volume of wafer and productshipments ramps up in each technology node, there is areduction in die cost (and therefore CPF) due to a reduc-tion in wafer cost; this decrease is due to process opti-mization and the manufacturing learning curve. Also, diecost is reduced as yield enhancement efforts are imple-mented, defectivity is reduced, yield increases and there-fore NDPW increases. A compilation of defect densitytrends indicates an average reduction of 19% per yearover the last 35 years4. The technology “cross-over”occurs when the CPF in the newer technology is belowthe CPF in the older technology.

4. Cost Reduction from Technology ScalingAn industry target has been to reduce minimum fea-ture size by around 30% at every process technologytransition. Table 1 shows the various process technol-ogy generations or “technology nodes” used since themid 1980’s.

Figure 2 Historical trends of transistors per chip and min-imum feature size

Die Cost = Wafer Cost / Net Die per Wafer

Net Die per Wafer (“NDPW”) = Yield* Gross Die perWafer (“GDPW”)

Gross Die per Wafer (“GDPW”) = Total usable Area onthe Wafer / Die Area

Figure 3 Cost per function and technology “cross-over”points

Table 1 Scaling ratio for various technology nodes sincethe mid 1980’s

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Such technology scaling was achieved typically inthe following manner:

a. Drive new photo lithography equipment andprocesses that allowed printing and patterning ofdimensions 30% smaller than in the previousgeneration.

b. Make improvements to other parts of theprocess, e.g., gate oxidation, ion implantation,diffusion, etching, interconnect metallurgy etc.

c. Engineer and optimize the transistor devicestructure and various aspects of the process tomeet performance and cost goals, and be manu-facturable and reliable.

d. Execute a “Linear Shrink” of an existing prod-uct reducing the die size by a scaling factor suchas 0.7. Due to various intricacies of the process,the design rules and device characteristics atshrinking geometries, such scaling becameincreasingly difficult. In the mid-1980’s such anapproach, which was referred to by some peo-ple as a “dumb shrink” became known as an“intelligent laborious shrink” at some companies.

e. A new set of design rules - both physical andelectrical - were usually used to design newproducts that took full advantage of the newtechnology capability. While the shrink approachwas able to get an initial product out in the newtechnology node, the “Re-Design” approach wasnecessary to maximize performance and mini-mize cost of products in the new node.

f. In addition, the new technology usually had somenew features aimed at increasing the packing effi-ciency, design productivity and device perform-ance. Some examples are: increasing the numberof metal interconnect layers, self-aligned polysili-con gate structure, oxide and trench isolation,standard cells, EDA tools and re-usable IP blocks.

We will now discuss migration of designs from onenode to the next using either the “Linear Shrink” orthe “Re-Design” approach. To illustrate the “LinearShrink”, consider Figure 4(a), which depicts a squaredie with dimension y and having N transistors, intechnology node T1. A simple shrink of the die intotechnology node T2 would reduce the die size by thescale factor k, where 0<k<1. It should be noted thatthis scaling factor corresponds to the factor 1/α usedby Dennard in his papers5. Table 2(a) is a summary ofthe resulting scaling parameters as well as typical val-ues for such a scaling. Although the cost to processthe wafer in the new technology node increases by afactor C (typically a 20% premium), the die cost andthe CPF reduces to Ck2 or 60% of the cost in the tech-nology node T1, for k=0.7. This initial analysisassumes the new technology is processed using thesame wafer size, and that the yield is the same in bothtechnologies.

The “Re-Design” approach is illustrated via Figure4(b) which depicts increased packing densityachieved by taking advantage of more aggressivetechnology features and design rules and a “Clever-ness Factor”, F. The number of transistors packed inthe same size die increases by a factor F2k-2. Furtherincreases in packing density resulted from the use oflarger die sizes. Manufacturing enhancements of theprocess, the equipment and the clean room environ-ment resulted in lower defect densities. This allowedthe fabrication of larger dice with acceptable yields inthe new technology node in spite of the tightergeometries. The increase in the maximum allowed diesize is represented by the factor S. For simplicity, weassume a square die and “die size” represents one lin-ear edge of the die. Table 2(b) summarizes the scalefactors and typical values. These typical values showa 29% annual reduction in CPF, a 4x increase in func-tions over a 3 year period, which is consistent withMoore’s Law1, 2 and the ITRS 20053.

Such a scaling methodology has been reported byIntel for their 80x86 microprocessors. Figure 5 showsthe migration of the 8086, 80286 and the 80486

Figure 4 (a) “Linear Shrink” from technology T1 to T2 and(b) “Re-design”

Table 2 (a) Summary of scale factors for a “Linear Shrink”

Table 2 (b) Summary of scale factors for “Re-Design”

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TECHNICAL ARTICLESprocessors with increasing transistors per chip6. Forexample, in 1989 the 8086 and 80286 microprocessorsfit into an area that was a fraction of the area in pre-vious technology generations. Then the 80486 wasintroduced in the new node with a larger die size and4x the number of transistors of the previous proces-sor in the previous node.

5. Die Cost Reduction by Increasing Wafer SizeThe industry has successfully increased wafer size7

from 50mm (2”) to 300mm (12”) as shown in Figure6. The wafer diameter steps result in either a 1.33x ora 1.5x diameter ratio versus the previous size. Anincreased number of gross die per wafer results fromthe use of larger diameter wafers, as shown in Figure7. The available silicon area is either 1.78x or 2.25xfor the two different diameter ratios. The actual ratioof GDPW is generally higher and is a function of thedie size, as shown in Figure 8. This is due toimproved optimization of die-stepping algorithms tomaximize the number of full die. Larger diameterwafers also allow a reduction of the number of partialdie around the perimeter of the wafer; this effect ismore dominant for larger die sizes. Manufacturing onlarger diameter wafers offers an improved economyof scale.

The use of larger diameter wafers does increasewafer cost. However, we will show that there is areduction in the die cost. Early on in the introductionof a new wafer size, a 70% increase in wafer cost isreasonable4. In mature production the cost to processa larger diameter wafer could increase 30%.

where W is the relative wafer cost for the larger waferand g is the relative GDPW

As mentioned earlier, the range of values for W are1.3-1.7 and for g are 1.8-2.5. Therefore, the range ofrelative die cost is 0.5-0.9, a 10-50% die cost reductionwhen using larger diameter wafers.

A couple of examples for a mature and a relativelynew technology are shown here:

a. For a 10mm die in 0.8um technology processedon 150mm and 200mm wafers, W=1.35, g=1.95.Therefore, die cost on 200mm wafers = 69% ofdie cost on 150mm wafers.

b. For a 10mm die in 130nm technology processedon 200mm and 300mm wafers, W=1.75, g=2.45.Therefore, die cost on 300mm wafers = 71% ofdie cost on 200mm wafers.

6. Optimizing the Die Size and PackingDensity per ChipSelecting the optimum packing density and the diesize becomes a challenge in this dynamic industry.We have developed models to predict the optimumdie size and functions per chip. In Figures 9 and 10we show examples of the cost/gate for 90nm and180nm technologies as a function of die size and mil-lions of gates per chip. The curves have a U-shape. Ifthe die size is too small the cost is dominated by the

Figure 5 Technology scaling methodology reported byIntel

Relative Die Cost on larger diameter wafers = W/g,

Figure 6 Silicon wafer diameter increase over time

Figure 7 Increased gross die from a wafer diameterincrease in the same technology

Figure 8 GDPW increase as a function of die size for twodifferent wafer size transitions

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overhead of the input/output structures, the scribelane, etc. If the die size gets too big, the cost per gateincreases due to the increased complexity. For sim-plicity, gate count is assumed here to be an equiva-lent 2-input NAND gate count. Each equivalent gateuses four transistors. The optimum gate density andcost per gate can be converted to transistor densityand cost per transistor. The actual transistor count perchip increases rapidly as larger amounts of memory isincluded on the die. For reference, one of Intel’s Pen-tium processors is reported with 55M transistors (14Mequivalent gates) in a 90nm technology4. Referring toFigure 10, this data point will be considered reason-ably well optimized in our analysis, since it is locatednear the minimum, just at the cusp of the steep slopeand marked by the arrow. The shape of the curve isaffected by parameters such as wafer cost, defect den-sity, physical and electrical design rules, design tools’packing efficiency.

7. Current TrendsThis paper has focused on providing a historical per-spective of business aspects of scaling. While adetailed discussion of the current status of technicaland business challenges is beyond the scope of thispaper, we will provide some highlights of currenttrends in this section.

a. The cost of wafer fabrication facilities and equip-ment, masks and chip design have all escalatedsignificantly over the years. Finding solutions to

technical challenges at the 32nm node willrequire ever increasing capital and manpowerinvestments.

b. Manufacturing entities have worked diligently toaccelerate the manufacturing and defectivitylearning curves.

c. Creative co-design of process and design consid-erations has been called for by many authors10

and are being implemented to manage chal-lenges such as increased leakage and standbypower.

d. New product introductions on the 65nm tech-nology node have been made at leading edgeusers in the 2005 time frame; the cross-overpoint varies but is expected to be in 2007. Leadproducts on 45nm will likely be announced in2007 with a cross-over in 2009. These timetablesindicate a less than 3 year cycle for the intro-duction of new technology nodes.

e. As in the past, technical solutions for the nexttechnology (32nm), e.g. the use of double-expo-sure lithography, will add significantly to capital,process development and therefore wafer cost.The author is confident that the industry will finda new manufacturing and design optimizationpoint that will allow introduction of new prod-ucts cost-effectively at this node.

f. The increasing cost of wafers, masks and designrequire users to very carefully assess the selectionof the proper technology for their products. Thetrend is towards the use of leading edge technol-ogy nodes only for products with very high vol-umes, a compelling technical argument and aclear value proposition.

8. SummaryThis paper has provided a simplified view of thebusiness aspects of scaling and technology migra-tions that have been key to sustaining a phenomenalreduction in CPF for integrated circuits. Althoughtrends such as the increasing cost of wafer fabs,masks and the increasing cost of complex designsindicate a possible slow down of the implementationof new technologies, the industry marches onward.The industry has demonstrated resilience in findingsolutions to challenges. New technologies are stillbeing introduced at a feverish pace allowingincreased packing density, reduced CPF andimprovements in performance.

9. AcknowledgementsThe author wishes to thank Behrooz Abdi, Bill Bider-mann, Mung Chen, James Clifford, Brian Henderson,Professor Dave Hodges, Merrill Hunt, Matt Nowakand Ian Young for reviewing the manuscript andoffering their valuable suggestions.

Figure 9 Cost per gate as a function of die size for 90nmand 180nm technologies

Figure 10 Cost per gate as a function of packing densityfor 90nm and 180nm technologies

cent

s/KG

ates

cent

s/KG

ates

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10. References1. G.E. Moore, “Progress in Digital Electronics”,

1975 IEDM, pp11-13.2. G.E.Moore, “No Exponential is Forever; but “For-

ever” can be delayed”, ISSCC 2003, Paper 1.1.3. International Technology Roadmap for Semicon-

ductors 2005, http://public.itrs.net4. IC Knowledge, www.icknowledge.com 5. W.Haensch, E.Nowak, R.H.Dennard, et. al., “Sili-

con CMOS Devices beyond scaling”, IBM J. Res.and Dev., Vol. 50, April/May 2006.

6. P. Gelsinger, P. Gargini, G. Parker, A. Yu, “2001:A Microprocessor Odyssey”, published in “Tech-nology 2001”, MIT Press, pp. 95-113, July 1992.

7. P. Gelsinger, “Moore’s Law – The Genius LivesOn”, IEEE SSCS Newsletter, September 2006.

8. R.C.Leachman, “Yield Modeling”, http://www.ieor.berkeley.edu/~ieor130/yield_models.pdf

9. M.Sydow, “Compare Logic-Array To ASIC-ChipCost per Good Die”, Chip Design Magazine, Feb-ruary/March 2006.

10. T.C. Chen, “Where CMOS is Going: Trendy Hypevs. Real Tecdhnology”, ISSCC 2006, Paper 1.1.

About the AuthorRakesh Kumar is President of TCX,a consulting services company. Heis also CEO of ei2, a fabless productintegration company. Previously hewas VP & GM of the worldwide Sil-icon Technology business unit atCadence Design Systems and Tality.During his 32 years of industry

experience Rakesh has also been at Unisys andMotorola where he held various technical and man-agement positions with increasing responsibility. Hehas numerous publications and patents to his credit.Dr. Kumar is on the AdCom of the IEEE Solid StateCircuits Society and serves as its Treasurer. He haschaired and served on the Steering committee of theIEEE Custom IC Conference for fourteen years.Rakesh received his Ph.D. and M.S. in ElectricalEngineering from the University of Rochester in 1974and 1971 respectively. He received his B. Tech. inElectrical Engineering from the Indian Institute ofTechnology, New Delhi in 1969. [email protected]

A Perspective on the Theory of MOSFET Scalingand its ImpactTak H. Ning, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, [email protected]

It was certainly the best of times to work on silicon inte-grated-circuit technology when I joined IBM Researchin 1973. My first assignment was to study the so-called

hot-electron effects in MOSFET’s. At the time and formany years that followed, hot-electron effects severelylimited the progress of MOSFET technology, particularlyCMOS technology. The reasons for this will be explainedlater. In the subsequent three decades, I have had theopportunity to participate in the evolution of silicon inte-grated-circuit technology and witness the tremendouslyrapid rise and fall of a couple of the platform technolo-gies. One of the most significant milestone events alongthe way was the establishment of a theory for scalingdown the physical dimensions of MOSFET’s, published in1974 [1]. In this paper, I provide a brief personal perspec-tive on the significant role this theory played in the evo-lution of silicon integrated-circuit technology.

From the very beginning, the basic idea of integrat-ed-circuit technology has been to employ advancedlithographic and process techniques to make eversmaller devices and to increase the chip-level integra-tion. The technology to produce stable n-channelMOSFET’s was developed in IBM in the 1960’s [2].Using n-channel instead of p-channel, the performanceof MOSFET’s was improved by about a factor of two.In 1963, CMOS circuits were reported with the promise

of negligible standby power dissipation [3]. So, whenthe theory of MOSFET scaling [1] was published, theprospect of MOSFET circuits with very low standbypower dissipation, that are both simple to make andscaleable, seemed quite realizable. The theory pre-scribed some simple rules to follow in scaling anddescribed the expected resultant circuit benefits, as list-ed in Table I. To first order, the expected drain currentequation for the scaled MOSFET is given by

(1)

where Id (reference) is the drain current of the refer-ence MOSFET and Id (scaled) is the drain current ofthe scaled MOSFET.

TABLE I: Rules and results for circuit performance in scal-ing MOSFET by a factor κ [1]

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However, a typical MOSFET in production in theearly 1970’s had a gate oxide of about 100 nm inthickness, a channel length of about 5 μm, and apower supply voltage of 5 V or larger. As explainedin a paragraph below, the performance of these high-voltage MOSFET circuits was simply much too inferi-or compared to the performance of silicon bipolar cir-cuits. Bipolar was the high-performance technology,the backbone of computers and high-performanceelectronics, while MOSFET was the low-cost technol-ogy for applications where performance was notrequired.

The benefit of applying the scaling theory to MOS-FET technology, especially to CMOS technology,seemed obvious and exciting. If we just follow therules and scale the CMOS devices by a factor of ten,the resulting circuits will be ten times faster. For morethan two decades following the publication of theMOSFET scaling theory, CMOS engineers focusedmuch of their efforts in scaling down the physical sizeof CMOS transistors. However, instead of scalingdown the power supply voltage, they left it at 5 volts,which was the standard for practically all integratedcircuits. There was simply little or no market for inte-grated-circuit chips using non-standard voltages. Suchconstant-voltage scaling of MOSFET quickly ran intotwo major difficulties, namely the power density of aCMOS circuit in switching increased very rapidly by afactor of κ2 to κ3, and the fast increasing electric fieldcaused hot-electron and oxide reliability problems.Power density was not much of a problem becausethe integration level was still relatively low so that thetotal chip power was readily manageable. However,device engineers had to devote much effort to devel-op practical techniques, such as LDD (Lightly DopedDrain) [4], in order to bring the reliability issues undercontrol. Controlling hot-electron effects added signifi-cant cost to the CMOS chips.

Scaling at constant voltage severely limited the per-formance potential of CMOS as well, particularly fordriving long wires and driving signals off chip. To firstorder, the performance for driving a capacitance load Cis CV/I, where V is the voltage swing and I is the cur-rent delivered by the transistor. For bipolar circuits, V istypically about 200-400 mV for driving on chip, andabout 800 mV for driving off chip. Thus, at 5 V, the volt-age swing of CMOS circuits was much too large forhigh-performance applications. Besides, in the late1970’s, bipolar engineers also developed a theory forscaling bipolar circuits [5] which guided the rapiddevelopment of faster and lower-power bipolar circuits.For more than twenty years after the MOSFET theorywas published, CMOS remained a low-cost technologylimited to applications where performance was not animportant factor. When performance was needed,scaled advanced bipolar technology was used.

The opportunity for scaled CMOS to break intohigh-end applications came when the industryworked together to established voltage standardsbelow 5 volt. Once it was recognized that CMOS atless than 5 V could be accepted by the market, engi-neers wanted to reduce CMOS voltage as fast as pos-sible. As an illustration of this “lower is better” mindset at the time regarding CMOS voltage, Figure 1 is aplot of three CMOS voltage roadmaps proposed in theearly and mid 1990’s. At the first semiconductor tech-nology roadmap workshop in 1992 [6], there was aconsensus that CMOS power supply voltage wouldnot be below 2 V until 2004. In 1995, it was proposedthat leading CMOS should have a power supply volt-age of 1.8 V in 1999. By the time the 1997 roadmap[7] was prepared, it was proposed that the voltage in1999 should be 1.5 V instead. For several years now,advanced CMOS microprocessor chips use a powersupply voltage of 1 to 1.2 V.

Reducing CMOS voltage makes the fabricationprocess for scaled CMOS less complex and hencelowers the cost. For one thing, process steps used toimplement LDD can be omitted. With the introductionof scaleable technology elements such as shallow-trench isolation and dual-poly gate (i.e., p+-polysili-con gate for p-FET and n+-polysilicon gate for n-FET)to the fabrication of reduced-voltage CMOS circuits,as illustrated in Fig. 2, CMOS technology becamereadily scaleable [8]. The same device schematic inFig. 2 was used to represent several generations ofCMOS technology, making the migration of devicesand circuits from one generation to the next relative-ly simple to implement, and exhibited more pre-dictable results. For the decade that followed, therewas accelerated progress throughout the semiconduc-tor industry scaling such a CMOS device structure toever smaller dimensions, as evidenced by the acceler-ated rate at which CMOS power supply voltage wasreduced.

With CMOS channel lengths scaled to around 100nm and voltages reduced to around 1 volt, the per-formance of digital CMOS became comparable to that

Fig. 1. Proposed power supply voltage trends for CMOS.(After references [6] and [7])

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of digital bipolar. The era of bipolar for high-per-formance digital circuits came to an end when IBMdecided to replace bipolar by CMOS as the technolo-gy for mainframe computers. At first, the CMOS main-frame processors was not really as fast as the bipolarversions, but the highly scaleable properties of CMOSallowed CMOS processors to catch up in just a fewyears, as shown in Fig. 3 [9]. Since then, CMOS hasbecome unquestionably the technology for all digitalapplications.

Every technology has its limits, and CMOS is noexception. The fact that the CMOS device structuredepicted in Fig. 2 is highly scaleable was both goodnews and bad news. The good news was that itbecame relatively straight forward to establish anindustry-wide technology roadmap, and every leadingsemiconductor company wanted and was able to beatthe roadmap targets. Again, this is evidenced by theincreasingly aggressive rate of CMOS power supplyvoltage reduction illustrated in Fig. 1. System devel-opers and consumers certainly benefited tremendous-ly from the faster-than-projected rate of CMOS scaling.The bad news was that the industry also reached thelimits of CMOS scaling at rate faster than anticipated.

Two of the limits of CMOS scaling were reached in the

early 2000’s. These limits are the high tunneling currentthrough the thin gate insulator and the high device offcurrent. That we reached these scaling limits so soonshould come as no surprise. In the case of gate insulatorthickness, it was shown that scaling CMOS to the regimewhere gate tunneling current is appreciable has littleimpact on the device characteristics [10]. Today, leading-edge CMOS microprocessor chips employ gate oxide lay-ers as thin as 1 nm, which is pretty much the limit set byacceptable gate tunneling current. The limit due to highdevice off current has been looming there since the verybeginning, as shown in Eq. (1). In Eq. (1), the factor[Vg − Vt − Vd /2]/κ scales only if the threshold voltageVt is scaled. If Vt is not scaled, this factor is smaller thanexpected from scaling and the resultant device speed isless than expected from scaling. As the CMOS voltagewas scaled below about 2 V, device designers had toreduce Vt in order to achieve the intended device per-formance targets. Reducing Vt has the effect of increasingthe device off current, as illustrated schematically in Fig.4. Reducing Vt repeatedly for several generations has leadto a dramatic increase of CMOS device off current.Today, CMOS circuits no longer have negligible standbypower dissipation. Instead, the performance of leading-edge CMOS logic chips is limited by a combination ofdevice off current and gate tunneling current.

Without the ability to reduce gate insulator thicknessand device threshold voltage any further, CMOS devicedesigners find it difficult to increase device speed by theusual means of scaling device channel length. Today,device engineers focus primarily on technology innova-tions for continued device performance improvementfrom one generation to the next. The most notable inno-vations that have been successfully developed and putinto volume manufacturing to date include using silicon-on-insulator (SOI) as the wafer substrate [11], usingembedded SiGe in the source/drain region of p-channelFET’s to improve hole mobility [12], and using highly-stressed dielectric films on top of n-channel FET’s toimprove electron mobility [13]. Each of these innovationsoffers incremental but appreciable improvements to the

Fig. 2. Schematic of a CMOS device structure that wasscaleable to deep sub-micron dimensions. (After Davari, [8])

Fig. 3. IBM S/390 mainframe uniprocessor performance.(After Rao et al., [9])

Fig. 4. Schematic showing the increase of device off currentwhen Vt is reduced, where Vt2 < Vt1.

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speed and/or power dissipation of CMOS circuits. Cir-cuit designers can always tradeoff the speed improve-ment for lower power dissipation. Judging from the pre-sentations at device conferences, it is reasonable toexpect a steady stream of additional innovations forenhancing CMOS performance to become ready formanufacturing in the next decade.

Nowadays, the concern is not the lack of innovativeideas for improving CMOS performance, but the timeand cost needed to bring a specific innovation from itsconcept stage to volume manufacturing. Most majorinnovations take 10 ±5 years from concept to manufac-turing, which is long compared to the 2 to 3 years toscale CMOS from one generation to the next (the lineardimension is reduced by a factor of 0.7 and the circuitdensity is improved by a factor of 2 each generation).Going forward, it is important that circuit and systemdesigners recognize this paradigm shift in CMOS devel-opment and plan their product strategies accordingly.

Thanks to the insights provided by the simple theoryof MOSFET scaling, we have been able to make unprece-dented progress in advancing CMOS technology over aperiod of about thirty years. In the process, we have runthe course of CMOS development guided by the theoryof scaling. We have left the period when leadership inCMOS technology was judged by being the first to scaleCMOS to the next dimensional node and entered a peri-od when leadership is judged more by being able toenhance chip-level performance through innovation.

References[1] R.H. Dennard, F.H. Gaensslen, H.-N. Yu, V.L. Ride-

out, E. Bassous, and A.R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physicaldimensions,” IEEE J. Solid-State Circuits, Vol. SC-9,pp. 256- 268 (1974).

[2] An account of the challenges and major milestonesin the development of n-channel MOSFET can befound in the article by E.W. Pugh, D.L. Critchlow,R.A. Henle, and L.A. Russell, “Solid state memorydevelopment in IBM,” IBM J. Res. Develop., Vol. 25,pp. 585-602 (1981).

[3] F.M. Wanlass and C.T. Sah, “Nanowatt logic usingfield-effect metal-oxide semiconductor triodes,” IEEEISSCC Technical Digest, pp. 32-33 (1963).

[4] S. Ogura, P.J. Tsang, W.W. Walker, D.L. Critchlow,and J.F. Shepard, “Design and characteristics of thelightly doped drain-source (LDD) insulated gatefield-effect transistor,” IEEE Trans. Electron Devices,Vol. ED-27, pp. 1359-1367 (1980).

[5] P.M. Solomon and D.D. Tang, “Bipolar circuit scal-ing,” IEEE ISSCC Technical Digest, pp. 86-87 (1979).

[6] Semiconductor Industry Association, 1992 Semicon-ductor Technology Workshop, Working GroupReport, published in 1993.

[7] The 1994 and 1997 National Technology Roadmapsfor Semiconductors, published by Semiconductor

Industry Association. [8] B. Davari, “CMOS technology scaling, 0.1 μm and

beyond,” IEDM Tech. Dig., pp. 555-558 (1996).[9] G.S. Rao, T.A. Gregg, C.A. Price, C.L. Rao, S.J. Repka,

“IBM S/390 parallel enterprise servers G3 and G4,”IBM J. Res. Develop., Vol. 41, pp. 397-403 (1997).

[10] H.S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S.Nakamura, M. Saito, and H. Iwai, “Tunneling gateoxide approach to ultra-high current drive in small-geometry MOSFET’s,” IEDM Tech. Dig., pp. 593-596(1994).

[11] G. G. Shahidi, A. Ajmera, F. Assaderaghi, R. J. Bolam,E. Leobandung, W. Rausch, D. Sankus, D. Schepis,L. F. Wagner, K. Wu, and B. Davari, “Partially-deplet-ed SOI technology for digital logic,” IEEE ISSCCTechnical Digest, pp. 426-427 (1999).

[12] S. Thompson, N. Anand, M. Armstrong, C. Auth, B.Arcot, M. Alavi, P. Bai, J. Bielefeld, R. Bigwood, J.Brandenburg, M. Buehler, S. Cea, V. Chikarmane, C.Choi, R. Frankovic, T. Ghani, G. Glass, W. Han, T.Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S.Joshi, C. Kenyon, J. Klaus, S. Klopcic, J. Luce, Z. Ma,B. Mcintyre, K. Mistry, A. Murthy, P. Nguyen, H. Pear-son, T. Sandford, R. Schweinfurth, R. Shaheed, S.Sivakumar, M. Taylor, B. Tufts, C. Wallace, P. Wang,C. Weber, and M. Bohr, “A 90 nm logic technologyfeaturing 50 nm strained silicon channel transistors, 7layers of Cu interconnects, low-k ILD, and 1 μm2SRAM cell,” IEDM Tech. Dig., pp. 61-64 (2002).

[13] Most dielectric films are of high stress as deposited.Until recently, device engineers worked hard to min-imize the stress in the deposited films to avoid pos-sible deleterious effects such as wafer bowing andfilm cracking and/or peeling. To day, device engi-neers work hard to increase the stress in a control-lable manner to increase n-FET drive current.

About the Author Tak H. Ning received his Ph. D. degreein physics from the University of Illi-nois at Urbana-Champaign in 1971. Hejoined IBM Thomas J. WatsonResearch Center in 1973. His earlytechnical contributions were in under-standing hot-electron effects and inadvanced bipolar technology. From

1982 to 1991, he managed the silicon devices and tech-nology department in IBM Research, contributing to andleading the research effort on CMOS, bipolar, DRAM,EEPROM and SOI. He was appointed an IBM Fellow in1991. In recent years, he has focused his technical activ-ities on understanding the limits of CMOS as well as theopportunities beyond CMOS. He received the 1989 IEEEElectron Devices Society J.J. Ebers Award and the 1991IEEE Jack A. Morton Award. He is a member of theNational Academy of Engineering, and a fellow of theIEEE and of the American Physical Society.

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The largest question in the early to mid 70’s washow far silicon could go in competition againstnewly emerging materials and devices such as

magnetic bubble memory, Gunn effect functionaldevices, integrated injection logic, GaAs MESFET inte-grated circuits, and Josephson junction logic.

The typical roadmap of major semiconductormanufacturing companies in those days was suchthat (1)Silicon based integrated circuits would loseposition by the mid 80’s except for silicon on sap-phire, SOS, based ones, (2)GaAs integrated circuitswould become the dominant design for high speedand /or low power applications, (3) Optical lithog-raphy would surrender its position against eitherelectron beam lithography or soft X-ray lithogra-phy, (4) Geometry shrink, however, may proceeddespite challenges around. In other words, no onewas even close to predicting what we are seeingtoday. In fact, many central research organizationsin industry decided that silicon would not be a rightsubject any more for advanced research, and eithershut down silicon research activities or transferredthe division to their operation divisions.

In the middle of the 70’s, Japan launched a largenational project, called the “VLSI project” which wasinstigated by the announcements made by Bell Lab-oratories for electron beam direct writing lithogra-phy, and by IBM demonstrating 8kbit dynamic ran-dom access memory at 1um minimum geometry,both of which were supposed to provide solutionsfor future computing systems in the mid 80’s andbeyond. The project consisted of Fujitsu, Hitachi,Mitsubishi, NEC and Toshiba, and had a centralizedresearch center for basic research to which all mem-ber companies sent researchers, and also two branchlaboratories for Fujitsu-Hitachi-Mitsubishi group andNEC-Toshiba group focused on more developmentoriented work. Two government laboratories, Elec-trotechnical Laboratory and NTT Laboratories werealso involved.

Moore’s Law was already becoming popular, butwhen it came to any methodical approach to makeit happen rather than a religious belief, there was notmuch idea which was viewed credible enough.Japan’s VLSI project had both logic and memory asthe targeted areas with MOSFETs, bipolar such asECL/CML, and compound semiconductor devices.The tool side was even broader, covering from opti-cal, electron beam and X-ray lithography, plasma

processes and a variety of thermal processes. Thisalmost implied that we needed to look around for360 degree instead of any particular focus. Also, itwas the time when layout design was viewed assuch a serious bottle neck that almost 90% of theworld population might need to become layoutdesigners and technicians by the end of the 80’s.Fortunately, many IEEE technical conferences, suchas IEDM and ISSCC were quite interesting in termsof a large variety of research results presented, butwhen it came to the future of silicon integrated cir-cuits, general perception was to seriously stagnant ataround 1um geometry.

Dr. Robert Dennard’s paper in 1974(1) appeared inthe IEEE Journal of Solid State-Circuits. As the firstproposal for the scaling principle, it looked, at firstglance, rather simple and did not attract much atten-tion, at least I remember from a little corner of Toshi-ba Research and Development Center where I was incharge of SOS microprocessor technology and alsoinvolved in Japan’s VLSI project looking into shortchannel MOSFET technology research. However, itdid not last long before more people started under-standing what it possibly would imply to the worldof MOS integrated circuits. However, it needed towait for CMOS taking the “dominant” design positionin the mainstream of integrated circuits before thescaling theory became the physics based guidingprinciple for Moore’s Law to continue. Without scal-ing theory, I doubt that Moore’s Law could have sur-vived for more than three decades. It was the firstattempt to couple geometry shrink with other impor-tant factors such as power-delay products, on-chipinterconnect performance as well as integration den-sity. The magic number alpha of “1.4” or 0.7x shrinkover all device parameters, as shown below becamea general guideline from one technology node to thenext technology node since then.

dimensions tox, L, W 1/αdoping α

voltage 1/αintegration density α2

delay 1/α2

power dissipation/Tr 1/α2

It is indeed difficult to see any other such exam-ple in which one set of rather simple principles cansurvive for such a long time. I would, however, say

Impact Of Scaling and the Scaling DevelopmentEnvironment Yoshio Nishi, Department of Electrical Engineering Center for Integrated Systems,

Stanford University, [email protected]

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that this has survived because of its simplicity andtransparency. There have been enormous impactscoming from the scaling principle, not only in theway we design devices and develop technology tomeet requirements, but also on the semiconductordevice manufacturing industry as well as manufac-turing equipment business by providing clear andeasily understandable directions with investmenttiming. The scaling principle and Moore’s Lawhave been inseparable in terms of providing a driv-ing force to technology research and developmentand justifying huge investment for more advancedinfrastructures for manufacturing. It was becausescaling continuously provided 2x density of inte-gration at reduced cost per gate or bit with betterperformances to integrated circuits chips designedand manufactured with more advanced technologyin the past three decades. It should not be forgot-ten that scalable design library has become one ofthe prerequisites for the design community, whichcut down design cost increase coupled with enor-mous progress made in computer aided designfrom logic design down to layout design capabili-ty.

Today we are still thinking with the scaling prin-ciple even though the scaling factor could be quan-tized due to actual size approaching the integertimes an atomic size, and performance would be inthe same way as somewhat quantized by nature.This would force us to rethink scaling not just forthe geometry scaling, but also consider a variety ofnew materials to keep the pace of improvementboth in performance and cost. As we see the era for“nanoelectronics” either evolutionary and/or revolu-tionary challenges, this is a great moment at whichwe all should appreciate what Dr. Dennard hasgiven to all of us.

References[1] R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L.

Rideout, E.Bassous and A. R. Le Blanc, “Designof Ion-Impanted MOSFET’s with Very SmallPhysical Dimensions,” IEEE J. Solid-State Circuits,SC-9, p. 256 (1974).

About the AuthorYoshio Nishi is a Professor in theDepartment of Electrical Engineering(research) and in the Department ofMaterial Science and Engineering atStanford University He also serves asDirector of Stanford NanofabricationFacility of National NanotechnologyInfrastructure Network of US, and

Director of Research of Center for Integrated Systems.Professor Nishi Received a BS in material science and

PhD in electronics engineering from Waseda Universityand the University of Tokyo, respectively.

He joined Toshiba R&D in the areas of research for semi-conductor device physics and interfaces mostly in silicon,resulting in discovery of ESR PB Center at SiO2-Si interface,the first 256bitMNOS non-volatile RAM, SOS 16bit micro-processor and the world first 1Mb CMOS DRAM. He wasalso involved in MITI VLSI project for ultra short channelMOS device technology research from 1976-1981.

He moved to Hewlett-Packard in 1986 as the Directorof Silicon Process Lab, followed by establishing ULSIResearch Lab as the Founding Director.

In 1995 he joined Texas Instruments, Inc as Senior VPand Director of Research and Development for semicon-ductor group, and implemented new R&D model for sil-icon technology development, followed by establishingthe Kilby Center.

In May, 2002, he became a faculty member of StanfordUniversity. His research interests cover nanoelectronicdevices and materials including metal gate/high k MOS,device layer transfer for 3D integration, nanowire devicesand resistance change non-volatile memory materials anddevices. He published more than 200 papers includingconference proceedings, and co-authored/edited 9 books.He holds more than 70 patents in the US and Japan.

During the period of 1995-2002 he served SRC andInternational Sematech as Board member, NNI Panel,MARCO Governing Council. etc. Currently he is an asso-ciate member of the Science Council of Japan.

Dr. Nishi is a Fellow of IEEE, a member of Japan Soci-ety of Applied Physics and the Electrochemical Society.Recent awards include the 1995 IEEE Jack MortonAward, and the 2002 IEEE Robert Noyce Medal.

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AbstractThe electronics industry often thinks of scaling in onlyone dimension: making things smaller. But it reallyscales in two directions, both smaller and larger, andthe semiconductor industry has employed both, allow-ing roughly 40 years of exponential progress in thecost reduction of electronic functions. The future ofthe semiconductor industry holds daunting challenges,including some related to scaling things larger, but ahistorical view shows this has always been true.

IntroductionThe topic of scaling usually invokes pictures of eversmaller features, transistors and wires, packing evermore functions onto densely packed circuit boards.On the other hand, fabs, tools, teams and complexi-ty have been increasing in size at nearly the sameexponential pace. It is the combined effect of thesetwo trends, smaller features working to solve largerproblems, that has allowed rooms full of electronicequipment to shrink into slivers of silicon, at a frac-tion of the cost, operating at a fraction of the power,and available to anyone, anywhere in the world.However, just as the amount of silicon required toperform a function has gotten smaller, the number ofusers and their demands has scaled up. A moderndata center is capable of serving millions instead offew, and of solving bigger problems with evergreater precision.

Looking back at the progress of integrated circuitscaling, it is easy to forget that it was never obvioushow to progress beyond the next two generations.The few that tried to extrapolate progress beyond thiswindow, or proclaimed that the end of scaling wasnear, were mostly proven wrong. With that historicallesson in mind, the following sections look at therecent past and near term future of feature scaling,resource scaling, and application scaling.

Scaling Transistors and InterconnectInsights into the scalability of the physics of fieldeffect devices unleashed a steady and rapid reduc-tion in feature sizes. Under conditions of constantelectric fields, smaller devices switch faster at lowerpower. Density increases quadratic, power dissipa-tion reduces cubic, and speed increases linearly. Ide-ally then, scaling allows more things to happenfaster at the same energy cost, and is economicallyattractive if the manufacturing cost per square areagrows only modestly. Specifically, in the past decadeor so, CMOS has improved density at each node by2x, increased performance more than 20%, while

limiting increases in the final cost per wafer to lessthan 30%. The compound effect of a new node everytwo (early on, three) years has brought mainframecapability down to the package of a cell phone.We’ve moved from megawatts to milliwatts, fromMHz to GHz, from kilobits to gigabits, and so on.Most importantly, all while moving from millions ofdollars to just a few dollars .

This progress wasn’t obvious at the outset. If wehad known then what is possible now, we wouldhave done it faster. Every time a new node is con-templated, lithography capability is two generationsaway from physical or practical (i.e. economic) lim-its. Today, the patterning process calls for 193nmimmersion lithography with various resolutionenhancements. Combining wavelength reduction,lens improvement, mask sophistication and resistenhancement now allows printing of features with aminimum pitch of lines and spaces near 125nm.Future improvements in numerical aperture (NA) to1.35 are expected to bring this down to sub-80nmfor regular arrays. Printing even smaller featureswith higher transistor density may require newcapability such as Extreme UV, which requires allreflective optics and a vacuum toolset. Serious chal-lenges also need to be overcome with regard tosource power and mask capability. The perennialalternative, direct-write e-beam, may have applica-tion in very low volume product or as mask writer,using a massively parallel beam to overcome thecharge-throughput limitations of a single beam. Inall cases, the mask plays a critical role, and hasbecome the key concern for designers.

Masks are no longer “black and white” but theirfeatures manipulate a complex two-dimensional con-trast image through focus and exposure windows.This specialty of Resolution Enhancement Technology(RET) has resulted in tricks like Sub Resolution AssistFeatures (SRAFs) for vias, model-based Optical Prox-imity Correction (OPC), and will likely embracemodel-based placement for SRAFs and dual-pattern,dual-etch for better poly and contacts definition. Asone might imagine, these techniques have greatlycontributed to the cost of masks, and hence productdesign. Scaling down has meant scaling up.

While the horizontal dimensions have becomesmaller than the gate dielectric of the past, the tech-nology has reached the practical limits of oxidethickness reduction. While dielectric improvementsusing Nitrogen and/or Hafnium may extend theeffective thickness, it is likely limited to at most afactor of two. Additional benefits may be gained

It’s All About ScaleHans Stork, Texas Instruments, Inc., [email protected]

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TECHNICAL ARTICLES


from metal gate electrodes by eliminating the deple-tion layer on the top side of the dielectric. Anymobility degradation because of additional scatter-ing will be overcome by the significant mobilityenhancements due to strain. In fact, the successfulapplication of strain is a superb example of unan-ticipated improvements that work precisely becauseof the new small scale of the devices. Many of theeffects below 100nm introduce problematic behav-iors: tunneling contributes to leakage in thindielectrics and high field junction profiles; line edgeroughness in resists patterns results in excessiveshort channel effects; and grain–boundary and side-wall scattering increase the resistivity of copperwires with very small cross-sections. Low resistanceis critical to high efficiency use of the device prop-erties. Contact and via resistance are thereforebecoming a bigger concern going forward as theirproperties scale non-linearly in the wrong direction.And, as many now know, the capacitance of theinterconnect is approaching its physical limits aswell. The low dielectric constant materials thatreduce the k-value from 4 for silicon dioxide, toaround 2.5 for heavily Carbon mixed compounds,are mechanically weak and can interfere with pack-aging robustness, as well as cause electrically lowerbreakdown voltages.

All these process and materials changes haveallowed density scaling to continue at its historicalpace of 2x every generation. The price has not onlybeen more complexity, but also the introduction ofseveral design tradeoffs. Design innovations nowneed to limit static and dynamic power dissipation,tolerate escalating parameter variations, maximizeincreasingly restricted layout options, and incorporateanalog and RF functions at the low voltages compati-ble with extremely small dimensions.

Scaling the ResourcesImmersion lithography allows for effectively shorterwavelength and a higher NA lens design to improvethe lithographic patterning pitch. A manufacturableimplementation requires cost effective throughput,defect density, and resist solution. The large increasein capital equipment cost consumes the largest frac-tion of the process cost budget. As is the case forevery process tool, to maintain cost effectiveness,high throughput/automation is required to offset theinitial capital outlays. But now the high volumecapability of each tool requires the fabs to be everlarger to avoid one-of-a-kind tool challenges. Inaddition, chips now may include over 10 layers ofinterconnect. While the process is repeatable, theinterconnect fraction of a fab is easily half the fabsize because of the multitude of tools. The explosionin process steps, represented typically by the num-

ber of mask layers has also increased rapidly. Thesize and cost of fabs has thus grown exponentially,each supplying an ever larger fraction of the market,and each generation requiring a larger investmentand higher market risk.

Resource demands have also rapidly grown on theproduct side. Thanks to the ability to yield hundredsof millions of transistors on a single die, design teamsfor chips are now equivalent to those that wererequired to build large computers. Product designsneed to comprehend everything from knowing thestrengths and limitations of the process, to definingand building the software infrastructure that supportsuch sophisticated systems-on-a-chip.

Scaling the ApplicationsAbsolute interconnect performance has become adominant speed limit and, consequently, variations inline-width and thickness add increasingly to thedesign margin. While many effects are systematic, thecomplexity of interconnect prevents a brute forcecomputational solution. This has become typical ofthe technical problems to be solved at the design andapplication level. Conceptually, the problem of opti-mizing interconnects to minimize delay and power isgoverned by simple physics. However, the sheer sizeof a problem like this, or that of RET or for that mat-ter, fab operations, is overwhelming. Not just for thedesign teams, but frequently for their computeresources as well. And finally, the challenge is notovercome by solving a steady state or exact condition.Parameters are not perfectly controlled, and it isbecomingly increasingly clear that comprehendingvariations is where the next breakthrough may beneeded. Nature gives us examples of how it has fig-ured out that designing with imperfect and infinitelyvariable components can be successful. Althoughhuman communication may be effective while beingimperfect, other communication or computation taskscannot tolerate any practical errors.

For example, encouraging progress by the EDAtool suppliers is trailing the needs for leading productdesigns. Integrating analog and RF functions inadvanced CMOS requires an architectural approach tomaximize the features of density and speed, ratherthan the precision of analog components.

SummaryOver the past 40 years the world has benefited fromexponential growth in the application of semiconduc-tors. Thanks to scaling transistor dimensions into thenanometer regime and scaling the manufacturingcapabilities to produce billions of individual chips, theindustry has achieved economies of scale that allowwhat was once mainframe capability to be affordableto everyone in the world in something as small as a

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TECHNICAL ARTICLEScell phone. With many fundamental physical scalinglimits still far away, this progress can and will contin-ue if demand for the applications supports theincreased investment necessary to get there.

About the Author Johannes M.C. (Hans) Stork is SeniorVice President and Chief Technolo-gy Officer of Texas InstrumentsIncorporated. As Director of the Sil-icon Technology Developmentorganization, Dr. Stork’s primaryresponsibilities are the developmentof advanced CMOS, packaging and

mixed signal process technologies. He joined Texas Instruments in September 2001,

after being the Director of the Internet Systems andStorage Lab at HP Laboratories, Hewlett-Packard from1999 until 2001. He had joined Hewlett-Packard in1994, holding the position of Director of the ULSIResearch Lab between 1995 and 1999.

Dr. Stork started his professional career in 1982at IBM's T.J. Watson Research Center as a researchstaff member in the bipolar technology and circuits

area. Starting in 1987 he led an exploratory devicesgroup which demonstrated record breaking SiGeHBTs. Hans was awarded two Outstanding Techni-cal Achievement Awards from IBM. He has writtenor co-authored nearly 100 cited papers and holdseleven US patents. He was elected IEEE Fellow in1994 for his contributions to SiGe devices andtechnology.

Hans has served on various conference and IEEEcommittees, including IEDM, VLSI, and BCTMbetween 1986 and 1996. Presently, Dr. Stork serves onthe Board of Directors of Sematech, and is chairmanof the Semiconductor Research Corporation (SRC)Board of Directors. He has been a member of the SIATechnology Strategy Committee since 1999.

In 2000-2001, he participated as a technical advisorto Government efforts on high performance comput-ing benchmarks and the national security issues ofInternet computing, and has recently been elected amember of the advisory committee for the EmergingTechnology Fund in the state of Texas.

Dr. Stork was born in Soest, The Netherlands, andreceived the Ingenieur degree in electrical engineeringfrom Delft University of Technology, Delft, The Nether-lands, and holds a PhD from Stanford University.

These three reprints show the difference between conference and journal reporting in the 1970s. When theconcept of scaling first saw the light of day at IEDM in 1972, only an abstract remained as an archive report.By 1973, the IEDM Digest provided a broader basic overview of Dennard’s report. Denard’s 1974 explana-

tion of scaling turned out to be the most cited article in the 51 year history of the JSSC, close to 700 times, accord-ing to the last count in 2005 by the independent citation report firm, Thomson ISI (sscs.org/jssc/topcites.htm). Themission of Journal of Solid-State Circuits is to provide the full archival source for important technical milestonesand fundamental explanations critical to the field.

Design of Micron MOS Switching DevicesR. H. Dennard, F. H. Gaensslen, L. Kuhn, H. N. Yu, IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.

Copyright 1972 IEEE. Reprinted with permission. Technical Digest. International Electron Devices Meeting, IEEE, 1972, pp. 168-170.

Modern photolithographic technology offers thecapability of fabricating MOSFET devices ofmicron dimensions and less. It is by no means

obvious that such small devices can be designed withsuitable electrical characteristics for LSI switching appli-cations. In this talk we will describe short-channeldevices (Leff ~ l µ) designed by scaling down largerdevices with desirable electrical characteristics. Later-al and vertical dimensions, doping level, and operat-ing voltages and currents are scaled in a self-consis-tent fashion. In this way small devices have been fab-

ricated without the usual deleterious effects associat-ed with short channels. The measured characteristicsof these short-channel devices and the larger devicesfrom which they were scaled will be compared.

The scaling procedure helps to better understandthe limitations of miniaturization of MOS devices. Sig-nificant problems are encountered when operatingvoltages become comparable to the band gap whichcannot be scaled within the silicon technology. Thesubthreshold characteristic of the device thenbecomes an important consideration.

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It has been shown previously that MOSFET switchingdevices can be scaled down to have one micron spac-ing between source and drain. In order to achieve

electrical characteristics suitable for dynamic memory andother digital applications, such miniaturized devices musthave reduced gate insulator thickness and junction depth,reduced operating voltages, and increased substrate dop-ing (1). The previously described one micron devicestructure is shown in Fig.1(a). With uniform substratedoping, a 200°A gate insulator is required to achieve thedesired control of the gate threshold voltage over theoperating range of the source and drain voltages.

Figure 1: MOS device designs for micron source-drainspacing. (a) Unimplanted design (b)Design with ionimplantation.

The present paper addresses improvements in thedesign of micron devices which can be obtained byusing ion implantation. The new n-channel design,which is shown in Fig. 1(b), uses a lighter doped sub-strate with a relatively heavy doped p-type region at thesurface between the source and drain. This implanted p-type region gives the desired threshold magnitude, andalso controls the extent of the source and drain deple-tion regions beneath the gate. With the gate turned off,these depletion regions must be kept separated so that

the surface potential in the channel region is indeedcontrolled by the gate. Merging of the depletion layersin the lighter doped substrate is prevented by using shal-low implanted source and drain junctions of depth com-parable to the p-type implanted region, and also bychoice of a moderate substrate doping level.

Figure 2(a) Vertical substrate doping profile, and (b) theresulting threshold versus source - substrate bias charac-teristic compared with alternate approaches. Experimentalconfirmation is shown by large dots.

The vertical-doping profile of the implanted regionbeneath the gate is shown in Fig. 2(a). Intuitively, it was feltthat a step function profile is preferable for the one micronimplanted device, and such a profile has been used fordesign purposes. In practice a single energy implantthrough the gate oxide with thermal treatment used in thesubsequent processing gives a reasonably good approxi-mation to the step function. Fig. 2(b) shows the gate thresh-old voltage (relative to the source) required to turn on thedevice as a function of the source - substrate potential usingthe one-dimensional model described in another confer-ence paper (2). The implantation profile was chosen to bedeep enough to prevent depletion layer punch through,and shallow enough to give the desired threshold voltagecontrol with a 350°A gate insulator thickness. Throughoutthe operating bias range (Vs-sub > 1), the gate field for thethreshold condition depletes the heavier doped implantedregion, and this depletion extends well into the lighterdoped substrate. This gives a threshold voltage relativelyindependent of source-substrate bias compared to a uni-formly doped substrate with the same 350°A oxide thick-ness. (See Fig. 2(b)). Compared to a non-implanted designwith a 200°A gate insulator, the new design has the sameslope in the threshold versus source bias characteristic, butthe overall threshold level is higher, which is desirable toprovide adequate design margins for circuit applications.

Ion Implanted MOSFET’s With Very Short ChannelLengthsR. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous , and A. LeBlancIBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.

Copyright 1973 IEEE. Reprinted with permission. Technical Digest, IEEE International Electron Devices Meeting, 1973, pp. 152-155.

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TECHNICAL ARTICLESThe one-dimensional threshold model is adequate for

devices with long source-drain separation, but in practicethe short devices of interest suffer a decrease in thresholdvoltage due to penetration of the drain field into the chan-nel region normally controlled by the gate. These shortchannel effects have been studied using a two-dimen-sional numerical model (3). The computed turn-on char-acteristic is shown in Fig. 3 for two values of source-drainspacing L in the range of one micron and for a relativelylong (10 micron) device, all normalized to the samewidth-to-length ratio (W/L=1). A drain voltage of 4 voltsis applied in all cases, which is the maximum consideredfor this design. The effect on the short devices is a shift ofthe characteristic along the gate voltage axis. This repre-sents a lowering of the threshold voltage. (Vt correspondsto a drain current of about 10-7 amps above which the cur-rent varies as (Vg-Vt)

2 rather than exponentially with Vg.Otherwise the device turns off properly.

Figure 3: Computed and experimental turn-on characteris-tics for different values of source-drain spacing, L.

Experimental devices have been fabricated to test thisdesign with various source-drain separations from 0.5 to10 microns. The p-type region was obtained with a 35KeV B11 implantation through the 350 Å gate oxide into2 ohm-cm substrates. The narrow silicon gates weredelineatead by contact printing from high-quality masks.Self-aligned source and drain regions were formed witha 100 KeV As75 implantation through the 350°A oxidelayer. The most significant thermal treatment after the B11

implant was eleven minutes at 1000°C. Good agreement was found between the threshold

characteristics of the experimental devices and thedesign predictions as shown in Fig. 2(b). The turn oncharacteristic of an experimental device of L=1.2microns displays the same behavior as the calculatedcharacteristic. (See Fig. 3). The variation of thresholdvoltage with source-drain spacing (at maximum drainvoltage) is shown in Fig.4 and compared with the cal-culated values from Fig. 3 (D=0.2µ).

Several design perturbations were simulated to testthe sensitivity to key parameters. One variable whichwas investigated was the use of a shallower implantedsurface layer, D=0.1 microns deep, with the dose adjust-ed to give about the same threshold value. Results forthis case are also shown in Fig. 4. The shallower

implant was found to be somewhat less effective inminimizing the threshold decrease for narrow sourcedrain spacing. The sensitivity to the source and drainjunction depth and to the background doping was alsoinvestigated, and the results are shown in Table I.These results show that there is little room for deviationfrom the original design and justify the original choices.

Figure 4. Experimental threshold voltage as a function ofsource-drain spacing compared to computed values.

In summary, ion implantation allows the fabricationof very small MOSFET switching devices with consider-ably thicker gate insulators. Capacitance from thesource and drain to the substrate and to the gate isreduced by more than a factor of two compared to con-ventional structures. Conversely, for a given thickness,smaller devices can be achieved using ion implantation.

AcknowledgementsWe wish to acknowledge the valuable contributionsof B.L. Crowder and F.F. Morehead, who providedthe ion implantations and related design information.Also important were the contributions of P. Hwangand W. Chang to two-dimensional device computa-tions. J. J. Walker and V. DiLonardo assisted with themask preparation and testing activities. The deviceswere fabricated by staff of the silicon technologyfacility at the T.J. Watson Research Center.

[1] R.H. Dennard, F.H. Gaensslen, L. Kuhn, and H.N.Yu, “Design of Micron MOS Switching Devices”IEEE IEDM, Dec. 1972.

[2] V.L. Rideout, F.H. Gaensslen, and A. LeBlanc,“Device Design Considerations for Ion ImplantedMOSFET’s” to be presented at IEEE IEDM, Dec. 1973.

[3] D.P. Kennedy and P.C. Murley, “Steady State Math-ematical Theory for the Insulated Gate Field EffectTransistor” IBM J. of Res. Develop. 17, 1, (1973).

Table 1

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Abstract—This paper considers the design, fab-rication, and characterization of very smallMOSFET switching devices suitable for digitalintegrated circuits using dimensions of the orderof 1 μ. Scaling relationships are presented whichshow how a conventional MOSFET can bereduced in size. An improved small device struc-ture is presented that uses ion implantation toprovide shallow source and drain regions and anonuniform substrate doping profile. One-dimensional models are used to predict the sub-strate doping profile and the correspondingthreshold voltage versus source voltage charac-teristic. A two-dimensional current transportmodel is used to predict the relative degree ofshort-channel effects for different device param-eter combinations. Polysilicon-gate MOSFET’swith channel lengths as short as 0.5 μ were fab-ricated, and the device characteristics measuredand compared with predicted values. The per-formance improvement expected from usingthese very small devices in highly miniaturizedintegrated circuits is projected.

INTRODUCTION New high resolution lithographic techniques for form-ing semiconductor integrated circuit patterns offer adecrease in linewidth of five to ten times over theoptical contact masking approach which is common-ly used in the semiconductor industry today. Of thenew techniques, electron beam pattern writing hasbeen widely used for experimental device fabrication[1]-[4] while X-ray lithography [5] and optical projec-tion printing [6] have also exhibited high-resolutioncapability. Full realization of the benefits of these newhigh-resolution lithographic techniques requires thedevelopment of new device designs, technologies,and structures which can be optimized for very smalldimensions.

This paper concerns the design, fabrication, andcharacterization of very small MOSFET switchingdevices suitable for digital integrated circuits usingdimensions of the order of 1μ. It is known thatreducing the source-to-drain spacing (i.e., the chan-nel length) of an FET leads to undesirable changes inthe device characteristics. These changes become sig-nificant when the depletion regions surrounding thesource and drain extend over a large portion of the

region in the silicon substrate under the gate elec-trode. For switching applications, the most undesir-able ‘short-channel” effect is a reduction in the gatethreshold voltage at which the device turns on,which is aggravated by high drain voltages. It hasbeen shown that these short-channel effects can beavoided by scaling down the vertical dimensions(e.g., gate insulator thickness, junction depth, etc.)along with the horizontal dimensions, while also pro-portionately decreasing the applied voltages andincreasing the substrate doping concentration [7], [8].Applying this scaling approach to a properlydesigned conventional-size MOSFET shows that a200-Å gate insulator is required if the channel lengthis to be reduced to 1μ.

A major consideration of this paper is to show howthe use of ion implantation leads to an improveddesign for very small scaled-down MOSFET’s. First,the ability of ion implantation to accurately introducea low concentration of doping atoms allows the sub-strate doping profile in the channel region under thegate to be increased in a controlled manner. Whencombined with a relatively lightly doped starting sub-

Design of Ion-Implanted MOSFET’s with Very SmallPhysical Dimensions ROBERT H. DENNARD, MEMBER, IEEE, FRITZ H. GAENSSLEN, HWA-NIEN YU, MEMBER, IEEE, V.LEO RIDEOUT, MEMBER, IEEE, ERNEST BASSOUS, AND ANDRE R. LEBLANC, MEMBER, IEEE

Reprinted from the IEEE Journal of Solid-State Circuits, Vol. SC-9, October 1974, pp. 256-268.

LIST OF SYMBOLS α Inverse semilogarithmic slope of sub-threshold characteristic.

D Width of idealized step function profile for channel implant.

�Wf Work function difference between gate and substrate.

εs i, εox Dielectric constants for silicon and silicon dioxide.

Id Drain current.

k Boltzmann’s constant.

κ Unitless scaling constant.

L MOSFET channel length.

μeff Effective surface mobility.

ni Intrinsic carrier concentration.

Na Substrate acceptor concentration.

�s Band bending in silicon at the onset of strong inversion for

zero substrate voltage.

�b Built-in junction potential.

q Charge on the electron.

Q eff Effective oxide charge.

tox Gate oxide thickness.

T Absolute temperature.

Vd ,Vs,Vg ,Vsub Drain, source, gate and substrate voltages.

Vd s Drain voltage relative to source.

Vs−sub Source voltage relative to substrate.

Vt Gate threshold voltage.

ws, wd Source and drain depletion layer widths.

W MOSFET channel width.

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strate, this channel implant reduces the sensitivity ofthe threshold voltage to changes in the source-to-sub-strate (“backgate”) bias. This reduced “substrate sen-sitivity” can then be traded off for a thicker gate insu-lator of 350-Å thickness which tends to be easier tofabricate reproducibly and reliably. Second, ionimplantation allows the formation of very shallowsource and drain regions which are more favorablewith respect to short-channel effects, while maintain-ing an acceptable sheet resistance. The combinationof these features in an all-implanted design gives aswitching device which can be fabricated with athicker gate insulator if desired, which has well-con-trolled threshold characteristics, and which has signif-icantly reduced interelectrode capacitances (e.g.,drain-to-gate or drain-to-substrate capacitances).

This paper begins by describing the scaling princi-ples which are applied to a conventional MOSFET toobtain a very small device structure capable ofimproved performance. Experimental verification ofthe scaling approach is then presented. Next, the fab-rication process for an improved scaled-down devicestructure using ion implantation is described. Designconsiderations for this all-implanted structure arebased on two analytical tools: a simple one-dimen-sional model that predicts the substrate sensitivity forlong channel-length devices, and a two-dimensionalcurrent-transport model that predicts the device turn-on characteristics as a function of channel length. Thepredicted results from both analyses are comparedwith experimental data. Using the two-dimensionalsimulation, the sensitivity of the design to variousparameters is shown. Then, detailed attention is givento an alternate design, intended for zero substratebias, which offers some advantages with respect tothreshold control, Finally, the paper concludes with adiscussion of the performance improvements to beexpected from integrated circuits that use these verysmall FET’s.

DEVICE SCALING The principles of device scaling [7], [8] show in a con-cise manner the general design trends to be followedin decreasing the size and increasing the performanceof MOSFET switching devices. Fig. 1 compares a

state-of-the-art n-channel MOSFET [9] with a scaled-down device designed following the device scalingprinciples to be described later. The larger structureshown in Fig. 1(a) is reasonably typical of commer-cially available devices fabricated by using conven-tional diffusion techniques. It uses a 1000-Å gate insu-lator thickness with a substrate doping and substratebias chosen to give a gate threshold voltage Vt ofapproximately 2 V relative to the source potential. Asubstrate doping of 5 x 1015 cm-3 is low enough to givean acceptable value of substrate sensitivity. The sub-strate sensitivity is an important criterion in digitalswitching circuits employing source followersbecause the design becomes difficult if the thresholdvoltage increases by more than a factor of two overthe full range of variation of the source voltage. Forthe device illustrated in Fig. 1(a), the design parame-ters limit the channel length L to about 5μ. Thisrestriction arises primarily from the penetration of thedepletion region surrounding the drain into the areanormally controlled by the gate electrode. For a max-imum drain voltage of approximately 12-15 V thispenetration will modify the surface potential and sig-nificantly lower the threshold voltage.

In order to design a new device suitable for small-er values of L, the device is scaled by a transformationin three variables: dimension, voltage, and doping.First, all linear dimensions are reduced by a unitlessscaling factor κ , e.g. tox

′ = tox/κ , where the primedparameters refer to the new scaled-down device. Thisreduction includes vertical dimensions such as gateinsulator thickness, junction depth, etc., as well as thehorizontal dimensions of channel length and width.Second, the voltages applied to the device arereduced by the same factor (e.g. Vd s

′ = Vd s/κ). Third,the substrate doping concentration is increased, againusing the same scaling factor (i.e., Na

′ = κNa). Thedesign shown in Fig. 1(b) was obtained using κ = 5which corresponds to the desired reduction in chan-nel length to 1μ.

The scaling relationships were developed byobserving that the depletion layer widths in thescaled-down device are reduced in proportion to thedevice dimensions due to the reduced potentials andthe increased doping. For example,

ws′ = {[2εs i(ψb

′ + Vs−sub/κ)]/qκNa}1/2 � ws/κ. (1)

The threshold voltage at turn-on [9] is also decreasedin direct proportion to the reduced device voltages sothat the device will function properly in a circuit withreduced voltage levels. This is shown by the thresh-old voltage equation for the scaled-down device.

Vt′ = (tox/κεox){−Q eff + [2εSiqκNa(ψs

′ + Vs−sub/κ)]1/2}+ (�W f + ψs

′) � Vt/κ. (2)

Fig. 1. Illustration of device scaling principles with κ = 5.(a) Conventional commercially available device structure.(b) Scaled-down device structure.

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In (2) the reduction in Vt is primarily due to thedecreased insulator thickness, tox/κ , while thechanges in the voltage and doping terms tend to can-cel out. In most cases of interest (i.e., polysilicongates of doping type opposite to that of the substrateor aluminum gates on p-type substrates) the workfunction difference �W f is of opposite sign, andapproximately cancels out ψs

′. ψs′ is the band

bending in the silicon (i.e., the surface potential) atthe onset of strong inversion for zero substrate bias. Itwould appear that the ψ ′ terms appearing in (1) and(2) prevent exact scaling since they remain approxi-mately constant, actually increasing slightly due to theincreased doping since ψb

′ � ψs′ = (2kT/q) ln

(Na′/ni). However, the fixed substrate bias supply

normally used with n-channel devices can be adjust-ed so that (ψs

′ + Vsub′) = (ψs + Vsub)/κ . Thus, by

scaling down the applied substrate bias more than theother applied voltages, the potential drop across thesource or drain junctions, or across the depletionregion under the gate, can he reduced by κ .

All of the equations that describe the MOSFETdevice characteristics may be scaled as demonstratedabove. For example, the MOSFET current equation [9]given by

Id′ = μeffεox

tox/κ

(W /κ

L/κ

)(Vg − Vt − Vd /2

κ

)·

(Vd /κ) = Id /κ (3)

is seen to be reduced by a factor of κ , for any givenset of applied voltages, assuming no change in mobil-ity. Actually, the mobility is reduced slightly due toincreased impurity scattering in the heavier dopedsubstrate.

It is possible to generalize the scaling approach toinclude electric field patterns and current density. Theelectric field distribution is maintained in the scaled-down device except for a change in scale for the spa-tial coordinates. Furthermore, the electric fieldstrength at any corresponding point is unchangedbecause V /x = V ′/x′. Thus, the carrier velocity at anypoint is also unchanged due to scaling and, hence,any saturation velocity effects will be similar in bothdevices, neglecting microscopic differences due to thefixed crystal lattice dimensions. From (3), since thedevice current is reduced by κ , the channel currentper unit of channel width W is unchanged by scaling.This is consistent with the same sheet density of car-riers (i.e., electrons per unit gate area) moving at thesame velocity. In the vicinity of the drain, the carrierswill move away from the surface to a lesser extent inthe new device, due to the shallower diffusions. Thus,the density of mobile carriers per unit volume will behigher in the space-charge region around the drain,complementing the higher density of immobile charge

due to the heavier doped substrate. Other scalingrelationships for power density, delay time, etc., aregiven in Table I and will be discussed in a subsequentsection on circuit performance.

In order to verify the scaling relationships, two setsof experimental devices were fabricated with gateinsulators of 1000 and 200 Å (i.e., κ = 5). The meas-ured drain voltage characteristics of these devices,normalized to W /L = 1, are shown in Fig. 2. The twosets of characteristics are quite similar when plottedwith voltage and current scales of the smaller devicereduced by a factor of five, which confirms the scal-ing predictions. In Fig. 2, the exact match on the cur-rent scale is thought to be fortuitous since there issome experimental uncertainty in the magnitude ofthe channel length used to normalize the characteris-tics (see Appendix). More accurate data from deviceswith larger width and length dimensions on the samechip shows an approximate reduction of ten percentin mobility for devices with the heavier doped sub-strate. That the threshold voltage also scales correctlyby a factor of five is verified in Fig. 3, which showsthe experimental

√Id versus Vg turn-on characteris-

tics for the original and the scaled-down devices. Forthe cases shown, the drain voltage is large enough tocause pinchoff and the characteristics exhibit theexpected linear relationship. When projected to inter-cept the gate voltage axis this linear relationshipdefines a threshold voltage useful for most logic cir-cuit design purposes.

Fig. 2. Experimental drain voltage characteristics for (a)conventional, and (b) scaled-down structures shown inFig. 1 normalized to W/L = 1.

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One area in which the device characteristics fail toscale is in the subthreshold or weak inversion regionof the turn-on characteristic. Below threshold, Id isexponentially dependent on Vg with an inverse semi-logarithmic slope, α, [10], [11] which for the scaled-down device is given by

α′(

volts

decade

)= dVg

′

d log10 Id′

= (kT/q log10 e)(

1 + εSi tox/κ

εoxwd /κ

), (4)

which is the same as for the original larger device.The parameter α is important to dynamic memory cir-cuits because it determines the gate voltage excursionrequired to go from the low current “off” state to thehigh current “on” state [11]. In an attempt to alsoextend the linear scaling relationships to α one couldreduce the operating temperature in (4) (i.e.,T ′ = T/κ , but this would cause a significant increasein the effective surface mobility [12] and thereby inval-idate the current scaling relationship of (3). In orderto design devices for operation at room temperatureand above, one must accept the fact that the sub-threshold behavior does not scale as desired. Thisnonscaling property of the subthreshold characteristicis of particular concern to miniature dynamic memo-ry circuits which require low source-to-drain leakagecurrents.

ION-IMPLANTED DEVICE DESIGN The scaling considerations just presented lead to thedevice structure with a 1-μ channel length shown inFig. 4(a). In contrast, the corresponding improveddesign utilizing the capability afforded by ion implan-tation is shown in Fig. 4(b). The ion-implanted deviceuses an initial substrate doping that is lower by about

a factor of four, and an implanted boron surface layerhaving a concentration somewhat greater than theconcentration used throughout the unimplanted struc-ture of Fig. 4(a). The concentration and the depth ofthe implanted surface layer are chosen so that thisheavier doped region will be completely within thesurface depletion layer when the device is turned onwith the source grounded. Thus, when the source isbiased above ground potential, the depletion layerwill extend deeper into the lighter doped substrate,and the additional exposed “bulk” charge will be rea-sonably small and will cause only a modest increasein the gate-to-source voltage required to turn on thedevice. With this improvement in substrate sensitivitythe gate insulator thickness can be increased to asmuch as 350 Å and still maintain a reasonable gatethreshold voltage as will be shown later.

Another aspect of the design philosophy is to useshallow implanted n+ regions of’ depth comparable tothe implanted p-type surface layer. The depletionregions under the gate electrode at the edges of thesource and drain are then inhibited by the heavierdoped surface layer, roughly pictured in Fig. 4(b), forthe case of a turned-off device. The depletion regionsunder the source and drain extend much further intothe lighter doped substrate. With deeper junctionsthese depletion regions would tend to merge in thelighter doped material which would cause a loss of

Fig. 3. Experimental turn-on characteristics for convention-al and scaled-down devices shown in Fig. 1 normalized toW/L =1.

Fig. 4. Detailed cross sections for (a) scaled-down devicestructure, and (b) corresponding ion-implanted devicestructure.

sscs_NL0107 1/8/07 9:56 AM

TECHNICAL ARTICLES


threshold control or, in the extreme, punchthrough athigh drain voltages. However, the shallower junctionsgive a more favorable electric field pattern whichavoids these effects when the substrate doping con-centration is properly chosen (i.e., when it is not toolight).

The device capacitances are reduced with the ion-implanted structure due to the increased depletionlayer width separating the source and drain from thesubstrate [cf. Figs. 4(a) and 4(b)], and due to the nat-ural self-alignment afforded by the ion implantationprocess which reduces the overlap of the polysilicongate over the source and drain regions. The thickergate insulator also gives reduced gate capacitance, butthe performance benefit in this respect is offset by thedecreased gate field. To compensate for the thickergate oxide and the expected threshold increase, adesign objective for maximum drain voltage was setat 4 V for the ion-implanted design in Fig. 4(b), com-pared to 3 V for the scaled-down device of Fig.4(a).

FABRICATION OF ION-IMPLANTED MOSFET’s The fabrication process for the ion-implanted MOS-FET’s used in this study will now be described. Afour-mask process was used to fabricate polysilicon-gate, n-channel MOSFET’s on a test chip which con-tains devices with channel lengths ranging from 0.5 to10 μ. Though the eventual aim is to use electron-beam pattern exposure, it was more convenient touse contact masking with high quality master masksfor process development. For this purpose high reso-lution is required only for the gate pattern which useslines as small as 1.5 μ which are reduced in the sub-sequent processing. The starting substrate resistivitywas 2 �·cm (i.e., about 7.5 × 1015cm−3). The methodof fabrication for the thick oxide isolation betweenadjacent FET’s is not described as it is not essential tothe work presented here, and because several suitabletechniques are available. Following dry thermalgrowth of the gate oxide, low energy (40 keV), lowdose (6.7 × 1011 atoms/cm2) B11 ions were implantedinto the wafers, raising the boron doping near the sil-icon surface. All implantations were performed aftergate oxide growth in order to restrict diffusion of theimplanted regions.

After the channel implantation, a 3500-Å thick poly-silicon layer was deposited, doped n+, and the gateregions delineated. Next, n+ source and drain regions2000-Å deep were formed by a high energy (100keV), high dose (4 × 1015 atoms/cm2) As75 implanta-tion through the same 350-Å oxide layer. During thisstep, however, the polysilicon gate masks the channelregion from the implant, absorbing all of the As75

dose incident there. The etching process used todelineate the gates results in a sloping sidewall whichallows a slight penetration of As75 ions underneath

the edges of the gates. The gate-to-drain (or source)overlap is estimated to be of the order of 0.2 μ. Thehigh temperature processing steps that follow theimplantations include 20 min at 900°C, and 11 min at1000°C, which is more than adequate to anneal outthe implantation damage without greatly spreadingout the implanted doses. Typical sheet resistanceswere 50�/� for the source and drain regions, and40�/� for the polysilicon areas. Following the As75

implant, a final insulating oxide layer 2000-Å thickwas deposited using low-temperature chemical-vapordeposition. Then, the contact holes to the n+ andpolysilicon regions were defined, and the metalizationwas applied and delineated. Electrical contact directlyto the shallow implanted source and drain regionswas accomplished by a suitably chosen metallurgy toavoid junction penetration due to alloying during thefinal annealing step. After metalization an annealingstep of 400 °C for 20 min in forming gas was per-formed to decrease the fast-state density.

ONE-DIMENSIONAL (LONG CHANNEL)ANALYSIS The substrate doping profile for the 40 keV,6.7 × 1011 atoms/cm2 channel implant incident onthe 350-Å gate oxide, is shown in Fig. 5.

Since the oxide absorbs 3 percent of the incidentdose, the active dose in the silicon is 6.5 × 1011

atoms/cm2. The concentration at the time of theimplantation is given by the lightly dashed Gaussianfunction added to the background doping level, Nb.For 40 keV B11 ions, the projected range and standarddeviation were taken as 1300 Å and 500 Å, respec-tively [13]. After the heat treatments of the subsequent

Fig. 5. Predicted substrate doping profile for basic ion-implanted device design for 40 keV B11 ions implantedthrough the 350-Å gate insulator.

sscs_NL0107 1/8/07 9:57 AM

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TECHNICAL ARTICLESprocessing, the boron is redistributed as shown by theheavier dashed line. These predicted profiles wereobtained using a computer program developed by F.F. Morehead of our laboratories. The programassumes that boron atoms diffusing in the siliconreflect from the silicon-oxide interface and therebyraise the surface concentration. For modeling purpos-es it is convenient to use a simple, idealized, step-function representation of the doping profile, asshown by the solid line in Fig. 5. The step profileapproximates the final predicted profile rather welland offers the advantage that it can be described by afew simple parameters. The three profiles shown inFig. 5 all have the same active dose.

Using the step profile, a model for determiningthreshold voltage has been developed from piecewisesolutions of Poisson’s equation with appropriateboundary conditions [11]. The one-dimensional modelconsiders only the vertical dimension and cannotaccount for horizontal short-channel effects. Results ofthe model are shown in Fig, 6 which plots the thresh-old voltage versus source-to-substrate bias for the ion-implanted step profile shown in Fig. 5. For compari-son, Fig. 6 also shows the substrate sensitivity charac-teristics for the nonimplanted device with a 200-Ågate insulator and a constant background doping, andfor a hypothetical device having a 350-Å gate insula-tor like the implanted structure and a constant back-ground doping like the nonimplanted structure.

The nonimplanted 200-Å case exhibits a low substratesensitivity, but the magnitude of the threshold voltageis also low. On the other hand, the nonimplanted 350-Å case shows a higher threshold, but with an unde-sirably high substrate sensitivity. The ion-implantedcase offers both a sufficiently high threshold voltage

and a reasonably low substrate sensitivity, particular-ly for Vs−sub ≥ 1 V. For Vs−sub < 1 V, a steep slopeoccurs because the surface inversion layer in thechannel is obtained while the depletion region in thesilicon under the gate does not exceed D, the stepwidth of the heavier doped implanted region. ForVs−sub ≥ 1 V, at inversion the depletion region nowextends into the lighter doped substrate and thethreshold voltage then increases relatively slowly withVs−sub [11]. Thus, with a fixed substrate bias of -1 V,the substrate sensitivity over the operating range ofthe source voltage (e.g., ground potential to 4 V) isreasonably low and very similar to the slope of thenon- implanted 200-Å design. However, the thresholdvoltage is significantly higher for the implanted designwhich allows adequate design margin so that, underworst case conditions (e.g., short-channel effectswhich reduce the threshold considerably), the thresh-old will still be high enough so that the device can beturned off to a negligible conduction level as requiredfor dynamic memory applications.

Experimental results are also given in Fig. 6 frommeasurements made on relatively long devices (i.e.,L = 10μ) which have no short-channel effects.These data agree reasonably well with the calculat-ed curve. A 35 keV, 6 × 1011 atoms/cm2 implant wasused to achieve this result, rather than the slightlyhigher design value of 40 keV and 6.7 × 1011

atoms/cm2.

TWO-DIMENSIONAL (SHORT CHANNEL)ANALYSIS For devices with sufficiently short-channel lengths,the one-dimensional model is inadequate to accountfor the threshold voltage lowering due to penetrationof the drain field into the channel region normallycontrolled by the gate. While some models have beendeveloped which account for this behavior [14], theproblem is complicated for the ion-implanted struc-ture by the non-uniform doping profile which leads toan electric field pattern that is difficult to approximate.For the ion-implanted case, the two-dimensionalnumerical current transport model of Kennedy andMock [15], [16] was utilized. The computer programwas modified by W. Chang and P. Hwang [17] to han-dle the abrupt substrate doping profiles consideredfor these devices.

The numerical current transport model wasused to calculate the turn-on behavior of the ion-implanted device by a point-by-point computa-tion of the device current for increasing values ofgate voltage. Calculated results are shown in Fig.7 for two values of channel length in the range of1μ, as well as for a relatively long-channel devicewith L = 10μ. All cases were normalized to awidth-to-length ratio of unity, and a drain voltageof 4 V was used in all cases. As the channel length

Fig. 6. Calculated and experimental substrate sensitivitycharacteristics for non-implanted devices with 200- and350-Å gate insulators, and for corresponding ion-implant-ed device with 350-Å gate insulator.

sscs_NL0107 1/8/07 9:57 AM Page 43

TECHNICAL ARTICLES


is reduced to the order of 1μ, the turn-on charac-teristic shifts to a lower gate voltage due to a low-ering of the threshold voltage. The threshold volt-age occurs at about 10−7 A where the turn-on char-acteristics make a transition from the exponentialsubthreshold behavior (a linear response on thissemilogarithmic plot) to the Id ∝ Vg

2 square-lawbehavior. This current level can also be identifiedfrom Fig. 3 as the actual current at the projectedthreshold voltage, Vt . When the computed charac-teristics were plotted in the manner of Fig. 3 theygave 4 × 10−8 A at threshold for all device lengths.The band bending, ψs , at this threshold condition isapproximately 0.75 V. Some of the other devicedesigns considered with heavier substrate concen-trations gave a higher current at threshold, so, forsimplicity, the value of 10−7 A was used in all caseswith a resultant small error in Vt .

MOSFET’s with various channel lengths weremeasured to test the predictions of the two-dimen-sional model. The technique for experimentally deter-mining the channel length for very short devices isdescribed in the Appendix. The experimental resultsare plotted in Fig. 7 and show good agreement withthe calculated curves, especially considering thesomewhat different values of L. Another form of pres-entation of this data is shown in Fig. 8 where thethreshold voltage is plotted as a function of channellength. The threshold voltage is essentially constantfor L > 2μ, and falls by a reasonably small amount asL is decreased from 2 to 1 μ, and then decreasesmore rapidly with further reductions in L. For circuitapplications the nominal value of L could be setsomewhat greater than 1 μ so that, over an expectedrange of deviation of L, the threshold voltage is rea-sonably well controlled.

For example, L = 1.3±0.3μ would giveVt = 1.0±0.1 V from chip to chip due to this short-channel effect alone. This would be tolerable formany circuit applications because of the tracking ofdifferent devices on a given chip, if indeed this

degree of control of L can be achieved. The experi-mental drain characteristics for an ion-implantedMOSFET with a 1.1-μ channel length are shown inFig. 9 for the grounded source condition. The gener-

al shape of the characteristics is the same as thoseobserved for much larger devices. No extraneousshort-channel effects were observed for drain voltagesas large as 4 V. The experimental data in Figs. 6 - 9were taken from devices using a B11 channel implan-tation energy and dose of 35 keV and 6.0 × 1011

atoms/cm2, respectively. The two-dimensional simulations were also used to

test the sensitivity of the design to various parameters.The results are given in Fig. 10, which tabulates val-ues of threshold voltage as a function of channellength for the indicated voltages. Fig. 10(a) is an ide-alized representation for the basic design that hasbeen discussed thus far. The first perturbation to thebasic design was an increase in junction depth to 0.4μ. This was found to give an appreciable reductionin threshold voltage for the shorter devices in Fig.10(b). Viewed another way, the minimum devicelength would have to be increased by 20 percent(from 1.0 to 1.2 μ) to obtain a threshold comparable

Fig. 7. Calculated and experimental subthreshold turn-oncharacteristic for basic ion-implanted design for variouschannel lengths with Vsub = -1V, Vd = 4V. Fig. 8. Experimental and calculated dependence of thresh-

old voltage on channel length for basic ion-implanteddesign with Vsub=-1V, Vd = 4V.

Fig. 9. Experimental drain voltage characteristics for basicion-implanted design with Vsub = 1V, L = 1.1μ, and w =12.2μ. Curve tracer parameters; load resistance 30Ω, drainvoltage 4 V, gate voltage 0-4V in 8 steps each 0.5 V apart.

sscs_NL0107 1/8/07 9:57 AM Page 44


TECHNICAL ARTICLES

to the basic design. This puts the value of the shal-lower junctions in perspective. Another perturbationfrom the basic design which was considered was theuse of a substrate doping lighter by a factor of 2,with a slightly higher concentration in the surfacelayer to give the same threshold for a long-channeldevice [Fig. 10(c)]. The results for smaller devicesproved to be similar to the case of deeper junctions.The next possible departure from the basic design isthe use of a shallower boron implantation in thechannel region, only half as deep, with a heavierconcentration to give the same long-channel thresh-old [Fig. 10(d)]. With the shallower profile, and con-sidering that the boron dose implanted in the siliconis about 20 percent less in this case, it was expectedthat more short-channel effects would occur. How-ever, the calculated values show almost identicalthresholds compared to the basic design. With theshallower implantation it is possible to use zero sub-strate bias and still have good substrate sensitivitysince the heavier doped region is completely deplet-ed at turn-on with a grounded source. The lastdesign perturbation considers such a case, againwith a heavier concentration to give the same long-channel threshold [Fig. 10 (e)]. The calculations forthis case show appreciably less short-channel effect.

In fact, the threshold for this case for a device withL = 0.8μ is about the same as for an L = 1.0μ

device of the basic design. This importantimprovement is apparently due to the reduceddepletion layer widths around the source anddrain with the lower voltage drop across thosejunctions. Also, with these bias and doping condi-tions, the depletion layer depth in the siliconunder the gate is much less at threshold, particu-larly near the source where only the band bend-ing, ψs , appears across this depletion region,which may help prevent the penetration of fieldlines from the drain into this region where thedevice turn-on is controlled.

CHARACTERISTICS OF THE ZERO SUBSTRATEBIAS DESIGN Since the last design shown in Fig. 10(e) appears tobe better behaved in terms of short-channel effects, itis worthwhile to review its properties more fully.Experimental devices corresponding to this designwere built and tested with various channel lengths. Inthis case a 20 ke V, 6.0 × 1011 atoms/cm2 B11 implantwas used to obtain a shallower implanted layer ofapproximately 1000-Å depth [11]. Data on thresholdvoltage for these devices with 4 V applied to the drainis presented in Fig. 11 and corresponds very well tothe calculated values. Data for a small drain voltage isalso given in this figure, showing much less variationof threshold with channel length, as expected. Thedependence of threshold voltage on source-to-sub-strate bias is shown in Fig. 12 for different values ofL. The drain-to-source voltage was held at a constantlow value for this measurement. The results show thatthe substrate sensitivity is indeed about the same forthis design with zero substrate bias as for the originaldesign with Vsub = −1 V. Note that the smaller devicesshow a somewhat flatter substrate sensitivity charac-teristic with relatively lower thresholds at high valuesof source (and drain) voltage.

Fig. 10. Threshold voltage calculated using two-dimen-sional current transport model for various parameter con-ditions. A flat-band voltage of -1.1 V is assumed.

Fig. 11. Experimental and calculated dependence ofthreshold voltage on channel length for ion-implantedzero substrate bias design.

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The turn-on characteristics for the zero substratebias design, both experimental and calculated, areshown in Fig. 13 for different values of L. The rela-

tively small shift in threshold for the short-channeldevices is evident; however, the turn-on rate is con-siderably slower for this case than for the Vsub = −1 Vcase shown in Fig. 7. This is due to the fact that thedepletion region in the silicon under the gate is veryshallow for this zero substrate bias case so that a largeportion of a given gate voltage change is droppedacross the gate insulator capacitance rather thanacross the silicon depletion layer capacitance. This isdiscussed in some detail for these devices in anotherpaper [11]. The consequence for dynamic memoryapplications is that, even though the zero substratebias design offers improved threshold control forstrong inversion, this advantage is offset by the flattersubthreshold turn-on characteristic. For such applica-tions the noise margin with the turn-on characteristicof Fig. 13 is barely suitable if the device is turned offby bringing its gate to ground. Furthermore, elevated

temperature aggravates the situation [18]. Thus, fordynamic memory, the basic design with Vsub = −1 Vpresented earlier is preferred.

CIRCUIT PERFORMANCE WITH SCALED-DOWN DEVICESThe performance improvement expected from usingvery small MOSFET’s in integrated circuits of compa-rably small dimensions is discussed in this section.First, the performance changes due to size reductionalone are obtained from the scaling considerationsgiven earlier. The influence on the circuit perform-ance due to the structural changes of the ion-implant-ed design is then discussed.

Table I lists the changes in integrated circuit per-formance which follow from scaling the circuitdimensions, voltages, and substrate doping in thesame manner as the device changes described withrespect to Fig. 1. These changes are indicated in termsof the dimensionless scaling factor κ .

TABLE ISCALING RESULTS FOR CIRCUIT PERFORMANCE

Justifying these results here in great detail would betedious, so only a simplified treatment is given. It isargued that all nodal voltages are reduced in theminiaturized circuits in proportion to the reducedsupply voltages. This follows because the quiescentvoltage levels in digital MOSFET circuits are either thesupply levels or some intermediate level given by avoltage divider consisting of two or more devices, andbecause the resistance V /I of each device isunchanged by scaling. An assumption is made thatparasitic resistance elements are either negligible orunchanged by scaling, which will be examined sub-sequently. The circuits operate properly at lower volt-ages because the device threshold voltage Vt scalesas shown in (2), and furthermore because the toler-ance spreads on Vt should be proportionatelyreduced as well if each parameter in (2 ) is controlledto the same percentage accuracy. Noise margins arereduced, but at the same time internally generatednoise coupling voltages are reduced by the lower sig-nal voltage swings.

Due to the reduction in dimensions, all circuit ele-ments (i.e., interconnection lines as well as devices)

Fig. 12. Substrate sensitivity characteristics for ion-implanted zero substrate bias design with channel lengthas parameter.

Fig. 13. Calculated and experimental subthreshold turn-oncharacteristics for ion-implanted zero substrate biasdesign.

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will have their capacitances reduced by a factor of κ .This occurs because of the reduction by κ2 in the areaof these components, which is partially cancelled bythe decrease in the electrode spacing by κ due tothinner insulating films and reduced depletion layerwidths. These reduced capacitances are driven by theunchanged device resistances V /I giving decreasedtransition times with a resultant reduction in the delaytime of each circuit by a factor of κ . The power dissi-pation of each circuit is reduced by κ2 due to thereduced voltage and current levels, so the power-delay product is improved by κ3. Since the area of agiven device or circuit is also reduced by κ2, thepower density remains constant. Thus, even if manymore circuits are placed on a given integrated circuitchip, the cooling problem is essentially unchanged.

TABLE II SCALING RESULTS FOR INTERCONNECTION LINES

As indicated in Table II, a number of problemsarise from the fact that the cross-sectional area ofconductors is decreased by κ2 while the length isdecreased only by κ . It is assumed here that thethicknesses of the conductors are necessarily reducedalong with the widths because of the more stringentresolution requirements (e.g., on etching, etc.). Theconductivity is considered to remain constant which isreasonable for metal films down to very small dimen-sions (until the mean free path becomes comparableto the thickness), and is also reasonable for degener-ately doped semiconducting lines where solid solu-bility and impurity scattering considerations limit anyincrease in conductivity. Under these assumptions theresistance of a given line increases directly with thescaling factor κ . The IR drop in such a line is there-fore constant (with the decreased current levels), butis κ times greater in comparison to the lower operat-ing voltages. The response time of an unterminatedtransmission line is characteristically limited by itstime constant RLC, which is unchanged by scaling;however, this makes it difficult to take advantage ofthe higher switching speeds inherent in the scaled-down devices when signal propagation over longlines is involved. Also, the current density in a scaled-down conductor is increased by κ , which causes areliability concern. In conventional MOSFET circuits,these conductivity problems are relatively minor, butthey become significant for linewidths of microndimensions. The problems may he circumvented in

high performance circuits by widening the powerbuses and by avoiding the use of n+ doped lines forsignal propagation.

Use of the ion-implanted devices considered in thispaper will give similar performance improvement tothat of the scaled-down device with κ = 5 given inTable I. For the implanted devices with the higheroperating voltages (4 V instead of 3 V) and higherthreshold voltages (0.9 V instead of 0.4 V), the currentlevel will be reduced in proportion to (Vg − Vt)

2/ tox

to about 80 percent of the current in the scaled-downdevice. The power dissipation per circuit is thus aboutthe same in both cases. All device capacitances areabout a factor of two less in the implanted devices,and n+ interconnection lines will show the sameimprovement due to the lighter substrate doping anddecreased junction depth. Some capacitance elementssuch as metal interconnection lines would be essen-tially unchanged so that the overall capacitanceimprovement in a typical circuit would be somewhatless than a factor of two. The delay time per circuitwhich is proportional to V C /I thus appears to beabout the same for the implanted and for the directlyscaled-down micron devices shown in Fig. 4.

SUMMARY This paper has considered the design, fabrication, andcharacterization of very small MOSFET switchingdevices. These considerations are applicable to high-ly miniaturized integrated circuits fabricated by high-resolution lithographic techniques such as electron-beam pattern writing. A consistent set of scaling rela-tionships were presented that show how a conven-tional device can be reduced in size; however, thisdirect scaling approach leads to some challengingtechnological requirements such as very thin gateinsulators. It was then shown how an all ion-implant-ed structure can be used to overcome these difficul-ties without sacrificing device area or performance. Atwo-dimensional current transport model modified foruse with ion-implanted structures proved particularlyvaluable in predicting the relative degree of short-channel effects arising from different device parame-ter combinations. The general objective of the studywas to design an n-channel polysilicon-gate MOSFETwith a 1-μ channel length for high-density source-fol-lower circuits such as those used in dynamic memo-ries. The most satisfactory combination of subthresh-old turn-on range, threshold control, and substratesensitivity was achieved by an experimental MOSFETthat used a 35 keV, 6.0 × 1011 atoms/cm2 B11 channelimplant, a 100 keV, 4 × 1015 atoms/cm2 As75

source/drain implant, a 350-Å gate insulator, and anapplied substrate bias of –1 V. Also presented was anion-implanted design intended for zero substrate biasthat is more attractive from the point of view of

Parameter Scaling FactorLine resistance, RL = ρL/Wt κNormalized voltage drop IRL/V κLine response time RLC lLine current density I/A κ

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threshold control but suffers from an increased sub-threshold turn-on range. Finally the sizable perform-ance improvement expected from using very smallMOSFET’s in integrated circuits of comparably smalldimensions was projected.

APPENDIX EXPERIMENTAL DETERMINATION OF CHANNEL LENGTH A technique for determining the effective electricalchannel length L for very small MOSFET’s from exper-imental data is described here. The technique is basedon the observation that

W Rchan = Lρchan (A1)

where Rchan is the channel resistance, and ρchan thesheet resistance of the channel. For a fixed value ofVg − Vt > 0, and with the device turned on in thebelow-pinchoff region, the channel sheet resistance isrelatively independent of L. Then, a plot of W Rchan

versus Lmask will intercept the Lmask axis at �Lbecause �L = Lmask − L , where �L is the processingreduction in the mask dimension due to exposure andetching. An example of this technique is illustrated inFig. 14.

The experimental values of W and Rchan used in Fig.14 were obtained as follows. First, the sheet resist-ance of the ion-implanted n+ region was determinedusing a relatively large four-point probe structure.Knowing the n+ sheet resistance allows us to computethe source and drain resistance Rs and Rd , and to

deduce W from the resistance of a long, slender, n+

line. The channel resistance can be calculated from

Rchan = Vchan/Id

= (Vd –Id (Rs + Rd + 2Rc + R load))/Id , (A2)

where Rc is the contact resistance of the source ordrain, and R load is the load resistance of the measure-ment circuit. Id was determined at Vg = Vt + 0.5 Vwith a small applied drain voltage of 50 or 100 mV.The procedure is more simple and accurate if oneuses a set of MOSFET’s having different values ofLmask but all with the same value of Wmask. Then oneneeds only to plot Rchan versus Lmask in order todetermine �L .

AcknowledgementsWe wish to acknowledge the valuable contributions

of B. L. Crowder and F. F. Morehead who providedthe ion implantations and related design information.Also important were the contributions of P. Hwangand W. Chang to two-dimensional device computa-tions. J. J. Walker and V. DiLonardo assisted with themask preparation and testing activities. The deviceswere fabricated by the staff of the silicon technologyfacility at the T. J. Watson Research Center.

References[1] F. Fang, M. Hatzakis, and C. H. Ting, “Electron-

beam fabrication of ion implanted high-perform-ance FET circuits,” J. Vac. Sci. Technol., vol. 10,p. 1082, 1973.

[2] J. M. Pankrantz, H. T. Yuan, and L. T. Creagh, “Ahigh-gain, low-noise transistor fabricated withelectron beam lithography,” in Tech. Dig. Int.Electron Devices Meeting, Dec. 1973, pp. 44-46.

[3] H. N. Yu, R. H. Dennard, T. H. P. Chang, and M.Hatzakis, “An experimental high-density memo-ry array fabricated with election beam,” in ISSCCDig. Tech. Papers, Feb. 1973, pp. 98-99.

[4] R. C, Henderson, R. F. W. Pease, A. M.Voshchenkow, P. Mallery, and R. L. Wadsack, “Ahigh speed p-channel random access 1024-bitmemory made with electron lithography,” inTech. Dig. Int. Electron Devices Meeting, Dec.1973, pp. 138-140.

[5] D. L. Spears and H. I. Smith, “X-Ray lithography– a new high resolution replication process,”Solid State Technol., vol. 15, p.21, 1972.

[6] S. Middlehoek, “Projection masking, thin pho-toresist layers and interference effects,” IBM J.Res. Develop., vol. 14, p. 117, 1970.

[7] R. H. Dennard, F. H, Gaensslen, L. Kuhn, and H.N. Yu, “Design of micron MOS switchingdevices,” presented at the IEEE Int. ElectronDevices Meeting, Washington, D.C., Dec. 1972.

Fig. 14. lllustration of experimental technique used todetermine channel length, L.

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TECHNICAL ARTICLES[8] A. N. Broers and R. H. Dennard, “Impact of elec-

tron beam technology on silicon device fabrica-tion,” Semicond. Silicon (Electrochem. Soc. Pub-lication), H. R. Huff and R. R. Burgess, eds., pp.830-841, 1973.

[9] D. L. Critchlow, R. H. Dennard, and S. E. Schus-ter, “Design characteristics of n-channel insulat-ed-gate field-effect transistors,” IBM J. Res.Develop., vol. 17, p. 430, 1973.

[10] R. M. Swanson and J. D. Meindl, “Ion-implantedcomplementary MOS transistors in low-voltagecircuits,” IEEE J. Solid-State Circuits, vol. SC-7,pp. 146-153, April 1972.

[11] V. L. Rideout, F. H. Gaensslen, and A. LeBlanc,“Device design considerations for ion implantedn-channel MOSFET’s,” IBM J. Res. Develop., tobe published.

[12] F. F. Fang and A. B. Fowler, “Transport proper-ties of electrons in inverted Si surfaces,” Phys.Rev. vol. 169, p. 619, 1968.

[13] W. S. Johnson, IBM System Products Division, E.Fishkill, N. Y., private communication.

[14] H. S. Lee, “An analysis of the threshold voltagefor short channel IGFET’s,” Solid-State Electron.,vol. 16, p. 1407, 1973.

[15] D. P. Kennedy and P. C. Murley, “Steady statemathematical theory for the insulated gate fieldeffect transistor,” IBM J. Res. Develop., vol. 17, p.1, 1973.

[16] M. S. Mock, “A two-dimensional mathematicalmodel of the insulated-gate field-effect transis-tor,” Solid-State Electron., vol.16, p. 601, 1973.

[17] W. Chang and P. Hwang, IBM System ProductsDivision, Essex Junction, Vt., private communi-cation.

[18] R. R. Troutman, “Subthreshold design considera-tions for insulated gate field-effect transistors,”IEEE J. Solid-State Circuits, vol. SC-9, p.55, April1974.

Robert H. Dennard (M’65) wasborn in Terrell, Texas, in 1932. Hereceived the B.S. and M.S. degreesin electrical engineering fromSouthern Methodist University, Dal-las, Tex., in 1954 and 1956, respec-tively, and the Ph.D. degree fromCarnegie Institute of Technology,

Pittsburgh, Pa., in 1958. In 1958 he joined the IBM Research Division where

his experience included study of new devices and cir-cuits for logic and memory applications, and devel-opment of advanced data communication techniques.Since 1963 he has been at the IBM T. J. WatsonResearch Center, Yorktown Heights, N.Y., where heworked with a group exploring large-scale integration(LSI), while making contributions in cost and yield

models, MOSFET device and integrated circuit design,and FET memory cells and organizations. Since 1971he has been manager of a group which is exploringhigh density digital integrated circuits using advancedtechnology concepts such as electron beam patternexposure.

Fritz H. Gaensslen was born inTuebingen, Germany, on October4, 1931. He received the DipI. Ing.and Dr. Ing. degrees in electricalengineering from the TechnicalUniversity of Munich, Munich,Germany, in 1959 and 1966,respectively.

Prior to 1966 he served as Assistant Professor in theDepartment of Electrical Engineering, Technical Uni-versity of Munich, Munich, Germany. During this peri-od he was working on the synthesis of linear and dig-ital networks. In 1966 he joined the IBM T. J. WatsonResearch Center, Yorktown Heights, N.Y., where he iscurrently a member of a semiconductor device andprocess design group. His current technical interestsinvolve various aspects of advanced integrated cir-cuits like miniaturization, device simulation, and ionimplantation. From September 1973 he was on a oneyear assignment at the IBM Laboratory, Boeblingen,Germany.

Dr. Gaensslen is a member of the Nachrichtentech-nische Gesellschaft.

Hwa-Nien Yu (M’65) was born inShanghai, China, on January 17,1929. He received the B.S., MS., andPh.D. degrees in electrical engi-neering from the University of Illi-nois, Urbana, in 1953, 1954, and1958, respectively. While at the Uni-versity, he was a Research Assistant

in the Digital Computer Laboratory and worked onthe design of the Illiac-II computer. Since joining theIBM Research Laboratory in 1957, he has beenengaged in various exploratory solid-state deviceresearch activities. After working with the AdvancedSystems Development Division from 1959 to 1962,he rejoined the Research Division in 1962 to workon the ultra-high speed germanium device technol-ogy. Since 1967, he has been engaged in advancedsilicon LSI device technology research. He is cur-rently the Manager of Semiconductor Technology atthe IBM T. J. Watson Research Center, YorktownHeights, N.Y.

Dr. Yu is a member of Sigma Xi.

V. Leo Rideout (S’61—M’65) was born in N.J. in 1941.He received the BS.E.E. degree with honors in 1963from the University of Wisconsin, Madison, the

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M,S.E.E. degree in 1964 from Stan-ford University, Stanford, Calif., andthe Ph.D. degree in materials sci-ence in 1970 from the University ofSouthern California (U.S.C.), LosAngeles. His thesis work at U.S.C.under Prof. C. H. Crowell concernedthermally assisted current transport

in platinum silicide Schottky barriers.From 1963 to 1965 he was a member of the techni-

cal staff of Bell Telephone Laboratories where heworked on high-frequency germanium transistors andmetal-semiconductor Schottky barriers on potassiumtantalate. In 1966 he spent a year as a Research Assis-tant in the department of Materials Science at the Tech-nological University of Eindhoven, Eindhoven, TheNetherlands, studying acoustoelectric effects in cadmi-um sulphide. In 1970 he joined IBM Research in thedevice research group of Dr. L. Esaki where heworked on fabrication and contact technology for mul-tiheterojunction “superlattice” structures using gallium-arsenide-phosphide and gallium-aluminum-arsenide.Since 1972 he has been a member of the semiconduc-tor device and circuit design group of Dr. R. Dennardat the IBM T. J. Watson Research Center, YorktownHeights, N.Y. His present research interests concernhigh density silicon FET technology. He is the authoror co-author of 20 technical papers and 3 US. Patents.

Dr. Rideout is a member of the ElectrochemicalSociety, Tau Beta Pi, Eta Kappa Nu, Phi Kappa Phi,and Sigma Xi.

Ernest Bassous was born inAlexandria, Egypt, on September 1,1931. He received the B.Sc. degreein chemistry from the University ofLondon, London, England in 1953,and the M.S. degree in physicalchemistry from the PolytechnicInstitute of Brooklyn, Brooklyn,

N.Y. in 1965. From 1954 to 1959 he taught Chemistry and

Physics at the British Boys’ School, Alexandria,Egypt. He went to France in 1959 where he workedfor one year on infra red detectors at the CentreNational d’Etudes des Telecommunications, Issy-les-Moulineaux, Seine. From 1960 to 1964 he worked atthe Thomas A. Edison Research Laboratory in WestOrange, N.J., where his activities included studies inarc discharge phenomena, ultra violet absorptionspectroscopy, and organic semiconductors. In 1964he joined the IBM Research Laboratory, YorktownHeights, N.Y., to work on semiconductors. As amember of the Research staff he is presentlyengaged in the study of materials and processesused in the fabrication of silicon integrated circuits.

Mr. Bassous is a member of the ElectrochemicalSociety and the American Association for theAdvancement of Science.

Andre R. LeBlanc (M’74) receivedthe B.S. degree in electrical engi-neering, and the M.S. degree inphysics from the University of Ver-mont, Burlington, in 1956 and1959, respectively, and the D.Sc.degree in electrical engineeringfrom the University of New Mexico,

Albuquerque, in 1962. Prior to joining IBM, Essex Junction, Vt., in 1957, he

was affiliated with G.E. as an electrical engineer and alsowith Sandia Corporation in conjunction with the Univer-sity of New Mexico. In 1959 he took an educationalleave of absence to complete his doctorate. He ispresently a member of the Exploratory Memory Groupat the IBM Laboratory, Essex Junction, where his currenttechnical interest includes a study of short-channel MOS-FET devices. He has authored five publications andtwelve papers, as well as several IBM Technical Reports.

Dr. LeBlanc is a member of Sigma Xi and Tau Beta Pi.

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James Meindl, friend and pio-neer of the solid-state circuitscommunity was recognized in

2006 with the highest IEEEaward, the IEEE Medal of Honor,“for pioneering contributions tomicroelectronics, including lowpower, biomedical, physical limitsand on-chip interconnect net-works.” Meindl, a prolific author,energetic mentor and broadthinker, accepted the award as thehighlight of the IEEE Honors cere-mony in June 2006.

Besides his outstanding technicalcontributions, Meindl is well knownto the solid-state circuits communi-ty for his service in many importantroles, serving as the first editor ofthe JSSC and chair of the ISSCC. In2003 ISSCC recognized Meindl asthe author with the highest numberof ISSCC papers during its first 50years. He has more than 360authored papers in IEEEXplore.

Q and A Meindl the MentorPublishing 360 papers requires alot of human interconnection, withstudents and co-authors. Meindl isan important force in generatingproductive graduate students andindustry leaders. Over his career,he has supervised over 80 Ph.D.graduates at Stanford University,Rensselaer Polytechnic Instituteand Georgia Institute of Technolo-gy, many of whom have gone onto have profound impact on thesemiconductor industry.

Q. How do you select your gradu-ate students?

A. The prime qualities I look for inselecting graduate students areability/talent, motivation/commit-ment, interpersonal skill/friendli-ness, integrity and responsive-ness. The best test for these qual-

ities is to engage the student in aone quarter/semester special proj-ects course prior to any decisionregarding a Ph.D. commitment.For overseas students, this is oftennot feasible and then at least aone academic year commitmentwith support is necessary basedon a resume and phone calls.

Q. What about written versus oralqualifying exams?

A. Even though it was new to mewhen I started on the faculty atStanford, I learned to prefer theoral over a written exam becausethe personal interaction with thestudent under challenging condi-tions is extremely revealing.Observing the student “thinkingout loud and responding toclues” is most informative.

Q. On picking thesis topics?A. My favorite word of advice to a

Ph.D. student is “try the simplestcase,” which I learned from Pro-fessor William Shockley, NobelPrize Recipient for the inventionof the transistor, whose office

was only two doors away fromme at Stanford.

Q. How successful have you beenpredicting your students’accomplishments?

A. I have had my share of surpris-es not as often related to thesisresearch productivity as to downstream professional accomplish-ments that I might have (or nothave) projected. Higher levelprofessional accomplishmentsare strongly related to “peopleskills.” My favorite question formyself regarding a Ph.D. gradu-ate is “what did he do best?"

Researching the Future Q. Defining problems, researching

to find solutions, communicat-ing the solutions, presentingand writing which of these ismost fun and which is hardest?

A. The most fun is finding an ele-gant new solution and this iswhat I strive to encourage everystudent to experience. Nothingis more challenging than askingthe right question in unambigu-ous terms at the right time.Checking solutions and inter-preting them to extract deepinsights are important aspects ofPh.D. research that I learnedwell at Carnegie Tech in the1950’s.

Q. What are the pros and cons ofresearch that ends up in thepublic domain versus theresearch destined for privatelyheld and licensed patents?

A. The IP issues of today are com-plex and can be vexing. TheSRC/MARCO Focus Center Pro-gram, supported by a consor-tium of US companies andDARPA, has what I have foundto be a quite reasonable

An Interview with James Meindl 2006IEEE Medal of Honor ReceipientMicroelectronics pioneer recognized with highest IEEE award

James Meindl receiving the IEEEMedal of Honor June 2006 at the IEEEaward ceremony.

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approach to IP ownership:MARCO receives a non-exclu-sive royalty-free license to allforeground IP and reasonableassurance that any critical back-ground IP will be licensed for areasonable royalty. Giving moreauthority to the Provost’s officeto negotiate IP agreementsshould help the current situa-tion. To be competitive global-ly, US companies now needuniversity research results andthe best interests of the countryare served when this happens.

Q. What are the new hot areas thatfor the next decade?

A. Electronics and more specificallyICs have been the principal driverof the most important economicevent of the past half century, theinformation revolution. My view ofthe critical reason for the unprece-dented impact of the IC is that itrepresents a fusion of the top-down and bottom-up approachesto microelectronics that has nowevolved to become nanoelectron-ics. Scaling is our common term forthe top-down approach. The bot-tom-up approach is epitomized bythe self-assembled single crystal sil-icon ingot from which (now300mm) silicon wafers are sliced,each yielding several hundredchips each now containing severalbillion transistors.

Of course Moore’s Law willcease, perhaps in a 10-20 year time-frame. But my crystal ball suggestsIC manufacturing will be importantfor more than double that numberof years. The “vacuum tube-to-tran-sistor like” breakthrough that isneeded to replace ICs will require amuch more elegant and stillunknown fusion of top-down nan-otechnology in the sub-10nm rangewith self-assembled bottom-up nan-otechnology probably rooted inbiochemical science.

Meindl accepted his award withthese comments about technology.

Early 21st century microchips are

a marvelous consequence of a“fusion of the top-down and bot-tom-up approaches to nanotech-nololgy.” Top-down nanotechnolo-gy has been used to pattern andproduce multibillion transistor chipswith minimum feature sizes nowbeyond 50 nm. Bottom-up nan-otechnology has been used to pro-duce self-assembled single crystalingots of silicon that are sliced toprovide 300 mm diameter wafers formicrochip manufacturing. Onebroad prospective is that to advancebeyond the ultimate limits of CMOSintegrated electronics will require anelegant fusion of top-down and bot-tom-up nanotechnology enabled byfuture discoveries and inventions inboth physical and biological scienceand engineering as profound as themid-20th century inventions of thetransistor and the integrated circuit.Carbon nanotube and graphenenanoribbon technologies representprimitive examples of efforts toachieve such a fusion.

About James MeindlEarly in his career, Dr. Meindldeveloped micropower integratedcircuits for portable military equip-

ment at the U.S. Army ElectronicsLaboratory in Fort Monmouth, NewJersey. He then joined StanfordUniversity in Palo Alto, California,where he developed low-powerintegrated circuits and sensors for aportable electronic reading aid forthe blind, miniature wireless radiotelemetry systems for biomedicalresearch, and non-invasive ultra-sonic imaging and blood-flowmeasurement systems. Dr. Meindlwas the founding director of theIntegrated Circuits Laboratory anda founding co-director of the Cen-ter for Integrated Systems at Stan-ford. The latter was a model foruniversity and industry cooperativeresearch in microelectronics.

From 1986 to 1993, Dr. Meindlwas senior vice president for aca-demic affairs and provost of Rens-selaer Polytechnic Institute in Troy,New York. In this role he wasresponsible for all teaching andresearch.

He joined Georgia Tech in 1993as director of its MicroelectronicResearch Center. In 1998, hebecame the founding director ofthe Interconnect Focus Center,where he led a team of more than

The first Editor, James Meindl, then of the US Army ElectronicsCommand had to be very diligent in his search for both adequatequantity and quality of papers for his first issues.

From the beginning, a decision was made that a major source ofpapers for the JSSC should be the full-length versions of papers firstpresented at the ISSCC. However, this aspect took time. Many of theconference speakers at the ISSCC were not accustomed to publishingin refereed scholarly publications. After the vigorous refereeing andselection process for paper presentation at the ISSCC, it was neces-sary to work rather carefully with prospective authors to encouragethem for further effort to achieve the results for adequate publicationin a major journal of the IEEE.

Dr. Meindl, as the first Editor made significant contributions, notonly in working with the authors to publish their good contributionsin spite of the press of their dealing on a daily basis with the explod-ing technology of solid-state circuits and devices. In addition he setthe tone for the Journal of Solid-State Circuits. In short order he wasable to achieve a high standard of quality and was able to establisha pattern of publishing major ISSCC presentations as regular titlepapers… From “The Origin of the Journal, the Council and the Conference

of Solid-State Circuits” by Donald O. Pederson, JSSC, April 1984

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60 faculty members from MIT,Stanford, Rensselaer, SUNYAlbany, and Georgia Tech in apartnership with industry and gov-ernment. His research at GeorgiaTech includes exploring different

solutions for solving interconnec-tivity problems that arise from try-ing to interconnect billions of tran-sistors within a tiny chip.

An IEEE Life Fellow, Dr. Meindlis the recipient of the Benjamin

Garver Lamme Medal of the Amer-ican Association for EngineeringEducation, the J.J.Ebers Award ofthe IEEE Electron Devices Society,the IEEE Education Medal and theIEEE Solid State Circuits Award.

Hugo De Man Awarded for Leadership in IntegratedCircuit Design and Design MethodologyFounder of IMEC recognized with highest SSCS award

Hugo De Man, Professor Emeritusat the Katholieke Universiteit, Leu-ven, Belgium will receive the IEEEDonald O. Pederson TechnicalField Award in Solid-State Circuits,on Monday 12 February 2007 atthe ISSCC for leadership in inte-grated circuit design and designmethodology.

Jan Rabaey, a U.C. Berkeley pro-fessor and a former graduate stu-dent of De Man notes that De Manis responsible for “many firsts inthe computer-aided design world -mixed-mode simulation, switched-capacitor simulation, digital signalprocessing optimization, high-levelsynthesis for DSP, silicon compila-tion, system-level design. De Manwas also the first to use the termand ideas of ‘Meet-in-the-middledesign methodology’, which is the

basis of the platform based designmethodology (this in the early1980s!) And De Man has majorimpacts on digital design” andRabaey cites the NORA CMOS asan example. NORA stands for “NoRace,” which has precharge andevaluation properties that enableone to design simple testing cir-cuits for output stuck-at-zero,stuck-at-one, stuck-open andstuck-on faults.

Georges Gielen, professor at K.U. Leuven, lists fields that De Manhas contributed to: “advanced sim-ulation (switched capacitors), high-level synthesis (the different Cathe-dral projects), hardware-softwareco-design, etc.” Much of this workhas been taken up by spin-offssuch as Silvar Lisco, EDC, andCoWare. “His contributions to thedevelopment of innovative designmethodologies and related EDAtools have enabled the design ofmulti-million-transistor chips. Hugoand his colleagues have built IMEC(the Inter-University Microelectron-ics Center) and K.U. Leuven intothe pre-eminent microelectronicsresearch center in Europe.”

Rabaey recalls from their jointprojects that De Man “was quickto observe that simulation tech-niques used for mixed-mode simu-lation as developed in the DIANAprogram could be easily adoptedto analyze discrete-time analogsystems as well. This was thebeginning of the development of asophisticated environment thatultimately covered all aspects of

switched-capacitor design, andwas commercialized by Silvar-Lisco. A second project where Icollaborated with him was on thenow ‘infamous’ Cathedral projects,which really brought high-levelsynthesis to the foreground. Again,Hugo observed early on that digi-tal signal processing was an areawhere design automation couldhave a big impact. Cathedral waswidely known as one of the first(and maybe last) instances of high-level synthesis that was adopted inindustry.”

The IMEC ChallengeDe Man comments that joiningRoger Van Overstraeten’s team in1983 to set up IMEC was the great-est challenge of his career. IMEC isan independent research institutecovering all aspects of micro-elec-

Hugo De Man, Professor Emeritus atthe Katholieke Universitiet, Leuven,Belgium, is the recipient of the 2007IEEE Donald O. Pederson TechnicalField Award in Solid-State Circuits.

His Royal Highness, the late King ofBelgium, Boudewijn, talking withHugo De Man while visiting themicroelectronics lab at the Universityof Leuven in the seventies.

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tronics and combining internation-al contract research by top playersin the field with doctoral levelresearch, teaching and publica-tions. According to Cor Claeys, acurrent Research Head at IMEC, itwas formed from a small researchgroup of about 20 people at theUniversity of Leuven. By thebeginning of this decade IMEC hadbecame the largest such group inEurope with 125 professionalresearchers. Dave Hodges whoknew and worked with him duringDe Man’s time as a post-doc atU.C. Berkeley, 1970-71, says thatDe Man and others “built IMECinto the pre-eminent microelec-tronics research center in Europe.It was always clear that he is a manwith many talents. He and his stu-dents have contributed much tothe progress of microelectronics.”

De Man explains, “IMEC helpedin creating a great mixed industry-university team to build a success-ful research program on DSP sili-con compilation, the results ofwhich are still in use today. Andmost of the team members haveeither created their own spin-offcompanies, are captains of indus-try or top level academics. So thegreatest challenge became also thegreatest fun as there is no satisfac-tion without overcoming somechallenge first.”

Willy Sansen, Head of ESAT-MICAS at K.U. Leuven, reports thatDe Man’s “task has been to lookaround and provide advice to thepolicymakers of IMEC. He doesthis exceedingly well!”

De Man Looks Back“I was extremely lucky to meettwo extra-ordinary visionary men-tors who both became friends forlife: Roger Van Overstraeten andDon Pederson. The first openedthe world of physics and technolo-gy for me, the second introducedme to the passion of circuit andsystem design and so many othergood things in life.

Common to both was the vision

that you never walk alone but thatgreat things only happen whenyou stimulate the best people tojoin forces and have fun in doingso. For that reason receiving theDon Pederson award is so dear tome as I owe a lot to him, as doeseveryone who had the privilege towork with him.

Another factor of luck is that Ibelong to a generation that couldparticipate in the 60-year evolutionfrom the single transistor circuit tothe billion-transistor chip. Perhapsone of the most fascinating periodsin engineering history, althoughyou never know.”

Inspired Educator De Man’s lectures were by far themost inspiring of Rabaey’s under-graduate career. “In fact, theyinspired me so much that I ulti-mately changed my personal direc-tion from control systems to inte-grated circuits,” Rabaey said. Gie-len also feels that De Man’s inspir-ing lectures and presentations arehis most memorable trait. Claeyspoints out that even now as anemeritus professor, “his presenta-tions are not at all a review of thehistory but more a look into thefuture. He is exploring new fieldsand tries to understand the physicsinvolved, their challenges andpotentials their may bring in thefuture.”

Raebey recalls De Man wasknown to be a fair but hard-drivingadvisor. His undergraduate labmates made a movie for a Christ-mas party of De Man’s studentsslaving on the terminals in thecomputer room, spewing tons ofcomputer paper from the printer,all this playing against the music ofIke and Tina Turner’s “ProudMary” with the lyrics “Working forDe Man every night and day.”

Gielen recalls, “the large size ofthe reading material for his cours-es. Hugo was infamous for that.He could motivate his students towork themselves through the bigpiles of difficult material that he

was teaching.”Claeys notes, “He initiated the

so-called ‘student projects’ where-by a group of 3 or 4 students hadto work during the year on a ded-icated project. In the 70s it was anew teaching concept which laterbecame common practice.”

Gielen recalls that De Man intro-duced many “design projects inour EE curriculum, where studentscould gain hands-on experienceswith the course material. Thisincludes also many projects withapplying CAD software to VLSIdesign.”

Claeys can still remember howan exam question of De Man’s 35years ago required undergraduatesto examine the whole picturebefore designing a circuit solution.“I want to build a radio for my carand I have to drive through theSahara, What type of technologyshould I use? You first had to ana-lyze the question: the desertmeans a hot temperature, technol-ogy must reliable, before ananswer could be given.”

Claeys pointed out that De Manwas available for the studentswhen needed. “The assistantsworking for him and supervisinglaboratories also had to treat thestudents as a very valuable asset.”

Claeys sums it up, “All his life heremained an enthusiastic professorwho considered teaching as a veryimportant job; I would more say amission in his life. Working togeth-er with students was an extremelyimportant issue for him.”

“It is ironic, though, that DeMan, despite being an inspirededucator, never wrote a textbookhimself about digital design. Someof his former students, like JanRabaey, have done so instead,”notes Gielen.

De Man comments that a mostsatisfying part of his career hasbeen seeing his Master and Ph.D.students contribute to progress inthe field worldwide, both in theacademic world and in industry.“For me, teaching is the most

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rewarding profession as it providesyou with the opportunity to multi-ply and transfer your knowledgeand to help people to stimulatetheir own great creative talent andmake it available to create a bettersociety. I am extremely grateful toall of my students for this greatestof all presents!”

Seeing Clearly And Conveying ItOne of DeMan’s principles is that“if you cannot explain somethingin simple words you don't knowabout what you are speaking.Somebody can give high leveltechnical presentations but oftenforget about basic things and con-cepts,” Claeys recalls.

Claeys continues by noting thatDe Man would comment “many sci-entists are too much focused ontheir own narrow research field andthe direct problems associated withthem. Executing projects and attract-ing new projects are key for them.However, people should have abroad view and interest in order toput their own activities in the rightcontext and take sufficient time tothink about future trends and chal-lenges. He is a great scientist withan excellent scientific track recordbut he also has a very good vision.”

Rabaey agrees, “De Man is a realdeep thinker - always listening andobserving and from this distillingnew visions. He also neverstopped learning. As such, he hasimpacted the directions of manypeople and companies.”

Georges Gielen continues, “DeMan is essentially a visionaryphilosopher, who continuouslylooks ahead into the future(future applications and societalneeds, state of the technology,etc.) and then tries to derivefrom that the research activitiesthat need to be started today.The drawback of being a vision-ary though is that some of thesetools were maybe commercial-ized a bit too early in time, in thesense that the market was not

always mature enough for imme-diate wide adoption in industrialpractice.”

Sansen always remembers DeMan’s laid-back kind of style, alwaysproviding a very broad view onthings. De Man has “a very broadview on where microelectronics isheading to; he continuously tries toextrapolate how technologies andsystem design can be teamed uptowards higher complexity. Hugodeserves this prize as he has beenone of the longest followers of DonPederson,” observes Sansen.

Sansen applauds De Manreceiving the Pederson award as“he has surely been one of themost ardent followers of Peder-son. He has been convinced allalong that CAD software is essen-tial to advance the design chips ofhigh complexity. He has been inthe forefront to illustrate this. Andhe has been very successful inputting out design software suchthat it could be used by design-ers; his ‘meet-in-the middle’approach for system design hasbeen exemplary.”

Biography of Hugo De ManHugo De Man was born on September 19, 1940 in Boom, Belgium.He received the Electrical Engineering and Ph.D. degrees from theKatholieke Universiteit Leuven (K.U. Leuven), Belgium, in 1964 and1968, respectively.

In 1968 he joined the K.U. Leuven, working on device physics andIC design. From 1969 to 1971 he was a postdoc at U.C. Berkeley, inthe CAD group of Prof. D.O. Pederson. In 1971 he returned to theK.U. Leuven, where he became full professor in 1974.

In 1975 he was a Visiting Associate Professor at U.C. Berkeley. Hewas an Associate Editor for the IEEE Journal of Solid-State Circuitsfrom 1975-1980 and Associate Editor for the IEEE Transactions onCAD from 1982 to 1985.

Prof. De Man has been advisor of 60 Ph.D. students. He has con-tributed to over 500 scientific publications and was keynote speakerat the ESSCIRC, DAC, DATE and ISSCC conferences. He was programchair of ESSCIRC and DATE conferences.

He is co-founder of the Interuniversity Micro-Electronics Center(IMEC) where, from 1984 to 1995, he was Vice-President of researchon design methodologies for Integrated Telecom Systems. This groupcreated the CATHEDRAL suite of silicon compilation tools DSP chipsand the COWARE hardware-software co design systems. This workand the co-design of numerous telecom and multimedia chips haveresulted in 6 Spin-Off companies.

In 1995 he became a Senior Fellow of IMEC working on systemdesign technologies. His interests continue in Technology AwareDesign methods and education methods for SoC design.

Prof. De Man received best paper awards at ISSCC, ESSCIRC, ICCDand DAC and the 1985 Darlington Award of IEEE Circuits and SystemsSociety. In 1999 he received the Technical Achievement Award of theIEEE Signal Processing Society, The Phil Kaufman Award of the EDAConsortium and the Golden Jubilee Medal of IEEE CAS. In 2004 hereceived the lifetime achievement awards of the European Design andAutomation Association (EDAA) as well as the European ElectronicsIndustry. Since 2005 he has been Emeritus of the K.U. Leuven and isstill active as Senior Fellow of IMEC.

Prof. De Man is a Fellow of IEEE and a member of the Royal Acad-emy of Sciences, Belgium.

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Recipients of the IEEE Solid-State CircuitAwards

IEEE Donald O. Pederson Technical Field Awardin Solid-State Circuits2006 Mark A. Horowitz

IEEE Solid-State Circuits Technical Field Award 2005 Bruce A. Wooley2004 Eric Vittoz2003 Daniel Dobberpuhl2002 Chenming Hu and Ping Ko2001 No Award2000 Robert H. Krambreck and Stephen Law1999 Kensall D. Wise1998 Nicky Lu1997 Robert W. Brodersen1996 Rudy J. van de Plassche1995 Lewis M. Terman1994 Paul R. Gray

1993 Kiyoo Itoh1992 Barrie Gilbert1991 Frank Wanlass1990 Toshi Masuhara1989 James D. Meindl

Solid-State Circuits Council Development Award1988 Karl Stein1987 Robert Widlar1986 Barrie Gilbert1985 Donald O. Pederson

The IEEE Solid-State Circuits Tech-nical Field Award was created in1989 and was renamed the IEEEDonald O. Pederson TechnicalField Award in 2006. The awardsbefore 1989 were Solid-State Cir-cuits Council Award in Solid-StateCircuits.IEEE Pederson

Award Medal

Pioneer in Mixed Signal Circuits will Receive IEEEGustav Robert Kirchhoff Award at ISSCC 2007Yannis P. Tsividis to be honored in February for contributions to circuits and MOS devicemodeling.

Katherine Olstein, SSCS Administrator, [email protected]

Yannis P. Tsividis will receivethe IEEE Gustav RobertKirchhoff Field Award for

contributions to circuits and MOSdevice modeling at the plenary ses-sion of the ISSCC in San Francisco,CA on 12 February 2007. TheKirchhoff Award acknowledgesoutstanding contributions withlong-term impact to the fundamen-tals of any aspect of electronic cir-cuits and systems.

When Glenn E. R. Cowan, a Tsi-vidis graduate student at ColumbiaUniversity, recently applied for hisfirst position after receiving thePh.D., interviewers at IBM saw hiswork with Dr. Tsividis on mixed-sig-nal VLSI computing as something“different from the mainstream” andgave him an equally challengingresearch job. A fellow student,Cowan recalled in a telephone inter-view, developed a Tsividis idea onparametric amplifiers using a MOS

transistor as part of his Ph.D. project,presented it at ISSCC 2003, and wonthe conference best paper award.

A Lifetime of Long ShotsChallenge and cutting-edge riskhave characterized Dr. Tsividis’s

work throughout his career.“I changed Ph.D. topics twice

before I found one that excitedme,” he said in an email interview.“It was exactly the prejudice thatMOS ICs are only good for digitalthat presented a challenge to me. Istill recall an industrial visitor atBerkeley, who came to see what Iwas doing in my thesis work, andsaid, with some irony, ‘So, youwant to make amplifiers out ofswitches?’”

Today, the challenge of combin-ing different domains is theapproach to research that heenjoys most. “One of the pet proj-ects in my group is continuous-time DSPs, with no sampling oraliasing – admittedly a long shot,”he said.

Potential of Mixed SignalMOS Was Hard to ForeseeIn the mid-seventies, it was diffi-

“Like many EEs of my generation, Istarted as a child by building a crystalradio, and have been tinkering eversince.” Yannis P. Tsividis

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cult to get the idea of mixed signalMOS ICs accepted. “When Yannisbegan his graduate work around1970,” said Dr. Paul Gray, an earlycollaborator who is now ProfessorEmeritus and Professor in theGraduate School, EECS, UC Berke-ley, in an email statement, “bipolarwas used for virtually all analogintegrated circuits and most digitalcircuits, which were at low inte-gration levels at the time. MOS wasused for memory and was justbeginning to be used for somecomplex logic circuits.” CMOS wasin its infancy. “It was not easy tosee that MOS technology wouldbring about the need to integrateboth analog and digital on thesame chip. This backdrop madeMOS analog circuits a somewhatspeculative proposition.”

Career Breakthrough WasThe First Useful MOS Operational Amplifier “Working with Paul Gray, YannisP. Tsividis developed and demon-strated the world’s first useful MOSoperational amplifier,” said DaveHodges, Professor of Engineering,EECS, UC Berkeley, via email. “Itwas fundamental to the develop-ment of mixed signal MOS inte-grated circuits, which provide vast-ly higher levels of circuit integra-tion than bipolar analog devices,”the prior mainstream technology.

Before CMOS was fully devel-oped, the implementation of highgain op amps in NMOS was a realchallenge, Hodges said. “Yanniscame up with some circuit ideas toovercome this” using NMOS-onlytechnology. Yannis’s most lastingcontribution to the usefulness ofCMOS was his work on the adap-tation of weighted-capacitor A/Dconversion techniques to a specialkind of converter used for voice,called a companding coder. Heand others first demonstrated thistechnique, which became verywidely used in telephone systemsaround the world in the 1980’s and1990’s.”

Subsequent milestones, Tsividissaid, have been “the work my stu-dents and I did on switched-capac-itor circuit analysis and simulation;our techniques for automaticallytuned integrated continuous-timefilters; and our work related to pre-cision MOS modeling for analogand mixed-signal design.”

Dr. Tsividis, who is an IEEE Fel-low, has received two best paperawards from the IEEE Circuits andSystems Society, as well as theIEEE-wide Baker best paperaward.

Master TeacherThe recipient in 2005 of the IEEEUndergraduate Teaching Award,Dr. Tsividis is unusual amongprominent researchers for hisenthusiasm about teaching at thislevel. “I find it extremely reward-ing,” he said. “I have created afirst-year undergraduate class,‘Introduction to Electrical Engi-neering,’ where we mix circuitsand electronics and attempt tomake students tinker. The idea isto make them excited and motivat-ed about what they will be learn-ing in their follow-up classes. Justto show you how rewardingundergraduate teaching can be, letme tell you a story from that class.The class has a heavy lab compo-nent. During an experiment onamplifiers, a student comes to meand says, ‘I see how, if I put a sig-nal in, I get a signal out, and if I donot put a signal in, I get nothingout. What would happen if I tookthe output signal and used it as the

input?’ That student had re-invent-ed oscillators right on the spot.”

In order to reach undergradu-ates, a professor “must be willingto find ways to explain things intu-itively to the students – not justthrow a bunch of equations atthem,” Tsividis said. “The key is tomake the math interesting, bymaking clear why it’s useful.Dumping the first circuits class onanybody in an EE department hasoften had disastrous results in themotivation of students – I’m sureour field has lost some of the bestminds because of this,” he said.

Interdependence ofResearch and Teaching “Whenever I want to really under-stand an area different from mine,I ask to teach a class in it,” Tsividissaid. “This is how I learned aboutDSPs, communications, signals andsystems, and semiconductordevices. Only when I am forced toexplain something carefully to oth-ers, do I understand it fully.” As forhis graduate students, he aimsespecially “to strike the right bal-ance between helping them andchallenging them to come up withtheir own solutions.”

Shanthi Pavan, a recent TsividisPh.D., who is now an assistantprofessor at the Indian Institute ofTechnology in Madras, India, saidin an email that he remembersespecially Prof. Tsividis’s “infec-tious enthusiasm,” “clarity,” “metic-ulous feedback,” and “virtually lim-itless patience.” Dr. Cowan wouldconcur. “I don’t think people candecide to become great teachers,”he said. ”It has to come from theheart.”

Yannis Tsividis received the Bach-elor’s degree in electrical engi-neering from the University ofMinnesota in Minneapolis in 1972,and the MS and Ph.D. degrees,also in electrical engineering, fromthe University of California atBerkeley in 1973 and 1976. He isCharles Batchelor Memorial Pro-

Kirchhoff Medal

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fessor of Electrical Engineering atColumbia University in New York,and has taught at the University ofCalifornia, Berkeley, MIT, and theNational Technical University ofAthens.

Dr. Tsividis began his career bydemonstrating the feasibility ofMOS mixed-signal circuits. In 1976,at a time that MOS was considereda digital integrated circuit technolo-gy, he designed and built a fullyintegrated MOS operational ampli-fier and demonstrated its use in aPCM codec. These results werewidely adopted by the industry inthe first massively produced mixed-signal MOS ICs. Together with hisstudents, he has since made manyother contributions at the device,circuit, system and simulation level.

These include techniques for fullyintegrated analog filters, whichhave been used in very large vol-ume products such as disc drivesand consumer electronics;switched-capacitor circuit theoryand simulation, with the resultingsoftware program Switcap widelyused for such systems in the earlydays of MOS telecom ICs; com-panding analog filters; discrete-time parametric circuits; mixedanalog-digital VLSI computation;and precision MOS device model-ing, with benchmarks incorporatedinto IEEE standards for judgingcompact models. His book, “Oper-ation and Modeling of the MOSTransistor” is a standard referencein the field. His most recentresearch effort involves 0.5 V ana-

log/RF MOS circuits, and analog-inspired digital signal processingtechniques, including continuous-time digital filters which operatewithout aliasing, and digital filterswhich use internal companding.

A Fellow of the IEEE, Dr. Tsividisis the recipient of the 1984 IEEEW.R.G. Baker Best Paper Award,the 1986 European Solid-State Cir-cuits Conference Best Paper Award,the 1998 IEEE Circuits and SystemsSociety Guillemin-Cauer Best PaperAward, and the 2005 IEEE Under-graduate Teaching Award, and co-recipient of the 1987 IEEE Circuitsand Systems Society DarlingtonBest Paper Award and the 2003IEEE International Solid-State Cir-cuits Conference L. Winner Out-standing Paper Award.

IEEE Educational Innovation Award to FiezTekBots® Named But Only Hint At Her Wide Ranging Talents

Terri Fiez, Chair of EE atOregon State Universi-ty, was presented with

the 2006 IEEE EducationalActivities Board Major Educa-tional Innovation Award “forundergraduate engineeringeducation innovation throughcreation and development ofPlatforms for Learning ® andits implementation in the elec-trical and computer engineer-ing curriculum through theTekBots® program.” Profes-sor Fiez developed the pro-gram at OSU in Corvalis, Ore-gon over the last decade.

Dr. Jim Hellums, TI Fel-low, who supervises fundingof research at academic insti-tutions, visits the Oregon campusand has watched many of the Plat-forms for Learning develop. TIfunds a number of graduateresearch projects managed by Fieztoday and has provided equipmentfor the program. “It would be eas-ier to develop and launch a new

program in industry than at a Uni-versity because of the bureaucracyand inertia. Some people who did-n’t want to do it just don’t. Even asa Department Head at a Universityone has to convince and cajole. Itis a Herculean effort.”

Hellums remembers that David

J. Allstot, Fiez’s graduateadvisor at Oregon State Uni-versity, predicted in 1988that she would be a star.Terri had only completedher masters when she wasfirst presenting her researchreport at ISSCC and Allstothad recommended that Hel-lums be sure to meet herbecause she was the bestamong the Allstot’s gradu-ate students.

Allstot, now Chair of EE atUniversity of Washington,recalls that “From the time Ifirst met Terri, it was clearthat she was a ball of fire.She has a great personalityand is naturally comfortable

in the academic environment,whether as a student, professor, oradministrator. Terri is equally goodat strategic and tactical thinking.“

Hellums recalled that Allstot hadjust proposed a robotics course atOSU in the 90s and had found notakers to expand the program

(l to r) Moshe Kam, IEEE VP Educational Activities,Terri Fiez, and Bruce Eisenstein, Awards CommitteeChair Educational Activities, in New Orleans on 24November 2006 during the BoD Meeting Series whenFiez received the Major Educational InnovationAward of the IEEE Educational Activities Board.

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about the time he left OSU for Ari-zona. Fiez came on campus, tookthe course and grew the TekBotprogram, “got it done and made itsuccessful. Then she enlarged thescope to the Platforms for Learning,which is all hers. It’s her vision andexcitement that gets it developed.“

Allstot recalls, “I'm guessing here,but I don't think she got interestedin robots until she became Head ofECE at OSU. There was a freshmanrobot course sequence that hadbeen put in place at OSU oneyear prior to her arrival. It wasbased on the freshman robotcourse that CMU ECE haddeveloped a few years earlier,but had some innovative addi-tions including enrolling somestudents from the local highschools. But, it was just a start.The next step in the thinking,as I understand it, was to deter-mine a way for those coursesto impact the entire undergraduatecurriculum. One idea was toinvolve seniors in capstone projectsthat improved the robots and alter-natives to them for the freshmansequence would be developed, aswell. Of course, this left the uncom-fortable two-year robot-free gapbetween the Freshman and Senioryears. This is the kind of situationwhere Terri shines. She conceivedthe “Platform for Learning” idea sothat the first-year robot experiencewas continued throughout theundergraduate years, and centeredaround a central theme that moti-vated upper level classes. Thismeant adding capabilities to theFreshman robots such as wirelesscommunications and control, etc.As is typical of Terri, she had agood idea and she found a way todescribe it in very simple, but pow-erful terms that everyone couldunderstand. This is really importantfor encouraging younger kids to getinvolved in Electrical Engineering.”

“This also presented an oppor-tunity for Terri to shine in anotherway. To be successful, she knewthat significant resources would be

needed to incorporate the Platformfor Learning into their undergradu-ate curriculum. So, she presentedthe idea to Tektronix, Inc., andgarnered critical support by adopt-ing the ‘TekBots’ moniker for theprogram. On the surface, such amove might appear to be hype.However, it is far more significantthan that. Previous to Terri'sarrival, the Freshman Robotsequence culminated in a so-called

‘Robot Rodeo’ that was open to thegeneral public, especially prospec-tive students and their families.That term was almost pejorative, inmy opinion, because it conjuredup the old ‘cow college’ image thatOregon State had in the early dayswhen it was Oregon AgriculturalCollege. It certainly didn't suggestleading-edge high-technology edu-cation and research. With the sim-ple twist of a phrase, TekBots,Terri conveyed the message that itwas really leading-edge robotlearning that had critical supportfrom the local high-tech industry,”recalls Allstot.

Fiez emphasized that “thisaward really recognizes an amaz-ing team. Over the last six years,we have had a core team of DonHeer (Education coordinator),Roger Traylor (senior instructor),Gale Sumida (Research and Edu-cation Support), Tom Thompson(Math and Science education PhDstudent and Philomath HighSchool teacher). Together, it hasbeen a thrill working with the fac-ulty and students in our depart-ment to create a unique experi-

ence that addresses what seemedto be missing in our own educa-tional experiences.”

Nowadays, Hellums reportsgoing to other schools and encour-aging them to pick up the Plat-forms for Learning program. “I tryto sell her idea.” The TekBots Plat-form for Learning has been imple-mented in eight engineering cours-es at OSU at the freshman throughsenior levels and is used by five

other institutions.The concept includes two

critical elements that aim tokeep freshman and sopho-mores involved and staying inan EE program, Hellumsreports. “It deals with thechallenges of the major beingtoo hard or too boring andgets over that sophomorehump,” said Hellums. Firstrobot implementations oftenend up looking like the OSU

mascot – a Beaver with whiskersthat sense objects and back upmove around them. By workingwith applications of theory, sens-ing, seeing, reacting and moving,the students realize what engineersdo in their career and see it can befun. They also work in teams. Hel-lums recalls that there was nothingdone in teams when he was a stu-dent but industry always works inteams, often fairly large teams. Sothe students learn early on to findtheir place in a team.

Kartikeya Mayaram, professor atOregon State University, and along time research collaboratorwith Fiez, sees definite differencesin the graduate students who havecome from the Learning Platformscurriculum. “They are ready to hitthe ground running. They arealready very good at trouble shoot-ing. They have skills that enablethem to do independent researchand basically they are moreresourceful in terms of knowingwhere to go and how to find infor-mation. That’s a very valuable setof skills to come with to graduateschool.”

“She had a good idea and shefound a way to describe it in

very simple, but powerfulterms, that everyone could

understand.” Dave Allstot

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Allstot points out that as aresearcher “Terri has made signifi-cant research contributions tooversampled data converters andsubstrate noise analysis tech-niques. She has made tremendouscontributions to the high-technol-ogy industry by advising manystudents who are prepared to ‘hitthe ground running’ in their jobs.She’s made important educationalinnovations, and her impact atOregon State cannot be overstat-ed. She has done a lot at many dif-ferent levels.”

Mayaram outlines how Fiez’sprogram has permeated much ofthe EE Curriculum. “Fiez is veryinvolved with the Platforms forLearning and works with a coreteam examining the curriculum.They look for critical points thatthe curriculum would benefitfrom the platforms methodology,and develop a straw man propos-al. So the core team does a lot ofthe ground work before theyactually go and talk with the fac-ulty. Then it’s an interactiveprocess at that point. ProfessorRoger Traylor who teaches thefreshman introductory course, isalready very involved in the Tek-Bot program. They have a goodidea of what’s going on in a classand they make a proposal forwhat makes sense in particularlabs. When the team has thoughtit out that well, it’s a lot easier forthe faculty to jump on board. Theteam takes on a lot of the detailwork which can be a stumblingblock if each faculty member isleft on their own.”

“Terri is natural leader. She iscreative, full of new and innova-tive ideas. She is down to earth,values people and that makes avery nice work environment. Interms of research and mentoring

her students she’s a great personand her students love her. Shekeeps in touch with most of hergraduate students long after theyhave graduated and been work-ing for ages. She advises themeven at later stages in theircareer,” Mayram notes.

Allstot says, “Terri has it all. Sheis technically talented with a raregift for leadership. Mark down thisprediction: She will be a universitypresident in the future. She is thatrare star who is approachable andlikable by all, mainly, I think,because it is always clear beingaround her that she really loveswhat she does. She has a greatsense of humor that she uses effec-tively in her presentations and inperson. Most important, she has alife. She is well balanced between

her family and professional inter-ests, more so than me and most ofour colleagues.”

Allstot asked Fiez, “Why do youobviously enjoy it so much?” Fiezreplied, “I can't think of a moresatisfying career. The opportunitiesfor creativity, working with stu-dents to find their way, new tech-nologies that will change theworld, learning and laughing. Ihave been very lucky all through-out my career to work with won-derful people who are passionateabout what they do. These includemy graduate advisors, Gary Makiand Dave Allstot, and my graduatestudents, undergraduates, the fac-ulty and staff in my School andRon Adams, OSU EngineeringDean. I can't think of a day notfilled with laughter!”

Terri S. Fiez (’82, M’85, SM’95, F’05)received the B.S. and M.S. degrees inelectrical engineering from the Uni-

versity of Idaho, Moscow, in 1984 and 1985respectively. In 1990 she received the Ph.D.degree in electrical and computer engineer-ing from Oregon State University, Corvallis.From 1985 to 1988 she worked at Hewlett-Packard Corporation, in Boise and Corvallis.She was on the faculty at Washington StateUniversity from 1990 to 1999. In 1999, shejoined the Department of Electrical andComputer Engineering at OSU as Professor

and Department Head. She became Director of the School of Elec-trical Engineering and Computer Science in 2003.

Dr. Fiez has participated extensively in IEEE activities including:IEEE International Solid-State Circuits Conference (2000-2006),IEEE Custom Integrated Circuits Conference (1994-1998), IEEETransactions on Circuits and Systems II Associate Editor (1995-1997), IEEE Journal of Solid-State Circuits Guest Editor (1997-1998)and IEEE CAS Distinguished Lecturer (2002-2004). Fiez receivedthe National Science Foundation Young Investigator Award andthe IEEE Solid-State Circuit Predoctoral Fellowship. She was elect-ed Fellow of the IEEE in 2005 “for contributions to analog andmixed-signal integrated circuits.”

Dr. Terri S. Fiez

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Sixteen outstanding members ofSSCS have accepted the Soci-ety’s invitation to join its Distin-

guished Lecturer Program. They are

Dennis FischetteIan GaltonAli HajimiriTadahiro KurodaJohn R. LongAkira MatsuzawaSreedhar NatarajanBram NautaClark T. C. NguyenMehmet SoyuerMircea R. StanToshiaki MasuharaKen UchidaAlbert J. P. TheuwissenRoland ThewesIan Young

Each will serve a two-year term,from 1 January 2007 through 31December 2008.

“The new additions to the DLlist increase our representation inAsia and Europe to better serve thechapters in their respective com-munities,” said C. K. Ken Yang,SSCS Education and DL ProgramChair. “The list of DLs covers abroad range of current topics.Local chapters can leverage thisresource for their activities andtechnical meetings,” he said.The Society’s DL Roster nowtotals 33 lecturers. It is available atsscs.org/Chapters/dl.htm.

Dennis Fischette isa Senior Member ofthe Technical Staff atAdvanced MicroDevices (AMD) inSunnyvale, CA. In1986 he graduated

from Cornell University, Ithaca,NY, with B.S. degree in Engineer-ing Physics and then studied theHistory of Science at the Universi-

16 New Speakers Will Diversify the SSCSDistinguished Lecturer Program

SSCS DLs Tour the IEEE Far East Shanghai and Beijing Chapters Host Inaugural Programson 15-18 November


The first SSCS Distinguished Lecturer Tour took place in the Far East(IEEE Region 10) on 15-18 November, 2006, immediately after the A-SSCC. The Shanghai and Beijing chapters each hosted a segment of thetour, which was initiated by SSCS DL Program Chair C.K. Ken Yangand coordinated by Dr. Zhihua Wang, Chair of SSCS-Beijing. The pro-grams included presentations by Drs. Tom Lee, Vojin Oklobdzija, BettyPrince and Marcel Pelgrom.

“The SSCS Far East DL Tour in Shanghai was very successful,” saidDr. Ting-Ao Tang, SSCS-Shanghai chair. “When we announced thisactivity, we received more than 100 return receipts asking to attend theworkshop. On the afternoon of November 16th, 180 crowded theroom.”

The Society is planning a second Distinguished Lecturer tour inEurope (IEEE Region 8) for the fall of 2007.

In Beijing, an appreciative audience gathered to hear SSCS DL’s Marcel Pelgromand Betty Prince (left) and Tom Lee and Vojin Oklobdzija (at right). Dr. ZhihuaWang (center) hosted the event, which took place at Tsinghua University.

At Fudan University, Shanghai (from left): Professors Anquan Jiang, HuihuaYu, Yinyin Lin, and Ting-AoTang, with Vojin Oklobdzija, C.K. Ken Yang, TomLee, Betty Prince, and Prof. Zhiliang Hong.

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ty of California, Berkeley. From1988 to 1991 he worked for Inte-grated CMOS Systems Sunnyvaleon device and circuit modeling.From 1991 to 1996 he worked forHal Computer Systems, Campbell,CA on clock synthesizers and cir-cuit design automation.

Before joining AMD, he workedfor Chromatic Research, Sunnyvaleon clock synthesizers, D/A circuits,and memories. His technical inter-ests include PLL and DLL design,clock-and-data recovery, circuitanalysis software, and high-speedIO circuits. He was a member ofthe ISSCC Digital Program Commit-tee from 2001-2006 and created anonline course on PLL Design forthe IEEE Expert Now program in2005. In his spare time, Dennis isan active jazz musician whorecently performed in China andVietnam.

Ian Galton receivedthe Sc.B. degreefrom Brown Univer-sity in 1984, and theM.S. and Ph.D.degrees from theCalifornia Institute

of Technology in 1989 and 1992,respectively, all in electrical engi-neering. Since 1996 he has been aprofessor of electrical engineeringat the University of California, SanDiego where he teaches and con-ducts research in the field ofmixed-signal integrated circuitsand systems for communications.Prior to 1996 he was with UCIrvine, and prior to 1989 he waswith Acuson and Mead Data Cen-tral. His research involves theinvention, analysis, and integratedcircuit implementation of criticalcommunication system blockssuch as data converters, frequencysynthesizers, and clock recoverysystems. In addition to his aca-demic research, he regularly con-sults at several semiconductorcompanies and teaches industry-oriented short courses on thedesign of mixed-signal integrated

circuits. He has served on a corpo-rate Board of Directors, on severalcorporate Technical AdvisoryBoards, as the Editor-in-Chief ofthe IEEE Transactions on Circuitsand Systems II: Analog and DigitalSignal Processing, as a member ofthe IEEE Solid-State Circuits Soci-ety Administrative Committee, as amember of the IEEE Circuits andSystems Society Board of Gover-nors, and as a member of the IEEEInternational Solid-State CircuitsConference Technical ProgramCommittee.

Ali Hajimiri receivedthe B.S. degree inElectronics Engi-neering from theSharif University ofTechnology, and theM.S. and Ph.D.

degrees in electrical engineeringfrom the Stanford University in1996 and 1998, respectively.

He has had appointments withPhilips Semiconductors, SunMicrosystems, and Lucent Tech-nologies (Bell Labs) in the past. In1998, he joined the Faculty of theCalifornia Institute of Technology,Pasadena, where he is a Professorof Electrical Engineering and thedirector of Microelectronics Labora-tory. His research interests are high-speed and RF integrated circuits.

Dr. Hajimiri is the author of TheDesign of Low Noise Oscillators(Boston, MA: Kluwer, 1999) andholds several U.S. and Europeanpatents. He is a member of theTechnical Program Committee ofthe International Solid-State Cir-cuits Conference (ISSCC). He hasalso served as an Associate Editorof the IEEE Journal of Solid-StateCircuits (JSSC), an Associate Editorof IEEE Transactions on Circuitsand Systems (TCAS): Part-II, amember of the Technical ProgramCommittees of the InternationalConference on Computer AidedDesign (ICCAD), Guest Editor ofthe IEEE Transactions onMicrowave Theory and Tech-

niques, and the Guest EditorialBoard of Transactions of Instituteof Electronics, Information andCommunication Engineers ofJapan (IEICE).

Dr. Hajimiri was selected to thetop 100 innovators (TR100) list andis a Fellow of Okawa Foundation.He is the recipient of Caltech'sGraduate Students Council Teach-ing and Mentoring award as well asAssociated Students of CaltechUndergraduate Excellence inTeaching Award. He was the Goldmedal winner of the NationalPhysics Competition and theBronze Medal winner of the 21stInternational Physics Olympiad,Groningen, Netherlands. He was aco-recipient of the IEEE JSSC BestPaper Award of 2004, the Interna-tional Solid-State Circuits Confer-ence (ISSCC) Jack Kilby Outstand-ing Paper Award, two times co-recipient of CICC's best paperawards, and a three times winner ofthe IBM faculty partnership awardas well as National Science Founda-tion CAREER award. He is acofounder of Axiom MicrodevicesInc. and member of SSCS AdCom.

Tadahiro Kuroda(M’88-SM’00-F’06)received the Ph.D.degree in electricalengineering from theUniversity of Tokyo,Tokyo, Japan, in 1999.

In 1982, he joined Toshiba Cor-poration, where he designedCMOS SRAMs, gate arrays andstandard cells. From 1988 to 1990,he was a Visiting Scholar with theUniversity of California, Berkeley,where he conducted research inthe field of VLSI CAD. In 1990, hewas back to Toshiba, and engagedin the research and developmentof BiCMOS ASICs, ECL gate arrays,high-speed CMOS LSIs fortelecommunications, and low-power CMOS LSIs for multimediaand mobile applications. Heinvented a Variable Threshold-volt-age CMOS (VTCMOS) technology

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to control VTH through substratebias, and applied it to a DCT coreprocessor and a gate-array in 1995.He also developed a Variable Sup-ply-voltage scheme using anembedded DC-DC converter, andemployed it to a microprocessorcore and an MPEG-4 chip for thefirst time in the world in 1997. In2000, he moved to Keio University,Yokohama, Japan, where he hasbeen a professor since 2002. Hehas been a Visiting Professor atHiroshima University, Japan, andthe University of California, Berke-ley. His research interests includelow-power, high-speed CMOSdesign for wireless and wirelinecommunications, human computerinteractions, and ubiquitous elec-tronics. He has published morethan 200 technical publications,including 50 invited papers, and 18books/chapters, and has filedmore than 100 patents.

Dr. Kuroda served as the Gener-al Chairman for the Symposium onVLSI Circuits, the Vice Chairmanfor ASP-DAC, sub-committeechairs for A-SSCC, ICCAD, andSSDM, and program committeemembers for the Symposium onVLSI Circuits, CICC, DAC, ASP-DAC, ISLPED, SSDM, ISQED, andother international conferences.He is a recipient of the 2005 IEEESystem LSI Award, the 2005 P&IPatent of the Year Award, and the2006 LSI IP Design Award. He is anIEEE Fellow and an IEEE SSCS Dis-tinguished Lecturer.

John R. Long re-ceived the M.Eng.and Ph.D. degreesin Electronics fromCarleton University,Canada in 1992 and1996, respectively.

He worked for 10 years at Bell-Northern Research, Ottawa (nowNortel Networks) designing ASICsfor Gbit/s fibre systems, and for 5years as a faculty member at theUniversity of Toronto. He joinedthe faculty at the TU Delft in Janu-

ary 2002, where his currentresearch interests include: low-power transceiver circuitry forhighly-integrated radios and elec-tronics design for high-speed datacommunications. Professor Longcurrently serves on the programcommittees of the ISSCC, ESSCIRC,IEEE-BCTM and GAAS 2004, and isa past Associate Editor of the IEEEJournal of Solid-State Circuits.

Toshiaki Masuhara(S768-M’69-SM’90-Fellow’94), Associa-tion of Super-Advanced Electron-ics Technologies(ASET), was born on

Mar. 5, 1945 in Osaka, Japan. Heobtained B.S., M.S. and Ph.D.degrees in Electrical Engineeringfrom Kyoto University, Kyoto, Japanin 1967, 1969 and in 1977, respec-tively. From 1969 to 1974, he was amember of the technical staff, 3rdand 7th Department at Hitachi Cen-tral Research Laboratory(CRL),Kokubunji, Tokyo, Japan, where heworked on depletion-load NMOSintegrated circuits and on modelingof sub-threshold characteristics ofMOS transistors. From 1974 to 1975,he was a special student, Depart-ment of Electrical Engineering andComputer Science, University ofCalifornia, Berkeley where heworked on double-diffused MOStransistors and a new CMOSprocess. In 1975, he returned toHitachi CRL and worked on newhigh speed CMOS SRAM. In 1987,he became department manager,7th Dept., Hitachi CRL, developingmemories, microprocessors, digitalsignal processors and high frequen-cy silicon devices. He then becamethe manager of the 1st Dept. in1990, performing research on highspeed GaAs and bipolar ICs andmaterials. From 1991 to 1993, hewas in Telecommunications Divi-sion, Hitachi, where he was respon-sible for the design of telecomICs.He became General Manager,Technology Development Opera-

tion (Center) in 1993, General Man-ager, Semiconductor ManufacturingTechnology Center, Semiconductor& IC Div. in 1997, and then becameSenior Chief Engineer, Semiconduc-tor Group, Hitachi. In 2001, heassumed his current position, Exec-utive Director, MIRAI Project, Asso-ciation of Super-Advanced Electron-ics Technologies (ASET).He is amember of IEEE and IEICE, Japan.He became a fellow of IEEE in 1994with the citation, ”For contributionin the invention and the develop-ment of NMOS circuits and high-speed CMOS memories”. He wasthe program co-chair and the chairin 1992-, 1993-, and general co-chairand chair in 1996- and 1997-VLSICircuit Symposium. He was anelected member of the Administra-tive Committee, SSCS from 1998 to2000.He received IEEE Solid-StateCircuit Technical Field Award on hiscontribution to NMOS depletion-load circuits and the developmentof high speed CMOS memories in1990 and the IEEE third MillenniumMedal in 2000. He has received aSignificant Invention Award, Japanin 1994, four Significant InventionAwards, Tokyo, Japan in 1984, 1985,1988 and 1992, Significant InventionAwards, Yamanashi, Japan in 1995and Gumma, Japan in 1996.

Akira Matsuzawareceived B.S., M.S.,and ph. D. degrees inelectronics engineer-ing from TohokuUniversity, Sendai,Japan, in 1976, 1978,

and 1997 respectively. In 1978, hejoined Matsushita Electric IndustrialCo., Ltd. Since then, he has beenworking on research and develop-ment of analog and Mixed Signal LSItechnologies; ultra-high speedADCs, RF CMOS circuits, and digitalread-channel technologies for DVDsystems. From 1997 to 2003, he wasa general manager in advanced LSItechnology development center. OnApril 2003, he joined Tokyo Instituteof Technology and he is a professor

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on physical electronics. Currently heis researching in mixed signal tech-nologies. He has published 30 tech-nical journal papers and 50 interna-tional conference papers. He is co-author of 9 books. He holds 34 reg-istered Japan patents and 65 US andEPC patents. He received the IR100award in 1983, the R&D100 awardand the Remarkable Inventionaward in 1994, and the ISSCCevening panel award in 2003 and2005. He now serves SSCS AdCommembers and he is an IEEE Fellowsince 2002.

Sreedhar Natara-jan is currently serv-ing as the Founder& CEO of EmergingMemory Technolo-gies (EMT) Inc. Hefounded EMT in

Dec 2004, which in a short periodhas grown to become a successfulleading design services and memo-ry IP provider under his leadership.Prior to EMT, his industry experi-ence comes from working at MoSys,Texas Instruments and ParadigmTechnologies in the area of SRAM,DRAM, Memory Compilers and SOI.Mr. Natarajan serves on the Adviso-ry Board of Diablo TechnologiesInc, Solido Design Automation andHS Memory Inc. He also serves onvarious international conferencetechnical committees like ISSCC,CICC, VLSI, ESSCIRC, ISLPED, SOCand VLSI Symposium. He co-authored the book “SOI Design:Analog, Memory and DigitalDesign” – Dec 2001, Kluwer Acade-mic Publishers and is also the recip-ient of the IEEE Circuits and SystemsOutstanding Service Award'01.

Dr. Natarajan was named among‘Top 40 under 40’ individuals bythe Ottawa Business Journal in2005. This awards program honorsindividuals throughout the Ottawabusiness community that embodythe region’s entrepreneurial spiritand business acumen, while at thesame time balancing communityand charitable involvement. He has

been a leading advocate to inno-vate and promote new memorytechnologies in the industry and isworking with many academic andindustry organisations to promotefuturistic memory technologies. Mr.Natarajan obtained his Master’sdegree in computer engineeringfrom University of Southwestern,Lafayette, LA. He is a IEEE Distin-guished Lecturer for 2007-2008 anda Senior member for the Institute ofElectrical and Electrical Engineers.

Clark T.-C. Nguyenreceived the B.S.,M.S., and Ph.D.degrees from theUniversity of Califor-nia at Berkeley in1989, 1991, and

1994, respectively, all in ElectricalEngineering and Computer Sci-ences. In 1995, he joined the facultyof the Department of Electrical Engi-neering and Computer Science atthe University of Michigan, AnnArbor, to which he has very recent-ly returned after a 3.5 year leave inWashington, DC, where he servedas the MEMS Program Manager inthe Microsystems Technology Office(MTO) of DARPA. His technicalinterests at Michigan focus on microelectromechanical systems (MEMS)and include integrated vibratingmicromechanical signal processorsand sensors, merged circuit/micro-mechanical technologies, RF com-munication architectures, and inte-grated circuit design and technolo-gy. Prof. Nguyen and his students atMichigan have garnered numerousBest Paper Awards at prestigiousconferences, including the 1998 and2003 IEEE Int. Electron DevicesMeetings, the 2004 IEEE UltrasonicsSymposium, the 2004 DARPA TechConference, the 2004 IEEE CustomIntegrated Circuits Conference, the2005 IEEE Int. Solid-State CircuitsConference, and the 2005 IEEE Fre-quency Control Symposium.

In 2001, Prof. Nguyen foundedDiscera, Inc., a company aimed atcommercializing communication

products based upon MEMS tech-nology, with an initial focus on thevery vibrating micromechanicalresonators pioneered by hisresearch in past years. He servedas Vice President and Acting ChiefTechnology Officer (CTO) of Dis-cera from 2001 to mid-2002.

In mid-2002, Prof. Nguyen went onleave from the University of Michiganto join the Microsystems TechnologyOffice (MTO) of DARPA in Arlington,Virginia, where he served as a Pro-gram Manager in MEMS technology.At DARPA, from mid-2002 through2005, Prof. Nguyen created and man-aged a diverse set of programs thatincluded Microelectromechanical Sys-tems (MEMS), Micro Power Genera-tion (MPG), Chip-Scale Atomic Clock(CSAC), MEMS Exchange (MX), HarshEnvironment Robust Micromechani-cal Technology (HERMIT), Micro GasAnalyzers (MGA), Radio IsotopeMicropower Sources (RIMS), RFMEMS Improvement (RFMIP), Navi-gation-Grade Integrated Micro Gyro-scopes (NGIMG), and Micro Cryo-genic Coolers (MCC).

Bram Nauta wasborn in Hengelo,The Netherlands, in1964. In 1987 hereceived the M.Sc.degree (cum laude)in Electrical Engi-

neering from the University ofTwente, Enschede, The Nether-lands. In 1991 he received thePh.D. degree from the same uni-versity on the subject of analogCMOS filters for very high frequen-cies. In 1991 he joined the Mixed-Signal Circuits and Systems Depart-ment of Philips Research, Eind-hoven, The Netherlands, where heworked on high speed AD con-verters. From 1994 he led aresearch group in the same depart-ment, working on analog keymodules. In 1998 he returned tothe University of Twente, as fullprofessor heading the IC Designgroup in the MESA+ ResearchInstitute and department of Electri-

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cal Engineering. His currentresearch interest is analog CMOScircuits for transceivers. He is alsopart-time consultant in industryand in 2001 he co-founded ChipDesign Works. His Ph.D. thesiswas published as a book: AnalogCMOS Filters for Very High Fre-quencies, Kluwer, Boston, MA,1993. He holds 8 patents in circuitdesign and he received the "ShellStudy Tour Award" for his Ph.D.Work. From 1997-1999 he servedas Associate Editor of IEEE Trans-actions on Circuits and Systems -II;Analog and Digital Signal Process-ing, and in 1998 he served asGuest Editor for IEEE Journal ofSolid-State Circuits. In 2001 hebecame Associate Editor for IEEEJournal of Solid –State Circuits.

Mehmet Soyuerreceived the B.S.and M.S. degrees inelectrical engineer-ing from the MiddleEast Technical Uni-versity, Ankara,

Turkey, in 1976 and 1978. Hereceived the Ph.D. degree in elec-trical engineering from the Univer-sity of California at Berkeley in1988, subsequently joining IBM atthe Thomas J. Watson ResearchCenter, Yorktown Heights, NY as aResearch Staff Member. His workhas involved high-frequencymixed-signal integrated circuitdesigns, in particular monolithicphase-locked-loop designs forclock and data recovery, clockmultiplication, and frequency syn-thesis using silicon and SiGe tech-nologies. At IBM Thomas J. WatsonResearch Center, Dr. Soyuer man-aged the Mixed-Signal Communi-cations Integrated-Circuit Designgroup from 1997 to 2000. He wasthe Senior Manager of the Commu-nication Circuits and SystemsDepartment from 2000 to 2006. InMarch 2006, he has been promot-ed to the position of DepartmentGroup Manager, CommunicationTechnologies, at Thomas J. Watson

Research Center. Dr. Soyuer hasauthored numerous papers in theareas of analog, mixed-signal, RF,microwave, and nonlinear elec-tronic circuit design, and he is aninventor and co-inventor of eightU.S. patents. Since 1997, he hasbeen a technical program commit-tee member of the InternationalSolid-State Circuits Conference(ISSCC). He was an Associate Edi-tor of the IEEE Journal of Solid-State Circuits from 1998 through2000, and was one of the GuestEditors for the December 2003Special ISSCC Issue. Dr. Soyuerchaired the Analog, MEMS andMixed-Signal Electronics Commit-tee of the International Sympo-sium on Low Power Electronicsand Design (ISLPED) in 2001. Hewas also a technical program com-mittee member of the TopicalMeeting on Silicon Monolithic Inte-grated Circuits in RF Systems(SiRF) in 2004 and 2006. Dr.Soyuer is a senior member of IEEE.

Mircea R. Stanreceived the Ph.D.and M.S. degrees inElectrical and Com-puter Engineeringfrom the Universityof Massachusetts at

Amherst and the Diploma in Elec-tronics and Communications fromPolitehnica University in Bucharest,Romania.

Since 1996 he has been with theDepartment of Electrical and Com-puter Engineering at the Universi-ty of Virginia, where he is now anassociate professor. Prof. Stan isteaching and doing research in theareas of high-performance low-power VLSI, temperature-awarecircuits and architecture, embed-ded systems, and nanoelectronics.He has more than eight years ofindustrial experience, has been avisiting faculty at UC Berkeley in2004-2005, at IBM in 2000, and atIntel in 2002 and 1999. He hasreceived the NSF CAREER awardin 1997 and was a co-author on

best paper awards at GLSVLSI2006, ISCA 2003 and SHAMAN2002. He is the chair of the VLSISystems and Applications Techni-cal Committee (VSA-TC) of IEEECAS, was general chair for ISLPED2006, technical program chair forISLPED 2005, general chair forGLSVLSI 2003, and has been ontechnical committees for numer-ous conferences.

He has been an Associate Editorfor the IEEE Transactions on Cir-cuits and Systems Systems since2004 and for the IEEE Transactionson VLSI Systems in 2001-2003. Hehas also been a Guest Editor forthe IEEE Computer special issueon Power-Aware Computing inDecember 2003 and a Distin-guished Lecturer for the IEEE Cir-cuits and Systems Society for 2004-2005. Prof. Stan is a senior memberof the IEEE, a member of ACM,IET, and also of Eta Kappa Nu, PhiKappa Phi and Sigma Xi.

Albert J.P. Theuwis-sen was born inMaaseik, Belgium onDecember 20, 1954.He received thedegree in electricalengineering from

the K.U. Leuven, Belgium in 1977.His thesis work was based on thedevelopment of supporting hard-ware around a linear CCD imagesensor.

From 1977 to 1983, his work atthe ESAT-laboratory of the K.U.Leuven focused on semiconductortechnology for linear CCD imagesensors. He received the Ph.D.degree in electrical engineering in1983. His dissertation was on theimplementation of transparentconductive layers as gate materialin the CCD technology.

In 1983, he joined the Micro-Circuits Division of the PhilipsResearch Laboratories in Eind-hoven, the Netherlands as a mem-ber of the scientific staff. Sincethat time he was involved inresearch in the field of solid-state

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image sensing, which resulted inthe project leadership of respec-tively SDTV- and HDTV-imagers.In 1991 he became DepartmentHead of the division ImagingDevices, including CCD as wellas CMOS solid-state imagingactivities.

He is author or coauthor ofmany technical papers in the solid-state imaging field and issued sev-eral patents. In 1988, 1989, 1995and 1996 he was a member of theInternational Electron DevicesMeeting paper selection commit-tee. He was co-editor of the IEEETransactions on Electron Devicesspecial issues on Solid-State ImageSensors, May 1991, October 1997and January 2003, and of IEEEMicro special issue on DigitalImaging, Nov./Dec. 1998.

He acted as general chairman ofthe IEEE International Workshop onCharge-Coupled Devices andAdvanced Image Sensors in 1997and in 2003. He is member of theSteering Committee of the afore-mentioned workshop and founderof the Walter Kosonocky Award,which highlights the best paper inthe field of solid-state image sensors.

During several years he was amember of the technical commit-tee of the European Solid-StateDevice Research Conference andof the European Solid-State CircuitsConference.

Since 1999 he is a member ofthe technical committee of theInternational Solid-State CircuitsConference. For the same confer-ence he acted as secretary, vice-chair and chair in the EuropeanISSCC Committee and he is a mem-ber of the overall ISSCC ExecutiveCommittee.

In 1995, he authored a textbook“Solid-State Imaging with Charge-Cou-pled Devices”. In 1998 he became anIEEE Distinguished Lecturer.

In March 2001, he became part-time professor at the Delft Univer-sity of Technology, the Nether-lands. At this University he teach-es courses in solid-state imaging

and coaches PhD students in theirresearch on CMOS image sensors.

In April 2002, he joined DALSACorp. to act as the company’sChief Technology Officer. In Sep-tember 2004 he retired as CTO andbecame Chief Scientist of DALSASemiconductors. This shift allowshim to focus more on the field oftraining and teaching solid-stateimage sensor technology.

In 2005 he founded ETETIS(European Technical Expert Teamon Image Sensors), a non-profitorganization to promote EuropeanR&D activities in the field of solid-state image sensors.

He is member of editorial boardof the magazine “Photonics Spec-tra”, an IEEE Fellow and memberof SPIE.

Roland Thewes wasborn in Marl, Ger-many, in 1962. Hereceived the Dipl.-Ing. degree and theDr.-Ing. degree inElectrical Engineer-

ing from the University of Dort-mund, Dortmund, Germany, in1990 and 1995, respectively. From1990-1995, he worked in a cooper-ative program between the SiemensResearch Laboratories in Munichand the University of Dortmund inthe field of hot-carrier degradationin analog CMOS circuits.

Since 1994 he was with theResearch Laboratories of SiemensAG and Infineon Technologies,where he was active in the designof non-volatile memories and inthe field of reliability and yield ofanalog CMOS circuits. From 1997-1999, he managed projects in thefields of design for manufacturabil-ity, reliability, analog device per-formance, and analog circuitdesign. From 2000-2005, he wasresponsible for the Lab on Mixed-Signal Circuits of CorporateResearch of Infineon Technologiesfocusing on CMOS-based bio-sen-sors, device physics-related circuitdesign, and advanced analog

CMOS circuit design. Since 2006,he is heading a department devel-oping DRAM Core Circuitry atQimonda.

He has authored or co-authoredsome 120 publications includingbook chapters, tutorials, invitedpapers, etc., and he gave lecturesand courses at universities. Heserved as a member of the techni-cal program committees of theInternational Reliability PhysicsSymposium (IRPS), and of theEuropean Symposium on Reliabili-ty of Electron Devices, FailurePhysics and Analysis (ESREF). Heis a member of the technical pro-gram committees of the Interna-tional Solid-State Circuits Confer-ence (ISSCC), of the InternationalElectron Device Meeting (IEDM),and of the European Solid StateDevice Research Conference (ESS-DERC). Moreover, in 2004, hejoined the IEEE EDS VLSI Technol-ogy and Circuits Committee.

Dr. Thewes is a member of theIEEE and of the German Associa-tion of Electrical Engineers (VDE).

Ken Uchida wasborn in Cambridge,MA in 1971. Hereceived B.S. degreein physics, M.S. andPh.D. degrees inapplied physics all

from the University of Tokyo,Tokyo, Japan, in 1993, 1995, and2002, respectively. In 1995, hejoined the Research and Develop-ment Center, Toshiba Corporation,Kawasaki, Japan. He has studiedcarrier transport properties innano-scaled devices such as Sin-gle-Electron Devices, Schottkysource/drain MOSFETs, Ultrathin-body SOI MOSFETs, Strained SiliconMOSFETs, and Carbon NanotubeTransistors. He developed thephysics-based compact model ofsingle-electron transistors and thedesign scheme of single-electronlogic circuits. He investigated thephysical mechanisms of mobilityenhancement in uniaxial stressed

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This article is reprinted fromthe May/June 2002 issue ofthe IEEE Professional Com-

munication Society Newsletter, vol.46, Number 3, pages 15-16 with thepermission of the authors and RudyJoenk, PCS newsletter editor.

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By Peter and Cheryl Reimold, www.allaboutcommunication.com

MOSFETs and clarified the impor-tance of the effective mass change.In addition, he experimentallydemonstrated the effectiveness ofsubband structure engineering inultrathin-body SOI MOSFETs. Dr.Uchida is a member of the JapanSociety of Applied Physics and IEEEElectron Devices Society. He wonthe 2003 IEEE EDS Paul RappaportAward for his work on single-elec-tron devices and 2005 Young Scien-tist Award from Ministry of Educa-tion, Culture, Sports, Science andTechnology of Japan.

Ian Young was born in Melbourne,Australia. He received the BSEE in1972, and the M. Eng. Science in1975, specialized in MicrowaveCommunications, from the Universi-

ty of Melbourne. Hereceived the Ph.D. inElectrical Engineer-ing from the Univer-sity of California,Berkeley, in 1978,where he was one of

the pioneers of the switched capaci-tor filter in MOS technology.

In 1983 he joined the Technol-ogy Development group at IntelCorporation, where he is cur-rently an Intel Senior Fellow andDirector of Advanced Circuitsand Technology Integration. Histechnical contributions havebeen recognized in the design ofDRAMs and SRAMs, processtechnology development andmicroprocessor implementations,the design of Phase Locked

Loops for microprocessor clock-ing and high speed I/O andmixed-signal RF CMOS circuitsfor communications.

He was a member of the Pro-gram Committee for the Sympo-sium on VLSI Circuits from 1991 to1996, serving as the Program Com-mittee Co-Chair/Chairman in 1995and 1996, and the Symposium Co-Chair/Chairman in 1997/1998. Hecurrently serves on the ExecutiveCommittee of the VLSI Symposia.Since 1992 he has been a memberof the ISSCC Technical ProgramCommittee, serving as the DigitalSubcommittee Chairman from1997 through 2003, Technical Pro-gram Committee Vice-chair in 2004and Chair in 2005. Dr Young is anIEEE Fellow.

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PEOPLE


want to evaluate the validity of yourapproach. It follows a logical pro-gression, from an overview (summa-ry) to the background (introduc-tion), to your method, to a discus-sion of anything interesting thatoccurred, and then to your results.The conclusions and recommenda-tions grow directly out of the results.

The management format usesthe same categories but rearrangesthem to allow general managementreaders to get the information theywant in the beginning, without hav-ing to read detailed sections.

You may not always need a sec-tion on method; this depends on thenature of your work and your read-ership. You may decide to give amore specific title to the discussionsection if it covers only one topic.Otherwise, these sections work formost technical reports.

The summary provides theessence of your report, preferably innontechnical terms. It should givegeneral answers to all your readers’most urgent questions, but the pri-mary reader here is usually theexecutive. Think broad brushstrokes. A good outline for theopening summary is the PAW: Pur-pose, Achievement, What Next. Fora discussion of the PAW, see the firstcolumn in this series (May/June2002 Newsletter, p. 10).

The introduction explains whatled to the work you did. It is anamplification of the purpose statedin the summary. To keep your intro-duction brief and interesting, consid-er your readers. How much back-ground do they want and need? Tell

them only that.The approach/method opens

with a summary of the key points ofthe method—points that couldinterest both management and tech-nical readers. The rest of the sectiontells your technical readers how youproceeded.

The discussion requires informa-tive subheadings. Use a clear sub-head for each topic you explore.Open each topic with a summaryparagraph that states your mainmessage. Then consider which read-ers will be most interested in thattopic. Note what questions theywould have and try to answer them.If you have more to tell, state it afteryou have answered their questions,or put it in an appendix.

The results state simply whatyou found. It is best to present themas a bulleted list. (This stops youfrom adding long interpretations,which don’t belong here.) Forexample:• The five-pound roast was no

longer on the counter. • The dog was under the table,

looking unwell. The conclusions are your deduc-

tions from the results. They, too,work well as a bulleted list. Theyshould grow clearly out of theresults. For example:• The dog ate five pounds of raw

beef. The recommendations state what

to do next. They should grow direct-ly out of your conclusions. Forexample:• When preparing roast beef,

close the kitchen door, making

sure the dog is outside thekitchen.

The appendixes consist of materi-al that is not critical for understand-ing your report but might be usefulin the future. Make sure that eachpage has enough information on itto make it self-explanatory.

Finally, here are two points thatapply to all sections:1. In each section and subsection,

move from the most to theleast important information,unless some other logicalscheme (e.g., chronology, leftto right, top to bottom, causalsequence) clearly makes thesection easier to understand.

2. Once you introduce severalitems in a certain order, stick tothat order in the rest of thereport.

Follow these simple rules, andyour readers will thank you formaking your report easily accessi-ble and readable.

Cheryl and Peter Reimold havebeen teaching communicationskills to engineers, scientists, andbusiness people for 20 years. Theirlatest book, “the Short Road to GreatPresentations” (Wiley, 2003), isavailable in bookstores and fromAmazon.com. Their consultingfirm, PERC Communications (1914 725 1024), [email protected]),offers business consulting and writ-ing services as well as customizedin-house courses on writing, pres-entation skills, and on-the-job com-munication skills. Visit their Website at www.allaboutcommunica-tion.com.”

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SSCS has awarded a record$35,603.96 in subsidies to arecord 30 chapters for 2007-

2008. The maximum allotment wasdoubled, in an AdCom vote lastAugust, from $1000 to $2000 for singleand new joint chapters, and from $500to $1000 for established joint chapters.

Chapter subsidy awards are usedprimarily to fund distinguished lec-turer seminars, chapter-level con-ferences and short courses andworkshops. They also underwritemembership promotion, network-ing, and web development.

The chief events to be subsi-dized next year exemplify therange of benefits that chapters pro-vide to local and regional IC pro-fessionals and students.

Chapter Workshops FosterLocal Business InitiativesIn Shanghai, many IC design com-panies have sprung up, especially inSOC design and manufacturing.Therefore, the chapter is planningtwo seminars for spring, 2007 tointroduce new methodologies to theIC community and to strengthen therelationship between academia andindustry. As many as eighty atten-dees are expected at each event.

About 30 engineers from indus-try and academia will come togeth-er in a two-day workshop spon-sored by the Finland/ Estonia chap-ter on 19-20 August, 2007. Moreinformation about this event, theseventh in a series, may be foundat http://isc.dcc.ttu.ee/ws.htm.

Chapter Seminars EnhanceStudent SkillsSSCS-Bangalore, a chapter with125 members, will devote SSCSsubsidy funds to two one-dayworkshops for undergraduate andgraduate students on advances andissues in devices and circuits. Eachwill take place at a local engineer-ing college and involve faculty andstudents in addition to invited

speakers. The Bangalore chaptersubsidy will also help to fund the10th VLSI Design and Test Work-shop in cooperation with the VLSISociety of India on 10-13 August.

West Ukraine is planning“Pidstryhach Readings,” a RegionalConference of Students and YoungScientists, and will also use SSCSsubsidy funds to sponsor awards atthe student scientific congress ofthe Institute of Telecommunica-tions, Radioelectronics, and Elec-tronic Engineering. SSCS-Sofia willconduct a competition in electron-ics design for high school studentsand support student activities atthe Technical University of Varna.

In Novosibirsk, the SSCS studentchapter and Novosibirsk-SSCS/EDStogether sponsor the annual Inter-national Workshop and Tutorial onElectron Devices and materials(EDM). This event will take placefor the eighth time in July.

The Society’s new chapter inPavia, Italy will use the SSCS sub-sidy to fund two two-day shortcourses in April and June onswitched-capacitor filters, MEMStechnology, data converters andmicrosensor interfaces for telecom,sigma-delta converters, and CMOSoff-chip drivers. The courses will beapproved for Ph.D. students by theMicroelectronics PhD Course Advi-sory Board at the University ofPavia, and will also serve studentsfrom the Polytechnic University ofMilan and the University of Genovaand Parma, among other schools.

Chapter-Sponsored AnnualConferences PromoteRegional AdvancementsSponsored by SSCS-Central Ukraineevery year and aided by SSCS sub-sidy funds, the Crimean MicrowaveConference (CriMiCo) regularlyattracts 350 attendees in the fall.The West Ukraine chapter organizesthe annual “Modern Problems ofRadio Engineering, Telecommunica-

tions and Computer Science”(TCSET) conference and the Inter-national Seminar/Workshop onDirect and Inverse Problems ofElectromagnetic and Acoustic WaveTheory (DIPED). The InternationalConference on Microelectronics(MIEL), sponsored by SSCS/ED-Ser-bia Montenegro with the aid of SSCSmonies, annually draws an audi-ence from over 30 countries in thespring. In Germany, two Multi Pro-ject Chip Workshops are held everyyear with the help of subsidy funds.Next year, the Novosibirsk Jointchapter will cosponsor the annualconference of the Russian A.S.Popov Radio Engineering Society.

Chapter-Sponsored Techni-cal Meetings Educate LocalCommunitiesVancouver will use its first-eversubsidy award for five talks featur-ing three local and two invitedspeakers. The chapter hopes todouble its membership during 2007on the basis of these meetings andan upgraded website. The newPhoenix chapter is planning a localworkshop in mid-February. SSCS-Ireland’s subsidy will contributetowards the IEEE InternationalAnalog VLSI Workshop in Cork.SSCS-Hong Kong will present a“Symposium on Solid-State Devicesand Novel Techniques for Biosens-ing Applications” next April. Andthe Novosibirsk Joint chapter willsponsor the first Russian IEEE Sem-inar on Solid-State Sensors, Actua-tors and Microsystems (MicroSys‘2007) in December. It will alsohost a seminar on Nanotechnologyin Electronics and participate in anAll-Russia Chapter Chairs Congress.

More information about the SSCSChapter Subsidies may be found at:sscs.org/Chapters/subsidy.htm.Information about the SSCS ExtraChapter Subsidy Program may befound at: sscs.org/Chapters/sub-sidy-extra.htm.

SSCS Awards $35,000 in Chapter SubsidesKatherine Olstein, SSCS Administrator, [email protected]

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Far East Chapters Meet in Hangzhou, ChinaInaugural SSCS Regional Meeting on 15 November, 2006

Jan Van der Spiegel, Chapters Committee Chair, [email protected]

The first SSCS regional chap-ters’ meeting was held in con-junction with the A-SSCC in

Hangzhou, China on 15 November,2006. The goal of the Far East meet-ing in IEEE Region 10 was to bringtogether chapter officers, societyrepresentatives and regional leadersto share experiences about bestchapter practices, to provide infor-mation on chapter support services,and to stimulate further chapterdevelopment in Asia. The meetingwas highly successful and resultedin a good dialogue among chapterand society representatives.

Professor Zhihua Wang of theBeijing Chapter hosted the eventand made the local arrangementswhich ensured a very smooth andwell run meeting. Six chapterswere represented: Beijing Chapter (Prof. Z. Wang)Hong Kong Chapter (K-P. Pun)

Seoul Chapter (J. Chung and S-I. Lim)Singapore Chapter (Y-P. Xu)Shanghai (T.A. Tang) and Taipei Chapter (H-S. Lin).

Several SSCS Society representa-tives attended: R. Jaeger (Presidentof the SSCS), Jan Van der Spiegel(Chapters Chair), Ken Yang (Chairof the Education Committee) andAnne O’Neill (Executive Director).In addition, three Far East digni-taries were present: Nicky Lu (A-SSCC Steering committee andTechnical Program Co-Chair), C.K. Chang (A-SSCC Steering Com-mittee), and X. Yan (Dean, EE Col-lege of Zhenjian University). Also,two Distinguished Lecturers partic-ipated: Betty Prince and VojinOklobdzija.

After the luncheon, Professor R.Jaeger welcomed all participants,congratulated the chapter chairs onan outstanding job and stressed the

important role chapters play in bring-ing educational and professionalbenefits to the local membership.Professor Van der Spiegel gave anoverview of SSCS Chapter growthand activities in Region 10. ProfessorKen Yang talked about the Distin-guished Lecture Program and the DLtour in Region 10 immediately fol-lowing the A-SSCC, on 15-18 Novem-ber. Anne O’Neill reviewed adminis-trative aspects, educational opportu-nities and financial aspects of chap-ters. During the remainder of themeeting, chapter representativesgave brief overviews of their respec-tive chapter activities. The meetingconcluded with a boat tour on thebeautiful West Lake, followed by atraditional Chinese dinner.

The Society plans to hold a sec-ond regional chapter meeting inSeptember, 2007 in conjunctionwith ESSCIRC.

From left, Kong-Pang Pun of The Chinese University of Hong Kong, Voijin Oklobdzija of University of Sydney , BettyPrince of Memory Strategies International, C.K. Ken Yang of UCLA, Yong Ping Xu of the National University of Singapore,Zhihua Wang of Tsinghua University, Ting-Ao Tang of Fudan University, Richard C. Jaeger of Auburn University, AnneO’Neill of IEEE SSCS, Andy Jinyong Chung of Puhang University of Science and Technology, Jan Van der Spiegel of Uni-versity of Pennsyvlania, C. K. Wang of National Taiwan University, Nicky Lu, of Etron Technology, Shin Il Lim of Korea’sMinistry of Commerce, Industry and Energy, and Hsung- Hsien Lin of National Taiwan University.

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Professor Vojin Oklobdzija, anIEEE Fellow and Distin-guished Lecturer of the IEEE

Solid-State Circuits Society gave aseminar entitled “Future of Micro-processors: Retrospective andChallenges” to the electronic andcomputer communities in West-ern Australia on Monday, 6November, 2006. The venue wasthe Innovation Centre WA at theTechnology Park in Bentley.Twenty five researchers and pro-fessionals from Perth attended thelecture.

In his talk, Professor Oklobdz-ija presented a retrospective ofmodern microprocessor develop-ment. He addressed advances inenabling technology that havebrought unprecedented growthand gave a perspective for futuredevelopment. The features whichhave enabled the developmentof modern microprocessors,guiding principles and contribu-tions made by modern micro-processor architecture were dis-cussed, as well as the move intosuper-scalars with respect to per-formance and implementationdifficulties.

Professor Oklobdzija thenaddressed the one billion transistorchallenge and the impact of thecomputer entry into consumermarket, representing new poten-tials and new challenges. An inter-esting discussion between Profes-sor Oklobdzija and the partici-pants, and among the participantsthemselves, followed the talk and

continued outside at a reception inhis honor provided by the IEEElocal section.

On the next day, ProfessorOklobdzija gave the keynoteaddress "Directions in ComputerEngineering" at the 7th Post Grad-uate Electrical Engineering Com-puter Symposium (PEECS) forresearchers and postgraduatesfrom the four Western AustralianUniversities. The Symposium wasorganized by Associate ProfessorLance Fung, who is the IEEE West-ern Australia Section Chair. Morethan 100 participants filled theauditorium.

Professor Oklobdzija put thecomputer engineering disciplineinto a historical perspective andshowed how computers haveseen an unprecedented expansionsince the first electronic comput-ers were built some 50 years ago.He later explained how comput-ers are playing a major part in ourlives and are fuelling economic

growth. He then outlined majormilestones and achievements incomputer development and con-tinued by showing trends andsharing his view on where growthand expansion in this area may beexpected. At the end, he offeredsome recommendations for theuniversity computer engineeringprograms.

The visit of Professor Oklobdz-ija to Western Australia conclud-ed with a discussion about a pro-posal to initiate a new joint IEEEchapter of SSCS and EDS, whichshould become two distinctchapters later. Current develop-ments in the research communi-ties in Western Australia in thefields of microelectronics, pho-tonics, solid states and electrondevices with new nanotechnolo-gy and nanomaterial for applica-tions such as military, medical,and general sensing applicationsjustify the establishment of a newIEEE chapter.

V. Oklobdzija Offers IEEE DL Talk and KeynoteAddress to PEECS Symposium in Western AustraliaMicroprocessors in the Past and Future Explored at November Meetings

By Adam Osseiran, Edith Cowan University, [email protected]

From left, Dr. Vojin Oklobdzija, Dr. Adam Ossieran, and Dr. Lance Fung.

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In the past year, the DenverSSCS Chapter hosted eightmonthly seminars, including

four by SSCS Distinguished Lectur-ers. These talks spanned a varietyof exciting developments in ICdesign, cutting-edge CMOS tech-nology, and high-speed test.

In the first seminar of 2006, Dr.Victor Chan of IBM gave a veryinformative overview of state-of-the-art strain and substrate engi-neering techniques to enhancechannel mobility in bulk and SOICMOS. In February, Dr. OsvaldoBuccafusca of Avago Technolo-gies, who is also the Chair of theIEEE Centennial Subsection thatcovers northern Colorado andsouthern Wyoming, described thechallenges and implementation ofa very high-speed optical samplingoscilloscope for characterization ofoptical serial links. Adam Healeyof Agere Systems, Chair of theIEEE 802.3ap Standards Commit-tee, built on this theme with a dis-cussion of 10 Gigabit Ethernet overbackplane interconnects. Thistopic is of significant interest to themany Fort Collins IC designersdealing with high-speed electricaldata links. Stefan Rusu presentedthe next talk on Intel’s Dual-CoreXeon® Processor. Abstracts andslides for all lectures are available

at the Chapter’s website. Dr. Marcel Pelgrom of Philips

Research visited Fort Collins inMay to deliver our first Distin-guished Lecture of the year. A pio-neering expert on transistor vari-ability, he delivered an insightfultalk on the analog challenges asso-ciated with nanometer CMOS.Given its relevant nature, Dr. Pel-grom's seminar drew a chapterrecord attendance of 120!

The next DL seminar was givenby Dr. Kiyoo Itoh of Hitachi Cen-tral Research Laboratory, whospoke about ultra-low voltagenano-scale embedded RAMs. Dr.Itoh emphasized the importance offully-depleted SOI technology asan enabling solution to overcome

device mismatch and allow forultra-low voltage operation. Prof.Boris Murmann was the nextspeaker, coming from StanfordUniversity to discuss the impor-tance of digital techniques to com-pensate for analog limitations,such as nonlinearity and variabili-ty, in sub-100nm CMOS.

In August, Prof. Behzad Razavivisited from the University of Cali-fornia at Los Angeles. His muchanticipated seminar covered someexciting new developments on the60GHz RF CMOS transceiver frontand discussed design and modelingchallenges in that domain. Not sur-prisingly, Prof. Razavi’s renownedauthorship drew quite a trail forautographs. Thanks to members-at-large Herman Pang and MichaelGildorf of Avago Technologies formaking possible our first ever semi-nar recorded on DVD. The DVDwill be available to chapters, uponrequest.

Following a social event inNovember, the year ended with aninth lecture by Sam Naffziger ofAdvanced Micro Devices, whospoke on high-performance proces-sors in a power-limited world. Fort

Denver Hosts Technical Seminars on Cutting-EdgeCMOS Technology and High-Speed TestAlvin Loke, Denver Chapter Chair, [email protected], Bob Barnes, Denver Chapter Vice Chair &Treasurer, [email protected], Tin Tin Wee, Denver Chapter Secretary & Webmaster,[email protected]

Alvin Loke, Denver Chapter Chair,presented an award of appreciationto Dr. Pelgrom.

The Distinguished Lecturer seminar by Dr. Marcel Pelgrom attracted an audi-ence of 120 at Fort Collins, CO on 11 May 2006.

The Society distributed this DVD as atechnical treat to attendees at theSociety’s Far East Chapters Luncheonand Meeting in November.

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Collins has quickly become ahotbed of leading-edge micro-processor activity with AMD recent-ly opening its brand new Mile HighDesign Center to match Intel’sestablished presence in Itaniumdevelopment.

We regret to announce that PastChair Dr. Don McGrath decided tostep aside from chapter activities,

having been overwhelmed by hisresponsibilities at LSI Logic. Wewish to extend our best wishes tohim and heartfelt thanks for hisinstrumental leadership and com-mitment to grow this young chap-ter for several years soon after itsinception in late 2002. We are alsograteful to our past speakers, espe-cially those who traveled from dis-

tant places and undoubtedly busyschedules to support our humbleservice to the northern Coloradodesign community. Finally, wewelcome Bruce Doyle who recent-ly joined the existing officer team.

Please visit ewh.ieee.org/r5/den-ver/sscs/ for more information,including past presentation slides,about our chapter events.

Herman Pang (far left) and Mikail Gilsdor (second from right, second row) video taped Dr. Razavi’s talk on 1 August, 2006.Dr. Razavi is eighth from right, front row. A. Loke and Tin Tin Wee, Chapter Secretary and Webmaster, are to his right.

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The successful Asian Solid-State Circuits Conference inNovember, 2006 in Hangzhou,

China was organized with a core of107 papers selected by an interna-tional program committee. Theacceptance rate was 32% with a con-ference audience of 260 registeredattendees. CK Wang, the SteeringCommittee chair of A-SSCC, report-ed that the conference was quitesuccessful both “in terms of paperquality and foreign attendees with82 from Japan, 48 from Taiwan, and39 from Korea.” Prof Wei ofTsinghua University and local hostfelt that it was the first high qualityand world class conference held inChina. The tutorials that began theconference were open at no cost toany students in attendance.

Three papers, announced aswinners of the Student DesignContest, were awarded at A-SSCC.The competition, in cooperationwith the ISSCC, includes trans-portation for the lead studentresearcher to the ISSCC February2007 in San Francisco, for thepapers to be included in the

ISSCC poster session. The A-SSCCstudent design contest finalistsare selected from regular accept-ed papers that are authored bystudents. Only the realizeddesigns, not simply simulations,are selected and invited todemonstrate the operation of thechips on-site. It is not a contestwith a single specification orapplication, but rather a contestfor the completeness of develop-

ment and demonstration of thefabricated integrated circuit. Thepapers, co-authors, and abstractsare listed below.

(I) A TCAM-based Periodic EventGenerator for Multi-Node Manage-ment in the Body Sensor NetworkSungdae Choi, Kyomin Sohn, Jooy-oung Kim, Jerald Yoo and Hoi-JunYoo (KAIST)

A low-power periodic events gen-eration is essential for a node con-troller in the network system withcentralized control and the timerinterrupt generation for variousdevices in a CPU. The proposedTCAM-based periodic event gener-ator manages the issuing eventswith the programmed value andthe number of the events is equalto the number of the word line ofthe TCAM block. The NAND-typeTCAM cell operates with as low as0.6V supply voltage and the low-energy match line prechargereduces the search line transitionwhich causes most of the searchenergy dissipation. The imple-mented event generator consumes184-nJ energy to schedule eventsof 255 nodes for 24-hours, which isless than 10% of energy consump-tion of conventional hardwaretimer blocks.

The Second A-SSCC Considers Challenges for the e-Life

Gathered for the opening plenary of the A-SSCC in Hangzhou are(l-r) ProfTadahiro Kuroda of Keo University and Chair of the Invited Program Commit-tee, Nicky Lu of Etron Technology and Chair of Conference Industry Program,Richard C. Jaeger of Auburn University and President SSCS, Richard Chang, thePresident of Semiconductor Manufacturing International Corporation andChair of the Technical Program, and C.K. Wang of National Taiwan Universityand Conference Steering Committee Chair.

Winners of the A-SSCC 2006 student design contest were (from left) first, Sung-dae Choi of KAIST, Seoul, second Mr. Yusaku Ito of the Tokyo Institute of Tech-nology, and third Mr. Simone Gambini Simone Gambini and Jan Rabaey of theUniversity of California at Berkeley. Presenting the awards is Prof. Hoi-JunYoo, Chair of Design Contest.

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(2) A 0.98 to 6.6 GHz TunableWideband VCO in a 180 nmCMOS Technology for Reconfig-urable Radio TransceiverYusaku Ito, Hirotaka Sugawara,Kenichi Okada and Kazuya Masu(Tokyo Institute of Technology)

This paper proposes a novel wide-band voltage-controlled oscillator(VCO) for multi-band transceivers.The proposed VCO has a core LC-VCO and a tuning-range extensioncircuit, which consists of switches, amixer, dividers, and variable gaincombiners with a spurious rejectiontechnique. The experimental results

exhibit 0.98-to-6.6GHz continuousfrequency tuning with -206dBc/Hzof FoMt which is fabricated by usinga 0.18um CMOS process. The fre-quency tuning range (FTR) is 149%,and the chip area is 800µm x 540µm.

(3) A 1.5MS/s 6-bit ADC with0.5V supplySimone Gambini and Jan Rabaey(University of California at Berkeley)

A moderate resolution analog-to-digital converter targeting wirelesssensor networks applications ispresented. Employing a succes-sive-approximation architecture,

the device achieves 6 bits of reso-lution at 1.5 MS/s output rate,while drawing 28 microamps froma low 0.5 V supply, correspondingto a Figure of Merit (FOM) of.25pJ/conversion step. Low-densitymetal5-metal6 capacitors guaranteefeedback DAC linearity while min-imizing input capacitance, whilethe use of a passive sample andhold, combined with a class-ABcomparator reduce analog powerdissipation to 4 microWatts (30% ofthe total). The analog core is oper-ational for supply values as low as.3V, even though sampling rate isreduced to 175kS/s.

Invitation from the ISSCC 2007 Technical ProgramChair

Iwould like to invite you to attendthe 54th ISSCC which will be heldin San Francisco on February 11-

15, 2007. The conference theme is“The 4 Dimensions of IC Innova-tion,” in recognition of the emergingsynergisms between the variousaspects of integrated circuit realiza-tion. There will be 243 outstandingpapers distributed over 31 technicalsessions covering advances in ana-log and digital circuits, data convert-ers, imagers, display and MEMS,memories, RF building blocks, tech-nology directions, and wireless andwireline communications. A com-mon theme among many of thepapers is how to control power con-sumption in deep-submicron tech-nologies while pushing for higherperformance and functionality. Thisrequires careful optimization amongthe four dimensions of IC design(technology, devices, circuits, andarchitecture). Several papers willpresent new approaches or circuitsfor dealing with the power issue,while other papers will set new per-formance records.

Besides the regular paper ses-sions, the ISSCC will offer a widevariety of high-quality educationalprograms, adding to the alreadysignificant value of the ISSCC. This

year, there are ten Tutorials, sevenDesign Forums, and one ShortCourse. This year’s short coursedeals with the popular topic of“analog, mixed-signal, and RF cir-cuit design in nanometer CMOS”.

There are also three excellentplenary presentations. MorrisChang of TSMC will talk about thefuture and the challenges of siliconfoundries and how foundries willcontinue to be a driving force forthe semiconductor industry by pro-viding advanced technologies. Thesecond plenary presentation byLewis Counts of Analog Deviceswill focus on analog and mixed-mode circuit innovation in thenanoscale regime. The third talk byDr. Joel Hartmann of Crolles2Alliance will explain how increased

parameter variability in today’snanoscale technologies requires aglobal optimization among the fourdimensions of IC design.

There are also the traditionalevening sessions. One of theevening panels will discuss the“ultimate limits of ICs” whileanother will deal with “digital RF”.The panels bring together expertsand visionaries who share theirviews with the participants. Inaddition, seven special topics ses-sions will provide an opportunityto learn about an emerging topicin a relaxed setting.

As you can see, the upcomingISSCC continues its tradition ofpresenting the best in solid-statecircuits and providing an opportu-nity to learn about the latestdevelopments through its richchoice of educational activities. Inaddition, the ISSCC is a greatavenue to network, meet old col-leagues and make new friends. Iam sure you’ll enjoy the ISSCCand I hope to be able to welcomeyou in San Francisco.

Jan Van der SpiegelTechnical Program Chair, ISSCC

[email protected]

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Synergy between variousdimensions of integrated cir-cuits in the nano-electronic

era will be the theme of ISSCC2007. ISSCC is the flagship confer-ence of the Solid-State CircuitsSociety.

Balance Among Process, Circuit,Architecture, and System TechnologyAdvances Required for InnovationPushed by the continued growth ofMoore’s Law, integrated circuitshave evolved from the micro-elec-tronic into the nano-electronic era.This transition has created tremen-dous opportunities for higher-den-sity, higher-performance, lower-power circuits and systems result-ing in cost-effective solutions forubiquitous communications, com-putation, sensing, display, con-sumer electronics, and multimedia.However, the advent of the nano-era has blurred the traditionalboundaries between the fourdimensions of IC innovation (tech-nology, devices, circuits, and sys-tem architecture). As a result, inno-vation in solid-state circuits requiresan intricate balance amongadvances in process, circuit, archi-tecture and system technology.

Novel Circuit Concepts and Four-Dimension InterrelationshipsSelected for Technical ProgramPaper proposals for novel circuitconcepts and systems and explo-rations of the interrelationshipsamong the four dimensions of ICinnovation were especially soughtfor the Conference.

Within the resulting technicalprogram of 234 papers, fifty percentare devoted in nearly equal propor-tions to wireline, digital, wireless,and the combined category ofimagers, medical, MEMS and dis-

plays. Special topic sessions inthree of these technical areas willbe “Last-Mile Access Options:PON/DLS/Cable/ Wireless,” “SecureDigital Systems,” and “Implantableand Prosthetic Devices: Life-Chang-ing Circuits.” The Wireless sessionwill include a panel discussion enti-tled “Digital RF– A Fundamentally-New Technology, or Just MarketingHype?” and a forum, “Giraffe:Power Amplifiers and TransmitterArchitectures.” There will also be atutorial within each area.

In the area of data converterswe notice a shift into the 90nmregime with 1-1.2V supply voltagegiving rise to higher performanceand lower power consumption formultimode operations. The papersin the digital arena showcase 65nmtechnologies at clocking speed upto 5GHz. Power managementreceives special attention amongthe high performance digitalpapers. Circuits make furtherinroads into the medical area withimplantable brain probes, multi-channel high-resolution retinalprosthesis. CMOS imagers witnesscontinued shrinking of the pixelsize while improving performance,competing with CCD type ofimagers. Papers in the area ofTechnology Direction will show-case the next-generation, post-CMOS technologies and systems.

Special-Topic Sessions on Next-Generation Circuit DesignOn Sunday evening before the firstday of the Conference, two special-topic seminars addressing next-gen-eration circuit-design challengeswill be open to all attendees.

“Digitally Enhanced Analog andRF” will include four talks by BorisMurmann (Stanford University),Steve Lewis (UC, Davis), Larry Lar-

son (UC, San Diego) and Jan Cran-inckx (IMEC, Belgium), who willexplore challenges and trends inCMOS in scaling technologies:

As CMOS chip technologiesscale to finer line widths, smallerdevices, and lower voltages, ana-log circuit targets are harder toachieve due to larger device mis-match, non-ideal device character-istics, and limited voltage swing. Atthe same time, scaled technologiesreduce power and area, whileincreasing performance and lower-ing cost for digital circuits everyyear. These trends lead to the dis-placement of high linearity, highlyaccurate analog circuits by lowerperformance analog circuits. How-ever, digital signal processing tech-niques come to the rescue, result-ing in better performance, at lowercost and shorter design time.

“Circuit Design in the Year 2012”will be presented by David Frank(IBM, TJ Watson, Yorktown Heights,NY), Hae-Seung Lee (MIT), MarcelPelgrom (Philips Research, Eind-hoven, The Netherlands) andBorivoje Nikolic (UC, Berkeley).This special-topic-session will pro-vide a thorough overview of specialcircuit design considerations whichwill accommodate sub-32nm deviceidiosyncrasies. Four experts willshare their insight into issues con-fronting microprocessor and mixed-signal design in 2012 and offerpotential solutions.

Short Course for Entry-Level andExperienced Nanometer CMOSDesignersA Short Course organized by IanGalton entitled “Analog, Mixed-Sig-nal and RF Circuit Design inNanometer CMOS” will be offeredtwice, with staggered starting times.Instructors Matt Miller (Freescale

Solid-State Circuits Conference Will Focuson Nano-Era Synergy ISSCC 2007 to Meet on 11-15 February in San Francisco


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CONFERENCESSemiconductor), Bram Nauta (Uni-versity of Twente, The Nether-lands), Robert Bogdan Staszewski(Texas Instruments), and Michel S.J. Steyaert (Katholieke Universiteit,Leuven, Belgium) will each give alecture.

In this one-day session they willexplain the fundamental limitationsfaced by those designing criticalcommunication system blocks suchas amplifiers, mixers, data convert-ers, and phase-locked loops innanometer CMOS, and presentstate-of-the-art circuit and system-level techniques for addressingthese limitations. A DVD including(1) The visuals of the four Short-Course presentations in PDF for-mat; (2) Audio recordings of thepresentations along with writtentranscriptions; (3) Bibliographies ofbackground papers for all four pre-sentations; and (4) PDF copies ofselected relevant backgroundmaterial and important papers inthe field (10 to 20 papers per pres-entation) may be purchased at reg-istration time, or at the on-site reg-istration desk. A substantial pricereduction is offered to those whoattend the course.

Plenary Session At the opening of the conference,three invited speakers from indus-try will examine key considera-tions and offer roadmaps for tech-nical innovation.

“Foundry Future: Challenges inthe 21st Century” will be the topic ofMorris Chang, Founding Chairman,Taiwan Semiconductor Manufactur-ing Corporation, Hsinchu, Taiwan.

The foundry business-model isan important positive influence onthe health of the overall IC indus-try. Therefore, it is critically neces-sary to scan the future for potentialissues that might inhibit foundry-industry growth.

In order to ensure continuedexpansion, the foundry industrymust address two significant chal-lenges: The first and foremost chal-lenge is business growth: We antic-ipate that growth matching previ-

ous industry experience may bemore difficult to attain in thefuture, simply because revenuegrowth of the semiconductor ICindustry (as a whole) has slowedsince 2000, and will continue to doso. Additionally, the penetration ofthe CMOS-logic market by thefoundry industry cannot continueunabated indefinitely; saturationshould be anticipated in the future.

The second challenge for thefoundry industry is to maintainprofitability: The growth of theindustry has attracted many com-panies to offer foundry services.Consequently, competition be-tween these companies increasesthe potential for commoditizationof foundry services, where manyfoundries, with apparently similar(but substantively different) serv-ices, compete on the basis ofprice alone.

The foundry industry mustrespond to these challenges by twomeans: expanding into new IC-product markets enabled by thecost reduction and performanceincreases resulting from technologyscaling; and by penetrating seg-ments of the IC market that are cur-rently not involved in foundry rela-tionships, by broadening the rangeof technologies that are offered. Inthe future, circuit designers canexpect, therefore, to be able toaccess process technologies tunedin various ways: For memory, ana-log, high-performance-logic, orimage-sensor applications, as wellas for CMOS logic.

Lewis Counts, Vice-President ofAnalog Technology and FellowAnalog Devices, Wilmington, MA,will discuss “Analog and Mixed-Sig-nal Innovation: The Process-Circuit-System-Application Interaction.”

Innovation in analog and mixed-signal electronics becomes increas-ingly more important to the con-tinued growth of the IC industry.While technologists working in theanalog and mixed-signal arenashare, with their digital counter-parts, the overarching goal ofreducing power and cost-per-func-

tion in each IC generation, theymust also operate under physicalconstraints that, until recently,have been secondary in the digitalworld.

From the advent of the first ana-log IC, analog designers haveexploited the potential of processtechnology to develop circuits thatminimize the impact of variation inprocess parameters on productperformance. While process scalinghas enabled the development of awide variety of products, from cell-phones to advanced medical-imag-ing systems, the success of theseproducts depends in large measureon their ease of use, and seamlessconnection to wireless and wirednetworks. Analog and mixed-signalsubsystems, including display driv-ers, and WLAN and cellular radios,support these critical interfaces.The downward scaling of supplyvoltage in deep submicron CMOS(now at 1V), may limit dynamicrange, forcing some analog func-tions to be implemented on otherprocesses, but it has also enablednew circuit architectures that gainback dynamic range.

The creative combination ofprocess, design, and system archi-tecture in providing robust solu-tions for demanding applications,will prove to be even more crucialin the future. Such solutions willbe essential in meeting the chal-lenges posed by the physical reali-ties of deepsubmicron design inachieving gigahertz speeds, mini-mizing power consumption, andintegrating multiple functions insmaller packages.

Joel Hartmann, Director, Crolles2Alliance, STMicroelectronics, Crolles,France will explore the intricate bal-ance that will increasingly berequired among process, device,circuit, and system aspects ofdesign in “Toward a New Nanoelec-tronic Cosmology.”

Gone forever are the days ofsmooth roadmap scaling, with itsmore-or-less-simple design rules,adequate supply voltages, andunimpeded circuit shrinkage. As

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CONFERENCES


scaling moved ahead to nanometerdimensions, things changed:Devices became more difficult topredict, and global performancedegraded due to leakage and dis-persion. One of the consequencesof this deteriorating situation hasbeen that increased parametervariability has led to a significantmismatch between simulation andactual measurement results, at alllevels. While many of these effectshave already been well known toanalog designers, the surprise,now, is that they are more broadlyimportant, even in digital design,where previously available noisemargins have almost disappeared.

Clearly, deep understanding andmodeling of all underlying physical

causes is urgently required to guidethe right choices at all levels. Con-ceptually, such understanding willlead to acceptable levels of perform-ance, manufacturability, and yield, atever-decreasing feature sizes. Mean-while, the increased parameter vari-ability observed today, as one tech-nology node invites the next, revealsthe tight coupling of the four seem-ingly- independent dimensions ofdesign, motivating the need to con-figure a new nano-cosmology, onein which global optimization resultsonly from an intricate balancebetween the Process, Device, Cir-cuit, and System aspects of design.

In this new nano-cosmology, theemerging concept of GeneralizedDesign-for-Manufacturabi l i ty

(GDfM) unifies current Design-for-Manufacturability (DfM), Manufac-turing-for-Design (MfD), andDesign-for-Yield (DfY), couplingall of the above-mentioned dimen-sions within a new space wheretheir inter-dependence is revealedand exploited. Tightly coupledphysical-electrical-mechanical-process modeling and simulation,will allow early detection of theimpact of design choices at all lev-els. This creates a 4D knowledgecontinuum reminiscent of the ideasof General Relativity, onesextremely rich in consequences forthe future of nanoelectronic design.

More information about ISSCC2007 may be found at:http://www.isscc.org/isscc/.

Advances in Analogue Circuit Design Conference(AACD) Will Convene on 27-29 March 200716th Annual Workshop to Showcase European Expertise in Semiconductor Design Applications

Jan Craninckx, Chair, SSCS-Benelux, [email protected], Jan Sevenhans, SSCS Region 8 Representative,[email protected], Jan Van der Spiegel, SSCS Chapters Chair, [email protected]

The 16th annual AACD work-shop will be held on 27 – 29March, 2007 in the Hotel

Thermae Palace at the beautifulbeach resort of Oostende, Belgium.SSCS is a technical cosponsor of thisconference.

The Thermae Palace, a uniqueseaside hotel in Art Deco style, isconveniently located within walk-ing distance of the bustling Oost-ende city centre.

The three-day workshop willfeature 18 excellent speakers onthe following topics:• Sensors, Actuators and Power

Drivers for the Automotiveand Industrial Environment(Tue 27 March)

• Very High Frequency Front

Ends (Wed 28 March)• Integrated PA’s from Wire line

to RF (Thu 29 March)A panel discussion will be

organized every evening on thetopic of the day to ensure a livelyinteraction with the audience. TheAACD technical program commit-tee for 2007 consists of• Herman Casier, AMI Semicon-

ductor Fellow, Belgium• Michiel Steyaert, Catholic

University, Leuven• Arthur Van Roermund, Eind-

hoven University of Tech-nology.

Europe has expertise in a richvariety of semiconductor designapplications: high-reliability andhigh-voltage automotive, medicalfor hearing aids and bio sensors,space radiation hard circuits andtelecom mixed signal and multi-media, among others.

Each year, a European companytakes the initiative to support theAACD local and logistic organiza-tion to give the technical programcommittee leaders a free hand toinvite the best international speak-ers for this three-day summary ofadvances in analogue circuit

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design. This year, the AACD localorganisation is supported by theCommunication High Voltage Prod-uct group of AMI Semiconductor inBelgium, represented by Jan Sev-enhans PhD, IEEE fellow, and tech-nically co-sponsored by IMEC, Leu-ven, Belgium in cooperation withthe SSCS-Benelux chapter.

Willy Sansen (KU Leuven), JanHuijsing (TU Delft) and RudyVan de Plassche (Broadcom)started the AACD annual work-shop in 1992 with the goal ofbringing together analog circuitdesign experts in Europe. Theproceedings with full paper con-tributions have been publishedeach year summarizing the stateof the art.

Over the past 15 years, theAACD workshop has coveredtimely topics such as biomedicalcircuits and sensors, telecomwireline copper and fiber optics,wireless public and LAN mixedsignal systems on a chip, RF andbaseband analogue radio circuitsin bipolar and CMOS technolo-gies, DSL drivers, A/D & D/Aconverters, low noise amplifiers,etc. It has taken place inScheveningen, Leuven, Eind-hoven, Villach, Lausanne, Como,Copenhagen, Nice, Munich,Noordwijk, Spa, Graz, Montreux,Limerick and Maastricht.

It will be our pleasure to wel-

come a large group of silicon cir-cuit and technology engineers andresearchers involved in analogueand RF IC design in automotive,telecom and all industrial and

other applications for this 16thAACD!

More information may be foundat www.aacd.ws/ and [email protected]

From left, Jan Van der Spiegel, SSCS Chapters Chair (University of Pennsylva-nia), Jan Craninckx, SSCS-Benelux Chair (IMEC, Belgium), and Jan Sevenhans,SSCS Region 8 Representative (AMI Semiconductor).

From left, Dr. Van De Plassche, Dr. Sansen and Dr. Huijsing at the inauguralAACD conference in Scheveningen, The Netherlands, 1992.

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The SSCS membership re-elected five members tothe Solid-State Circuits Society AdministrativeCommittee (AdCom) for terms beginning 1 Jan-

uary, 2007. Jan Van der Spiegel and Thomas H. Lee were elect-

ed for a second term, and Kevin Kornegay and Hae-Seung (Harry) Lee were elected as new members. Theelection also returned John J. Corcoran to the AdComafter a year off.

The AdCom includes fifteen members elected bythe membership at large, with 5 members elected eachyear for a 3-year term. They meet twice a year, before

the ISSCC in February and again in the summer.The AdCom is responsible for overseeing Society

technical activities, conferences and publications, andfor initiating, developing and managing all Societyactivities. Stephen H. Lewis, SSCS past president andchair of the nominating committee, said that it recruit-ed individuals with a broad understanding of the fieldand its working engineers.

Biographies of the 2007 AdCom members were pub-lished in the July Newsletter and are available on line.www.ieee.org/portal/pages/sscs/06July/AcCom_Can-didates06.html

Corcoran, Kornegay, H. S.Lee, T. Lee, and Van der Spiegel Elected to SSCS AdCom

John J.Corcoran

KevinKornegay

Hae-Seung(Harry) Lee

Thomas H.Lee

Jan Van derSpiegel

Design Council Newsletter Completes Inaugural Year

The year-old IEEE Council onElectronic Design Automation(CEDA) updates interested

readers with its quarterly CEDA Cur-rents Newsletter. SSCS is one of sixfounding member societies of theIEEE Council, which is best knownfor sponsoring the Design Automa-tion Conference. In this first year ofpublishing CEDA Currents Newsletter,articles covered Logic Synthesis com-petition at IWLS, an interview withRobert Brayton, and opinion pieceson the state and need for formalverification.

The Currents Newsletter is avail-able in two formats, on line atwww.ieee-ceda.org, and as anembedded department within IEEEDesign & Test, abridged and edited to conform to thepublishing guidelines of that IEEE Computer Societymagazine. The standalone version of the newslettercarries content additional to the D&T embedded cov-erage; a column related to interviews, opinions,counter-opinions and matters of general interest tothe community. In addition, since the standalone ver-sion is published at a shorter schedule, it accommo-dates last minute listing of events and news. The

standalone version is distributedonline as well as in paper form atmajor CEDA events. The editors areKarti Mayaram ([email protected]) and Preeti Ranjan Panda([email protected]); Nanette Collins([email protected]) also serves assupport for IEEE CEDA’s broader out-reach activities.

In addition to Currents Newslet-ter, CEDA also publishes IEEETransactions on Computer AidedDesign which features in-depthtechnical articles for the re-searchers, and the Design & Testmagazine which features technicalarticles that have direct impact onindustrial practice.

Founding of CEDAThe Solid-State Circuits Society is a founding memberof the IEEE Council on Electronic Design Automation(CEDA). The SSCSC AdCom voted its support in Feb-ruary 2005. Bryan Ackland and Jan Rabaey serve asSSCS Representatives on the new CEDA governingbody whose President is Al Dunlop.

As a subject area, design automation has beenspread across a number of technical activities within

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SSCS NEWS

the IEEE. These activities range from monolithic cir-cuits to large information-processing systems. Withinthe context of electronic systems, computer-aideddesign (CAD) was synonymous with circuit simulationwhen it started as a discipline in the ‘60s. Now, CADdeals with a much broader set of concerns. Thoseissues continue to evolve with technological advancesin materials, processing, devices, and circuits. Gener-ally, they’re put under the umbrella of electronicdesign automation (EDA).

On one side of the spectrum, the physical design ofelectronic circuits requires both deep knowledge andinteraction with specialists on solid-state circuits andmore broadly electronic devices. Yet the ubiquitouspresence of programmable processor cores in integratedcircuits has shifted much CAD work into the design ofembedded software and hardware/software co-design--areas that are traditionally covered by computer scien-tists. By combining theory and practice, CAD is a keytechnology that boasts its own thriving industry. It alsois a driver for the much larger semiconductor and elec-tronic systems industry. It was natural for such an activ-ity to have a diversified footprint within the IEEE as atechnical organization. The range of CAD activitiesenabled the IEEE to benefit from the significant cross-fertilization of ideas from various mathematical and engi-neering optimizations and practices. As an organizedactivity, however, it was much harder for the organiza-tion to serve its members with information on interrelat-ed advances and publications. The recognition of majoradvances was often secondary to major society activities.

CEDA was ratified by IEEE as a Technical Council

effective January 2006. Within IEEE Technical Activi-ties, a council like CEDA represents an organizationwith member societies. CEDA has six IEEE membersocieties: Antennas and Propagation; Circuits and Sys-tems; Computer; Electron Devices; Microwave Theoryand Techniques; and Solid-State Circuits. As with anyIEEE technical activity, the ultimate goal is to advancethe profession through a variety of technical activitiesfrom conferences and publications to standards. Toserve members who are spread across various mem-ber societies, CEDA brings together several importantresources. It provides conferences and publications toits technical community. As of this writing, the co-sponsored conferences include DAC, ICCAD, andDesign and Test in Europe (DATE). CEDA enjoys spe-cial relationships with focused technical activities,such as DATC and TTTC in the Computer Society andCANDE within the Circuits and Systems Society.CEDA also is participating in the DARPA/MTO activi-ties in building the roadmap for electronic systems

Rajesh K. Gupta, the Vice President of Publicationsfor CEDA says, “Clearly, we’re pleased to receive suchbroad support and community momentum towardbuilding this new Council. We also are humbled bythe challenges facing the community, which mustmatch the pace of innovation by rapidly drawing newtalent and entrepreneurship to the field. We need toengender technical activities that excite and challengeour audience and readership to new capabilities andopportunities. From this promising start, we hope tobuild years of exciting innovation and invention inelectronic design automation.”

IEEE Undergraduate Teaching Award Nomination Deadline - January 31st

The IEEE Undergraduate Teaching Awardis a Technical Field Award of the Insti-tute established by the Board of

Directors in 1990 to honor teachers of elec-trical and electronics engineering and therelated disciplines, ‘for inspirational teach-ing of undergraduate students in the fieldsof interest of the IEEE.’

A primary goal of the IEEE is to ensure thatthe Institute Awards Program provides due recog-nition for superior achievement in the engineeringprofession. To that end, and in response to thedesire of the membership, the Awards Board, andBoard of Directors that the field of education bemore broadly recognized, this award for undergrad-uate teaching was added to the Awards Program.

Selection criteria include such contributionsas curriculum development, authorship ofcourse materials, involvement with stu-dents and faculty in advisory capacities, aswell as ‘attracting students to engineeringand scientific professions, and preparingthem for effective careers in engineering

and the sciences.’Recipient selection is administered by the

IEEE Awards Board through the Technical FieldAwards Council. It is presented to an individual only.

The award consists of a bronze medal, certificateand honorarium.

For a nomination form, list of past recipients andcommittee roster see:

www.ieee.org/awards/sums/ungrad.xml

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SSCS NEWS


The IEEE Graduate Teaching Award is aTechnical Field Award established bythe Board of Directors in 1990 and

renamed in honor of Leon K. Kirchmay-er in 2002. Dr. Kirchmayer was wellknown and revered throughout theworld for his commitment to studentsand education.

This award honors teachers of electri-cal and electronics engineering and therelated disciplines, ‘for inspirational teaching ofgraduate students in the IEEE fields of interest.’

A primary goal of the IEEE is to ensure that theInstitute Awards Program provides due recognitionfor superior achievement in the engineering profes-sion. To that end, and in response to the desire of themembership, the Awards Board, and Board of Direc-tors that the field of education be more broadly rec-ognized, this award for graduate teaching was addedto the Awards Program. Selection criteria includesuch contributions as curriculum development,authorship of course materials, involvement with stu-dents and faculty in advisory capacities, as well as

‘attracting students to engineering and scien-tific professions, and preparing them for

effective careers in engineering and thesciences.’

Recipient selection is administeredby the IEEE Awards Board through theTechnical Field Awards Council. It isawarded to an individual only.In the evaluation process, the follow-

ing criteria are considered: excellence inteaching graduate students, curriculum devel-

opment with the inclusion of current research anddevelopment knowledge that reflects the state of theart in courses, authorship of course material for grad-uate students; and involvement with and direction ofstudents to prepare them for effective careers in engi-neering and the sciences, and the quality of the nom-ination.

The award consists of a bronze medal, certificateand honorarium.

For nomination form, list of past recipients and acommittee roster:

www.ieee.org/awards/sums/gradtch.xml

IEEE Leon K. Kirchmayer Graduate Teaching Award Nomination Deadline - 31 January

Call for Nominations: SSCS Predoctoral Fellowships2007 – 2008Due Date is 1 May, 2007

Nominations for the Society’s Predoctoral Fellow-ships in solid-state circuits are due on 1 May,2007 for the academic year 2007-2008. The one-

year awards will include a stipend of $15,000, tuitionand fees up to a maximum of $8,000, and a grant of$2,000 to the department in which the recipient is reg-istered. A maximum of two awards will be made.

Applicants must have completed at least one yearof graduate study, be in a Ph.D. program in the areaof solid-state circuits, and be a member of IEEE.The award will be made on the basis of academicrecord and promise, dissertation research program,and need.

Applications should be in electronic format andmust include the following items:

A Short (one-page) Biography - including IEEEmembership number.

Academic Records - including a copy of all rele-vant undergraduate and graduate transcripts.

Graduate Study Plans - including a summary ofwhat has been completed and what is planned (about2 pages is appropriate), plus a list of any publications

authored or co-authored. A copy of each publicationis desirable. Work that must be done to complete thegraduate program of study should be explained --why it is important, and what is novel about itsapproach -- as well as the importance of SSCS pre-doctoral fellowship support toward completion of thedoctoral degree.

Letters of Recommendation - At least two lettersof recommendation are required; one should be fromthe principal advisor. These letters should addressacademic record, accomplishments and promise,graduate study research program, and need.

Deadline: 1 May 2007Please email your application materials to: [email protected]. Electronic file submission is preferred but if paper

files are all you can provide, either fax them to +1732-981-3401 or mail to:

IEEE-SSCS Executive OfficePredoctoral Fellowship

445 Hoes LanePiscataway, NJ 08854

sscs_NL0107 1/8/07 9:59 AM Page 82

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SSCS SPONSORED MEETINGS2007 ISSCC International Solid-StateCircuits Conferencewww.isscc.org11– 15 February 2006 San Francisco Marriott Hotel, San Francisco,CA, USAPaper deadline: PassedContact: Courtesy Associates, [email protected]

2007 Symposium on VLSI Circuitswww.vlsisymposium.org14–16 June 2007Kyoto, JapanPaper deadline: 10 January 2007Contact: Phyllis Mahoney, [email protected] Business Center for Academic Societies,Japan,[email protected]

2007 Custom Integrated Circuits Conferencehttp://www.ieee-cicc.org/16–19 September 2007San Jose, CA, USAPaper deadline: TBDContact: Ms. Melissa [email protected]

2007 A-SSCC Asia Solid-State Circuits Con-ferencewww.a-sscc.org/12–14 November 2007Seoul, KoreaPaper deadline: TBDContact: [email protected]

SSCS PROVIDES TECHNICAL CO-SPONSORSHIP 2007 International Conference on VLSIDesign www.vlsiconference.com/ 6–10 January 2007

Bangalore, IndiaPaper deadline: PassedContact: VLSI Secretariat:[email protected]

Advances in Analogue Circuit Design(AACD) Conference www.aacd.ws/27–29 March, 2007Oostende, Belgium.Paper deadline: TBDContact: [email protected]

2007 Design, Automation and Test inEuropewww.date-conference.com/conference/next.htm16–20 April, 2007Acropolis, Nice, FrancePaper deadline: PassedContact: [email protected]

2007 International Symposium on VLSITechnology, Systems and Applications(VLSI-TSA) vlsidat.itri.org.tw25 Apr - 27 Apr 2007 Hsinchu, Taiwan Paper Deadline: PassedContact: Ms. Stacey C.P. [email protected]

2007 International Symposium on VLSIDesign, Automation and Test (VLSI-DAT) vlsidat.itri.org.tw25 Apr - 27 Apr 2007 Hsinchu, Taiwan Paper Deadline: PassedContact: Elodie J.F. [email protected]

2007 Radio Frequency Integrated Circuits Symposium www.rfic2007.org3–8 June 2007Honolulu, HawaiiPaper deadline: 8 January 2007Contact: Dr. Luciano [email protected]

2007 Design Automation Conferencewww.dac.com4–8 June 2007San Diego, CA, USAPaper deadline: PassedContact: Kevin Lepine, Conference [email protected]

2007 IEEE Symposium on VLSI Circuitswww.vlsisymposium.org14 Jun - 16 Jun 2007 Kyoto, JapanPaper Deadline: 10 January 2007Contact: Ms. Phyllis W. [email protected]

ESSCIRC/ESSDERC 2007 - 37th European SolidState Circuits/Device Research Conferenceswww.essscirc.org11 Sep - 13 Sep 2007 Munich, GermanyPaper Deadline: 7 April 2007Contact: Mr. Philip [email protected]

2007 IEEE Bipolar/BiCMOS Circuits andTechnologyMeeting - BCTM 30 Sep - 02 Oct 2007 Boston Marriott Long Wharf, Boston, MA Paper Deadline: TBDContact: Ms. Janice [email protected]

SSCS EVENTS CALENDARAlso posted on www.sscs.org/meetings

IEEE SOLID-STATE CIRCUITS SOCIETY NEWSLETTER is published three times per year, January, May,and September by the Solid-State Circuits Society of The Institute of Electrical and Electronics Engineers,Inc. Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016-5997. $1 per member per year(included in society fee) for each member of the Solid-State Circuits Society. This newsletter is printed inthe U.S.A. Postmaster: Send address changes to IEEE Solid-State Circuits Society Newsletter, IEEE, 445Hoes Lane, Piscataway, NJ 08854. ©2006 IEEE. Permission to copy without fee all or part of any materi-al without a copyright notice is granted provided that the copies are not made or distributed for directcommercial advantage and the title of publication and its date appear on each copy. To copy materialwith a copyright notice requires specific permission. Please direct all inquiries or requests to IEEE Copy-rights Manager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966.

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