2. use and dissemination of foreground (section a- public) · eurosoi+- fp7-216373 9 of 38...

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2. USE AND DISSEMINATION OF FOREGROUND (Section A- Public)

I. Training and promotional activities.

a. Website database (http://www.eurosoi.org) i. EUROSOI Virtual Journal

http://www.eurosoi.org/articles.asp ii. EUROSOI Landmark publications

http://www.eurosoi.org/landmark_publications.asp iii. EUROSOI Newsletters

http://www.eurosoi.org/newsletters.asp iv. EUROSOI News&Announcements

http://www.eurosoi.org/news.asp v. EUROSOI Training material database

http://www.eurosoi.org/tutorials.asp

b. Organization of Training events and Tutorials

i. Multigate SOI MOSFETs (January 23rd,2008, Cork, Ireland) • The SOI MOSFET: from Single Gate to Multigate (Prof. Jean-Pierre Colinge,

Tyndall, Ireland) • Physics of the Multigate MOS System (Prof. Bogdan Majkusiak, Warsaw

University of Technology, Poland) • Mobility in Multigate MOSFETs (Francisco Gamiz, University of Granada, Spain) • Multigate MOSFET Technology (Malgorzata Jurczak, IMEC, Belgium) • Radiation Effects in Advanced Single- and Multi-Gate SOI MOSFETs

(Véronique Ferlet-Cavrois, CEA, France) • Multigate MOSFET Circuit Design (Gerhard Knoblinger, Infineon, Germany)

ii. First FDSOI tutorial of the Thematic Network on SOI technology, devices and circuits (November 17-18, 2008, Grenoble, France)

• Introduction of the First FDSOI Tutorial (Olivier Faynot, CEA-LETI, Grenoble, France)

• Variability Issues (Asen Asenov, Glasgow University) • Fully-Depleted SOI for Nanometer Subthreshold Circuits (D. Bol, UCL, Belgium) • Compact Modeling of Undoped FDSOI MOSFET (O. Rozeau, LETI, Grenoble,

France) • FDSOI Devices: Physics and Characterization (Prof. Sorin Cristoloveanu, IMEP,

Grenoble, France) • FDSOI Circuit Design (Alexandre Valentian, CEA-LETI, Grenoble, France) • FDSOI: Technology and Electrical Results (F. Andrieu, CEA-LETI, Grenoble,

France) • EUROSOI+: European Platform for low-power applications on Silicon on

Insulator Technology (Prof. F. Gámiz, UGR, Spain)

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iii. SOI from modelling to design (January 19th, 2009, Goteborg, Sweden) • Modelling of ultra thin body SOI nano-transistors (Prof. Luca Selmi, University of

Udine) • Strained channel materials for SOI transistors (Prof.Siegfried Mantl,

Forschungszenter, Jülich, Aachen) • SOI technology: an opportunity for RF designers, (Prof.Jean-Pierre Raskin,

Université Catholique de Louvain) • From MEMS to embedded NEMS (Dr.Julien Arcamone, CEA-LETI, Grenoble) • Ultimately thin carbon on insulators : Graphene (Prof.Max Lemme, Harvard

University, Cambridge, Massachusetts) • SOI Circuits: Do you want Partially Depleted or Fully Depleted Devices?

(Prof.Jean-Pierre Colinge, Tyndall National Institute, Cork) • Digital SOI design in the nanometer era - from high-performance to ultra-low-

power circuits (Prof.David Bol, Université Catholique de Louvain)

iv. SOI Concepts: from materials to devices and applications (June 20th-26th, Autrans, France, 2009). MIGAS Summer School

!!!! Introduction to SOI - What is SOI?, J.P. Colinge, Tyndall, Ireland - SOI zoo, J.P. Colinge, Tyndall, Ireland SOI Material - Smart-Cut and beyond, L. Clavelier, Leti, France - Technology modules, C. Fenouillet-Béranger, STmicroelectronics & Leti, France !!!! SOI transistors: device physics - Mechanisms in PDSOI and FDSOI devices, O. Faynot, Leti, France

- Transport in double-gate and nanowire MOSFET, T. Hiramoto, University of Tokyo, Japan

- Quantum and tunneling SOI devices, A. Zaslavsky, Stony Brook University, USA - Advanced simulation, F. Gamiz, UGR, Spain - Advanced modelling and ultimate scaling, T. Ernst, Leti, France !!!! Electrical characterization and reliability

- Advanced techniques for material and device characterization, S. Cristoloveanu, IMEP-LAHC, France

- Radiation effect and reliability, R. Schrimpf, Vanderbilt, USA - How SOI can solve variability issues?, A. Asenov, Glasgow Univ., UK Designing SOI circuits - SOI circuit design plateform, P. Flatresse,STMicroelectronics, France - SOI memories, B. De Salvo, Leti, France - Low power RF, J.-O. Plouchart, IBM, USA - Power devices, P. Wessels, NXP, Netherlands - MEMS, NEMS, sensors, D. Elata, Technion, Israel

v. Exploring new routes with SOI (January 25th, 2010, Grenoble, France)

• Advanced SOI Technology (Dr.Jan Hoentschel, GlobalFoundries, Dresden, Germany)

• Composite single-crystal-based wafers for advanced radiofrequency acousto-electric devices (Dr.Sylvain Ballandras, FEMTO-ST, France)

• Electrical characterisation of SOI nanodevices, (Prof.Gerard Ghibaudo, IMEP-LAHC, INPG-MINATEC, Grenoble, France)

• Wafer Level 3D Integration: Overview of technologies (Dr.N.Sillon, CEA-LETI, Grenoble)

• SOI substrate for RF applications? (Dr.Eric Desbonnets, SOITEC, Bernin, France)

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vi. Silicon on Insulator: Materials to Circuit Design (September 13th, 2010, Seville, Spain)

• Smart cut enabled materials (Cindy Colinge, Tyndall, Cork, Ireland) • Physics of SOI devices (Jean Pierre Colinge, Tyndall, Cork, Ireland) • SOI MOSFET compact models (Benjamin Iñiguez, URV, Tarragona, Spain) • SOI technology: An opportunity for RF designers?. (Jean Pierre Raskin, UC,

Louvain-la-Neuve, Belgium) • Analog SOI CMOS devices : figures of merit, design techniques and

applications. (Denis Flandre, UCL, Louvain-la-Neuve, Belgium ) • SOI design: logic circuits. (Philippe Flatresse, STMicroelectronics, Crolles,

France)

vii. Silicon on Insulator technologies for future electronics (January 17th, 2011, Granada, Spain)

• SOI solutions for next technological nodes. (Sigfried Mantl, FZJülich, Aachen, Germany)

• ETSOI Technology (Bruce Doris, IBM Research, Yorktown Heights, USA) • CMOS-SOI-MEMS Imagers (Yael Nemirovsky, Technion, Haifa, Israel) • SOI Low-power applications (Noboyuki Sugii, LEAP, Tokyo, Japan) • Memories on SOI (Malgorzata Jurczak, IMEC, Leuven, Belgium) • SOI Photonics (Jean Marc Fedeli, CEA-LETI, Grenoble, France)

c. Organization of Workshops.

i. Fourth Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (Tyndall National Institute, Cork, Ireland, Jan 23-25th, 2008): http://www.tyndall.ie/eurosoi2008/ (56 accepted communications, 80 attendants)

ii. Fifth Workshop of the Thematic Network on Silicon on Insulator

Technology, Devices and Circuits (Chalmers University of Technology, Goteborg, Sweden, Jan 19-21st, 2009): http://chalmers2009.eurosoi.org (60 accepted communications, 90 attendants)

iii. Sixth Workshop of the Thematic Network on Silicon on Insulator

Technology, Devices and Circuits (MINATEC, Grenoble, France, Jan 25-27th, 2010): http://grenoble2010.eurosoi.org/ (56 accepted communications, 110 attendants)

iv. Seventh Workshop of the Thematic Network on Silicon on Insulator

Technology, Devices and Circuits (Parque de las Ciencias, Granada, Spain, Jan 17-29th, 2011): http://granada2011.eurosoi.org/ (64 accepted communications, 120 attendants)

d. Discussion Panels. The opinion of SOI experts.

i. “Key Issues in SOI: Solutions and Ideas”, chaired by Prof.Sorin Cristoloveanu, January 24th, 2008, Cork, Ireland

Participants: Dr. Damien Bretegnier, SOITEC

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Prof. Denis Flandre, UCL Dr. Segei Okonin, Innovative Silicon Dr.Olivier Faynot, CEA-LETI Prof. Jean-Pierre Colinge, Tyndall

ii. “What is the killing advantage of multiple-gate SOI MOSFETs: electrostatics and scalability, transport or functionality”, chaired by Prof.Sorin Cristoloveanu, January, 20th, 2009 Goteborg, Sweden

Participants: Prof. Cor Claeys, IMEC Prof. Jerry Fossum, University of Florida Prof. Jean-Pierre Colinge, Tyndall Dr.Olivier Faynot, CEA-LETI Dr.Stephane Monfray, STMicroelectronics, Crolle Prof.Francis Balestra, IMEP, SINANO Institute

iii. “SOI Technologies: What kind of research for what kind of products?”,

chaired by Prof.Raphael Clerc, January 26th, 2010, MINATEC, Grenoble, France

Participants: Dr. Horacio Mendez, SOI Industrial Consortium, USA

Dr. Christophe Tretz, IBM, USA Dr. Frederic Bouef , STMicroelectronics, Crolles, France Dr. Jan Hoentschel, GlobalFoundries, Dresden, Germany Prof. Jean-Pierre Colinge, Tyndall, Cork, Ireland Prof. K.Saraswat, Stanford University, Stanford, USA

iv. “The contribution of SOI to the brilliant future of Nanoelectronics””, chaired by Prof.Francis Balestra, January 18th, 2011, Parque de las Ciencias, Granada, Spain

Participants: Dr. Malgorzata Jurczak, IMEC, Belgium

Dr. Bruce Doris, IBM, USA Dr. Olivier Faynot, LETI, Grenoble, France Prof. Massimo Fischetti, UT Dallas, USA Prof. Carl Das, EUROPRACTICE, IMEC, Belgium Dr. Nobuyuki Sugii, Leap, Japan

e. Elaboration & Upgrading of Technical Focused Reports (TFRs).

i. EUROSOI State of the art report: Deliverable D4.4. (To be published online on EUROSOI Website).

ii. EUROSOI roadmap. Deliverable D4.5. (To be published online on EUROSOI Website).

iii. EUROSOI who is who. Deliverable D4.6. (To be published online on EUROSOI Website).

iv. Benchmark of UTB vs. FinFET vs. DG SOI transistors. Which SOI device is favourite and for which application? http://www.eurosoi.org/public/D4.15.focused.report.utb_finfet_def.pdf

v. Reliability, lifetime,and ageing are relevant topics from an industrial perspective. http://www.eurosoi.org/public/D4.16.focused.report.soi_reliability.pdf

vi. SOI model with parameters representative of technologies of interest http://www.eurosoi.org/public/D4.17.focused.report.soi_model.pdf

f. Sponsoring of SOI events (Deliverables D2.6 & D2.7)

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1. IEEE International SOI conference (2008-2009)

2. nanoKISS 2010: Korean International Summer School on Nanoelectronics

3. International SemOI Workshop "Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices"

4. European Solid State Device Research Conference 2010, ESSDERC-2010, Tutorial: “Silicon on Insulator: Materials to Circuit Design”

5. nanoKISS 2011: Korean International Summer School on Nanoelectronics

II. Development of EUROSOI fabrication & prototyping platform for the design of low-

power SOI circuits.

a. Coordination of information exchange on LETI FDSOI technology. FDSOI wafers with functional devices have been provided to UCL, IMEP, URV and UGR. Also, electrical measurements have been provided to UGR.

b. Coordination of activities for the documentation, promotion and spreading of Research-dedicated Design Kit (RDK). The development of the research design kit is progressing in phase with what has been planned in the European project called DECISIF. This design kit contains a digital part that includes device model, Design Rules Control file and Layout Versus Schematic file. These files are essential to model and control the layout generated by the designers. This part is completed at 100%. The design kit contains also an analog part that includes Matching parameters, RF parasitics and related model (completed at 100%). The design kit finally contains an automated digital Design flow that includes Standard cell library and SRAM memory cuts. This last part is completed at 100%. With such level of achievement, the design kit can already be used to design some elementary circuits.

c. Promotion of the FDSOI technology.

Promotion of the FDSOI technology has been made by LETI during this period to the following companies:

- Presentation of the technology and results are regularly (every 3 months) made to SOITEC.

- Technology and electrical results have been also presented to ST Microelectronics in order to highlight the interest of such technology for Low Power applications.

- Promotion of FDSOI technology has also been done to AMD and ARM through a presentation at the SOI consortium meeting in November 2008.

- During the LETI annual review (in June 2009), a specific presentation has been made by Olivier Faynot in order to make a status of this technology at LETI and present the state of the art of the Research dedicated Design Kit.

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- In the frame of the 2009 VLSI symposium, held in Kyoto, Olivier Faynot had the opportunity to participate to the evening rump session. The rump session was focussed on ‘The Key technology options for sub 20nm nodes’.

- A FDSOI workshop has been co-organized in Leuven from October 15-16th 2009, by the SOI Consortium and IMEC. This workshop was dedicated to the promotion of the FDSOI technology for the industrial companies that are more focussed on Bulk and FinFET technologies. (http://www.soiconsortium.org/resources/fully-depleted-soi-october-2009.php )

- After 2009 IEDM conference in Baltimore, a second FDSOI workshop has been co-organized (on December 9th) by the SOI Consortium and LETI. The goal was the same as the previous workshop. This meeting was a good opportunity to expose ARM company to the recent FDSOI results. (http://www.soiconsortium.org/resources/fully-depleted-soi-december-2009.php )

- In the frame of the DECISIF project, the most recent FDSOI technology developments have been presented in Dresden (Global Foundries site), in front of the project partners: ST, SOITEC, SILTRONIC, MPI Halle, Juelich. (http://www.catrene.org/web/downloads/profiles_medea/2T104-DECISIF-profile-outMEDEA%20(21-7-09).pdf )

- During the EUROSOI 2010 workshop, a working group meeting has been organized and Carlo Reita (LETI) presented the status of the FDSOI platform. Outcomes of this meeting are summarized in deliverable D5.3.

- Technology and electrical results have been also presented to ST Microelectronics and SOITEC in order to highlight the interest of such technology for Low Power applications. No travel expenses are related to this promotion.

- An article has been written in ‘Advanced Substrates News’, in the Spring 2009 edition. The title is: ‘Leti, Soitec and ST have discovered the sources of threshold voltage variation in undoped, ultrathin FD-SOI architectures.’ It can be read using the following website: http://www.advancedsubstratenews.com/index.php?newsletter=4&nomRubrique=IEDM-Highlights&rubrique=78#Leti

- A FDSOI workshop has been held in Japan during SSDM conference (Sept. 2010). During this workshop, Carlo Reita presented a status of the platform and announced its availability through CMP in France.

- A press release announcement has been made, in October 2010, to announce the availability of the FDSOI platform through CMP. http://www.eetimes.com/electronics-news/4208994/20-nm-MPW-run-for-SOI-scheduled http://cmp.imag.fr/aboutus/slides/Slides2011/20_CEALeti_Carlo_Reita_2011.pdf

- During the LETI annual review (in June 2011), a specific presentation has been made by Olivier Faynot in order to make a status of this technology at LETI and present the state of the art of the Research dedicated Design Kit.

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- In the frame of the 2010 IEDM conference, held in San Francisco, Olivier Faynot had the opportunity to give an invited talk on the FDSOI technology. This was a good opportunity to expose the Semiconductor community to the last results obtained with this technology

- After IEDM conference in San Francisco, a FDSOI workshop has been

co-organized (on December 9th) by the SOI Consortium and LETI. The goal was the same as the previous workshop. This meeting was a good opportunity to expose ARM and ST companies to the recent FDSOI results.

- During the EUROSOI 2011 workshop, several presentations were dedicated to the promotion of the FDSOI technology: Carlos Mazuré, from SOITEC, presented a status on the readiness of the SOI wafers for such platform and Bruce Doris presented the status of the ongoing technology developed in USA, in collaboration with CEA-LETI.

- Technology and electrical results have been also presented, during

technical meetings, to ST Microelectronics and SOITEC in order to highlight the interest of such technology for Low Power applications.

- A workshop has been organized in Taiwan, during the VLSI-TSA

conference. CEA-LETI was co-organizer of this workshop.

d. Coordination of activities for the evaluation of the possible integration in the existing EUROPRACTICE structure.

1. We are now considered as one of the EUROPRACTICE projects (http://www.europractice.org/).

2. We participated in the EUROPRACTICE Workshop held in Leuven on September 4th, 2008.

3. A telephone meeting with Dr.Carl Das (IMEC) and Dr.John Mclean (RAL), Dr.Olivier Faynot (LETI), Dr.Carlo Reita (LETI) and Prof.Francisco Gamiz (UGR) was held on September 9th, 2009 to discuss the following steps to be given in order that LETI-FDSOI technology could be offer in the framework of EUROPRACTICE program.

4. A meeting with EUROPRACTICE was organized in Granada (Deliverable D5.6)

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TEMPLATE A: LIST OF SCIENTIFIC (PEER REVIEWED) PUBLICATIONS, STARTING WITH THE MOST IMPORTANT ONES

NO. Title Main author Title of the

periodical or the series

Number, date or frequency

Publisher Place of

publication Year of

publication Relevant pages

1 Low Frequency Noise Characterization in n-channel FinFETs

R.Talmat Solid State Electronics

Submitted Elsevier UK 2012

2 Design of Silicon Double-Gate Tunnel FETs with Ultra-Low Ambipolar Currents

F.Hraziia Solid State Electronics


3 CMOS without doping: multi-gate silicon-nanowire field-effect-transistors

F.Wessely Solid State Electronics


4 Analysis and Optimization of Lateral Thin-Film Silicon-on-Insulator (SOI) PMOS Transistor with an NBL layer in the Drift Region

I.Cortés Solid State Electronics


5 Function of the Parasitic

Bipolar Transistor in the 40nm PD SOI NMOS Device Considering the Floating Body Effect

C.H.Chen Solid State Electronics


6 Analysis of temperature

variation influence on the analog performance of 45 rotated triple-gate NMUGFETs

M.A.Pavanello Solid State Electronics


7 GIDL behavior of p- and

nMuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

M. Galeti Solid State Electronics


8 Improved 1/f Noise

characterization of Strained SiGe On Insulator MOSFETs

M.Valenza Solid State Electronics


9 Influence of discrete dopant on quantum transport in silicon nanowire transistors

N.Dehdashti-Akhavan

Solid State Electronics


10 Confinement-induced carrier mobility increase in nanowires

N.Neophytou Solid State Submitted Elsevier UK 2012

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by quantization of warped bands

Electronics

11 LDMOS-transistors on semi-insulating Silicon-on-polycrystalline-Silicon Carbide substrates for improved RF and thermal properties

S.Lofti Solid State Electronics


12 Ultra-thin body and thin-BOX

SOI CMOS Technology Analog Figures of Merit

V.Kilchytska Solid State Electronics


13 Quantum simulation of an ultrathin body field-effect transistor with channel imperfections

V.Vyurkov Solid State Electronics


14 Subband Engineering in n-

Type Silicon Nanowires using Strain and Confinement

Z.Stanojevic Solid State Electronics


15 Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

F.H.Ruddell Solid State Electronics

52 Elsevier UK 2008 1849 1853

16 Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology

D.Bol Solid State Electronics

52 Elsevier UK 2008 1939 1945

17 High-temperature DC and RF behaviors of partially-depleted SOI MOSFET transistors

M.Emam Solid State Electronics

52 Elsevier UK 2008 1924 1932

18 Threshold voltages of SOI MuGFETs

M.G.C.de Andrade

Solid State Electronics

52 Elsevier UK 2008 1877 1883

19 Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

M.A.Pavanello Solid State Electronics

52 Elsevier UK 2008 1904 1909

20 Modeling the equivalent oxide thickness of Surrounding Gate SOI devices with high-κ insulators

I.M.Tienda-Luna Solid State Electronics

52 Elsevier UK 2008 1854 1860

21 Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

M.de Souza Solid State Electronics

52 Elsevier UK 2008 1933 1938

22 Temperature behavior of spiral inductors on high resistivity substrate in SOI CMOS technology

M.El Kaamouchi Solid State Electronics

52 Elsevier UK 2008 1915 1923

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23 Substrate bias and operating temperature effects on the performance of Schottky-barrier SOI nMOSFETs

D.H.Ka Solid State Electronics

52 Elsevier UK 2008 1910 1914

24 Compact charge and capacitance modeling of undoped ultra-thin body (UTB) SOI MOSFETs

O.Moldovan Solid State Electronics

52 Elsevier UK 2008 1867 1871

25 Germanium on sapphire by wafer bonding

P.T.Baine Solid State Electronics

52 Elsevier UK 2008 1840 1844

26 Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations

R.Yan Solid State Electronics

52 Elsevier UK 2008 1872 1876

27 Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs

W.Guo Solid State Electronics

52 Elsevier UK 2008 1889 1894

28 Evaluation of super-critical thickness strained-Si on insulator (sc-SSOI) substrate

A.Ogura Solid State Electronics

52 Elsevier UK 2008 1845 1848

29 Analysis of STI-induced mechanical stress-related Kink effect of 40 nm PD SOI NMOS devices biased in saturation region

I.S.Lin Solid State Electronics

52 Elsevier UK 2008 1884 1888

30 How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

A.Kranti Solid State Electronics

52 Elsevier UK 2008 1895 1903

31 Electron subband structure and controlled valley splitting in silicon thin-body SOI FETs: Two-band k · p theory and beyond

V.Sverdlov Solid State Electronics

52 Elsevier UK 2008 1861 1866

32 Multi-Subband Monte Carlo study of device orientation effects in ultra-short channel DGSOI

C. Sampedro Solid State Electronics

54 Elsevier UK 2010 131 136

33 Performance estimation of junctionless multigate transistors

C.W.Lee Solid State Electronics

54 Elsevier UK 2010 97 103

34 Effect of rotation, gate-dielectric and SEG on the noise behavior of advanced

S.Put Solid State Electronics

54 Elsevier UK 2010 178 184

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SOI MuGFETs

35 Effect of high-energy neutrons on MuGFETs


54 Elsevier UK 2010 196 204

36 Electron subband structure in strained silicon UTB films from the Hensel–Hasegawa–Nakayama model – Part 2 efficient self-consistent numerical solution of the k · p schrödinger equation

O.Baumgartner Solid State Electronics

54 Elsevier UK 2010 143 148

37 SOI versus bulk-silicon nanoscale FinFETs

J.G.Fossum Solid State Electronics

54 Elsevier UK 2010 86 89

38 Systematic study of Schottky barrier MOSFETs with dopant segregation on thin-body SOI

C.Urban Solid State Electronics

54 Elsevier UK 2010 185 190

39 Low-temperature characterization and modeling of advanced GeOI pMOSFETs: Mobility mechanisms and origin of the parasitic conduction

W.V.DDaele Solid State Electronics

54 Elsevier UK 2010 205 212

40 Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides

T.Rudenko Solid State Electronics

54 Elsevier UK 2010 164 170

41 Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

S.Burignat Solid State Electronics

54 Elsevier UK 2010 213 219

42 Electron subband structure in strained silicon UTB films from the Hensel–Hasegawa–Nakayama model – Part 1 analytical consideration and strain-induced valley splitting

T.Windbacher Solid State Electronics

54 Elsevier UK 2010 137 142

43 Thin-film devices for low power applications

S.Monfray Solid State Electronics


44 Large-signal analysis of substrate effects in RF-power SOI-LDMOS transistors

L.Vestling Solid State Electronics

54 Elsevier UK 2010 171 177

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45 Fabrication of Silicon on Diamond (SOD) substrates by either the Bonded and Etched-back SOI (BESOI) or the Smart-Cut™ technology

J. Widiez Solid State Electronics

54 Elsevier UK 2010 158 163

46 Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs

L.P.Nguyen Solid State Electronics

54 Elsevier UK 2010 123 130

47 Hole transport in DGSOI devices: Orientation and silicon thickness effects

L.Donetti Solid State Electronics

54 Elsevier UK 2010 191 195

48 Suppression of gate-induced drain leakage by optimization of junction profiles in 22 nm and 32 nm SOI nFETs

A.Schenk Solid State Electronics

54 Elsevier UK 2010 115 122

49 Physical modeling of millimetre wave signal reflection from forward biased PIN diodes

R.P.Jackson Solid State Electronics

54 Elsevier UK 2010 149 152

50 Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications

M.Bawedin Solid State Electronics

54 Elsevier UK 2010 104 114

51 Oxygen out-diffusion from buried layers in SOI and SiC–SOI substrates

L.-G.Li Solid State Electronics

54 Elsevier UK 2010 153 157

52 Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies

T.Signamarcheix Solid State Electronics


53 Physics of Gate Modulated Resonant Tunneling (RT)-FETs: Multi-barrier MOSFET for steep slope and high on-current

A.Afzalian Solid State Electronics


54 Capacitor-less A-RAM SOI memory: Principles, scaling and expected performance

N.Rodríguez Solid State Electronics


55 Simulation of the electrostatic and transport properties of 3D-stacked GAA silicon nanowire FETs

F.G.Ruiz Solid State Electronics


56 Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency

M.Valenza Solid State Electronics


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noise

57 Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs



58 Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance

K.H.Park Solid State Electronics


59 High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

C.Le Royer Solid State Electronics


60 Detailed investigation of effective field, hole mobility and scattering mechanisms in GeOI and Ge pMOSFETs

W.V.DDaele Solid State Electronics


61 Impact of SEG on uniaxially strained MuGFET performance

P.G.D.Agopian Solid State Electronics


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3. REPORT ON SOCIETAL IMPLICATIONS A General Information (completed automatically when Grant Agreement number is entered. Grant Agreement Number:

216373

Title of Project: European Platform for Low-Power Applications on Silicon-On-Insulator Technology

Name and Title of Coordinator: Francisco Gamiz, Professor

B Ethics

1. Did you have ethicists or others with specific experience of ethical issues involved in the project?

¡

¤

Yes

No

2. Please indicate whether your project involved any of the following issues (tick box) :

YES

INFORMED CONSENT • Did the project involve children? • Did the project involve patients or persons not able to give consent? • Did the project involve adult healthy volunteers? • Did the project involve Human Genetic Material? • Did the project involve Human biological samples? • Did the project involve Human data collection?

RESEARCH ON HUMAN EMBRYO/FOETUS • Did the project involve Human Embryos? • Did the project involve Human Foetal Tissue / Cells? • Did the project involve Human Embryonic Stem Cells?

PRIVACY • Did the project involve processing of genetic information or personal data (eg. health, sexual

lifestyle, ethnicity, political opinion, religious or philosophical conviction)

• Did the project involve tracking the location or observation of people? RESEARCH ON ANIMALS

• Did the project involve research on animals? • Were those animals transgenic small laboratory animals? • Were those animals transgenic farm animals? • Were those animals cloning farm animals? • Were those animals non-human primates?

RESEARCH INVOLVING DEVELOPING COUNTRIES • Use of local resources (genetic, animal, plant etc) • Benefit to local community (capacity building ie access to healthcare, education etc)

DUAL USE • Research having potential military / terrorist application

C Workforce Statistics 3 Workforce statistics for the project: Please indicate in the table below the number of people

who worked on the project (on a headcount basis). Type of Position Number of Women Number of Men

Scientific Coordinator 1 Work package leader 5 Experienced researcher (i.e. PhD holders) 4 11 PhD Students

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