2 layered pxd · 2021. 2. 19. · 19. feb 2021 bpac - 2 layered pxd - [email protected] 2...

2 LAYERED PXDBPAC Feb 2021

19. Feb 2021 BPAC - 2 layered PXD - [email protected] 2

PXD2 MODULE PRODUCTION− modules from old productions

− 5 L1 modules and 4 phase 2 modules → 3 L1 ladders assembled

− two batches started in 2018

− PXD9-20: 12 wafers → 27 modules assembled, one L1 pair left

− PXD9-21: 12 wafers → waiting for final metal (copper)

IFIF

OF1OF1

OF2OF2

OB1OB1

OB2OB2

IBIB

PXD wafer @ HLL cutting + SMD + ASIC FCASICs: SWB, DCD, DHP

Kapton attachment+ ladder gluing@ MPP


PROBLEMS DURING PXD9-20 FLIP-CHIP 1− broken vacuum pump in flip-chip furnace

− wrong temperature profile→ high copper consumption on bump connections

− oxidation of module bump pads

− particle problems

− difficult (narrow) process window

− different optimal temperatures for switcher and DHP+DCD FC

− improve thermal contact by omitting aluminum interposer− good wetting of all ASICs− sufficient copper under DHP solder bumps (status Nov. 20)

− finally: 2 step process

1) higher temperature step for SWBs

2) lower temperature step for DHPs+DCDs on end of stave


PROBLEMS DURING PXD9-20 FLIP-CHIP 2− > complete re-qualification of FC process with

− new vacuum pump

− better thermal contact

− new FC adhesive

− changed temperature profile and dual step

− > successfully tested, first three modules functional at first tryW60_OF1, W60_IB, W61_IB

− last L1 pair assembly on hold

− poly silicon plate of furnace broke during work on other project(no PXD modules harmed)

− 6 weeks replacement time


PROBLEMS DURING PXD9-20 FLIP-CHIP 3− through laborious rework at HLL 23 of 27 assembled modules working

− 9 also working after Kapton attachment

− 14 to be connected to Kapton and tested

− 8 modules have been subjected to temperature cycling in climate chamber and through module power cycling→ standard procedures for all modules in new characterization scheme

− 50 cycles a -30°C to +70°C

− no impact on services

− no impact on module functionality

− subject one module to severalhundred power cycles


PXD9-20 MODULE STATUS

− 11 L1 modules assembled, tested (and thermally cycled)

− 3 L1 ladders: L61, L62, L63 (grades A, B, A)

− 1 grade A IB, 2 grade C/D IF, 2 destroyed IF

− 14 modules ready for Kapton attachment

− 2 IF, 5 IB, 3 OB, 4 OF, 2 failed FC

− > highly successful rework of modules

− 1 L1 pair of bare sensors left (W57)

W50 W51 W52 W53 W54 W55 W56 W57 W58 W59 W60 W61

IF lost A – L61 B – L62 A – L63 D ready for test 99.8 shear test ready for KA 0 lost in rework

OF1 NA lost NA 99.9 NA 100 ready for KA ready for test 0 bad after FC ready for KA 100

OF2 NA lost NA NA NA 0 100 ready for KA 100 99.6 100 0

OB1 100 lost 99.5 100 100 99.8 Y ready for test ready for KA 99.5 100 99.4 B 0

OB2 0 lost 100 Y 100 99.5 100 ready for test 98.9 0 bad after FC 0 0

IB 0 lost A B – L62 A – L63 A – L61 ready for test 100 ready for KA ready for KA ready for KA ready for KA

C

A,B,C,D – full tested moduleL# – part of ladder #KA – Kapton attachmentFC – flip-chipnumber – bare sensor

– global passed, grade A – global passed, grade B 0 – global tests failed

(implant/poly short)

W51 lost during cutting

PXD9-20 L1 tally:

− 3 viable L1 ladders ready

− material for 3 more L1 ladders from this waferplus 1 grade A IB and 3 IB to be tested


PXD9-21 SENSOR STATUS− all wafers at start of phase 3

− global test results (allClear vs. Source)W65 W66 W67 W68 W69 W70 W71 W72 W73 W74 W75 W76

IF ok ok ok ok ok ok ok ok ok

OF1 ok ok ok ok ok ok bad ok ok ok

OF2 bad ok ok ok ok ok ok ok ok ok ok ok

OB1 ok ok ok ok ok ok ok ok ok ok ok

OB2 ok bad ok ok ok ok bad ok ok ok

IB ok bad any gate any gate ok ok ok ok any gate

1st gate 1st gate 1st gate

1st gate 1st gate

1st gate

1st gate 1st gate


phase 1 phase 2

phase 3

phase 1:− implants− dielectrics− 2x poly silicon

phase 2:− 2 Al layers

phase 3: thinning and copper1) handle wafer removal ✔2) oxide removal on the backside ✔3) sputter Ti:W barrier and Cu seed layer4) lithography for electro-plating5) Cu electro-plating6) removal of the seed layer and barrier layer7) Cu conditioning (wet etching, thermal)8) tests on flying needle probe station9) final passivation BCB10) cut lithography, cutting


PXD9-21 SENSOR STATUS− all wafers at start of phase 3

− global test results (allClear vs. Source)

− proceed with two sub batches

− PXD9-21x (end of March)

− W65, W67, W71, W72, W73, W75→ best prospects for L1 modules

− PXD9-21z

− the rest

W65 W66 W67 W68 W69 W70 W71 W72 W73 W74 W75 W76








1st gate 1st gate

1st gate

1st gate 1st gate


phase 3

phase 3: thinning and copper1) handle wafer removal ✔2) oxide removal on the backside ✔3) sputter Ti:W barrier and Cu seed layer4) lithography for electro-plating5) Cu electro-plating6) removal of the seed layer and barrier layer7) Cu conditioning (wet etching, thermal)8) tests on flying needle probe station9) final passivation BCB10) cut lithography, cutting


PXD9-21 SENSOR STATUS

− 11 modules exhibit 1st gate short to clear after global testing

− AllClearGate vs. AllGate test:

− AllClearGate line was contacted directly via bond-pad as opposed to dedicated bias-resistor testpad on previous productions

− 1st gate line pad was directly contacted as opposed to AllGate testpad

− reason and exact location of short remains unclear

− suspected short between gate pad and bulk by needle stab could not be confirmed

− 6 IB modules did not receive this test to exclude damage

− > impact on module performance marginal: gate line was cut physically and will not connect to switcher, first gates are outside physics acceptance

W65 W66 W67 W68 W69 W70 W71 W72 W73 W74 W75 W76








1st gate 1st gate

1st gate

1st gate 1st gate



FULL TALLY13 L2 LaddersL42 W02_OF1 W03_OB1 ?/B MPPL44 W32_OF1 W32_OB2 A/A MPPL45 W33_OF1 W42_OB1 A/A MPPL46 W33_OF2 W46_OB2 A/A MPPL47 W46_OF1 W45_OB2 A/A MPPL48 W03_OF2 W46_OB1 A/A MPPL49 W08_OF2 W08_OB1 A/A MPPL50 W46_OF2 W08_OB2 A/A MPPL51 W45_OF1 W42_OB2 A/A MPPL52 W43_OF1 W33_OB1 A/A MPPL53 W05_OF1 W04_OB1 A/A MPPL54 W45_OF2 W10_OB1 A/A MPPL55 W37_OF1 W37_OB1 Ph II/Ph II MPP

8 L1 ladders (5 A/B in Germany)L21 W46_IF W43_IB C MPPL35 W04_IF W04_IB C DESYL37 W05_IF W42_IB B/A KEKL56 W37_IF W06_IB Ph II/C MPPL57 W11_IF W46_IB B/B MPPL58 W10_IF W05_IB A/A MPPL61 W52_IF W55_IB A/A MPPL62 W53_IF W53_IB B/B MPPL63 W54_IF W54_IB A/A MPP

Need 8 L1 (+ spares)− up to 3 more L1 ladders from PXD9-20

− 1 IB ready (grade A)− up to 3 IF and 6 IB to come (2+5 FC’ed, 1+1 bare)

→ assemble 4 more L1 from PXD9-21

− best case – only 4 IB needed

Need 12 L2 (+spares)

− 3 OB + 4 OF flip-chipped→ up to 3 more ladders


ADDITIONAL MATERIAL− 4 more L1 pairs

− ASICs are available− additional SWB to be tested at KIT

− Kaptons are available− L1 fwd: 19− L1 bwd: 10− L2 fwd: 38− L2 bwd: 22

− SCB final preparations at MPP

− hole drilling for carbon tubes

− patch panels

− nominal plus spares available

− good from last production: 11 IB, 9 IF, 10 OB, 11 OF

− additional PPs from previous production


PXD2 SCHEDULE

− assemble first half-shell in April using the best modules

− for assembly of second half-shell wait until sufficient number of additional good L1 ladders is available

− decided to postpone PXD2 transport to KEK to end of 2021 (beam pipe) 0 > 2 months contingency

− despite recent hiccups in module assembly PXD2 production is not on the critical path


BACKUP


BPAC NOV 2020 COMMENTS− It was not clear from the presentation if the PXD2 will include modules that were exposed to the flip-chip problem in

the final detector. → A: yes, these modules are thermally cycled in climate chamber and by power-cycling to confirm that the mechanical/electrical connections of the chips are sound

− Identify the root cause of the sensor damage during wafer level testing of the PXD9-21 run before proceeding. (short between gate and clear-gate)→ A: extensive tests were done, but unfortunately the reason could not be identified

− Make a complete inventory of all the parts and determine how many modules can be built in the most ideal case.→ A: exact inventory of sensors is presented. The first priority is finishing the production of PXD2 with reasonable contingency, enough ASICs, Kaptons and sensors have been confirmed to be available for this.

− Enlarging the group with young physicists, who will become expert in the operation of the PXD and the interface with the accelerator, is strongly encouraged.→ A: 3 first year PhD students at DESY (Anselm), Göttingen (Marike), Bonn (Jannes) + 1 new postdoc at DESY (Arthur)

− Develop the installation schedule of the PXD2, including assessment of all resources and type of resources needed for the installation and related activities, as soon as possible. → A: working on this


BACKUP− ‘PXD21-2’ batch (PXD9-20 sensors)


BACKUP− ‘PXD21-3’ batch

(PXD9-20 sensors)

2 layered pxd · 2021. 2. 19. · 19. feb 2021 bpac - 2 layered pxd - [email protected] 2...

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