2 ghz w-cdma radio transceiver

2 GHz W-CDMA Radio Transceiver

by

Cheung, Tze Chiu

Thesis submitted to the Faculty of the

Virginia Polytechnic Institute and State University in partial fulfillment of the

requirements of the degree of

Master of Science

in

Electrical Engineering

APPROVED:

Dennis G. Sweeney, Chairman

Charles W. Bostian Brian D. Woerner

December, 1998

Blacksburg, Virginia

Table of Contents iv

Table of Contents

1. Introduction................................................................................................................ 1

1.1 Motivation...................................................................................................... 1

1.2 Objective ........................................................................................................ 2

1.3 Outline of Thesis ............................................................................................ 2

2. System Overview ....................................................................................................... 4

2.1 Operating Band Structure............................................................................... 4

2.2 Code Division Multiple Access ..................................................................... 6

2.3 Data and Chip Rate ........................................................................................ 7

2.4 Channel Bandwidth........................................................................................ 7

2.5 Spreading and Modulation ............................................................................. 8

2.6 Transmit, Adjacent Channel and Spurious Power ......................................... 9

2.7 Receiver Sensitivity ..................................................................................... 12

2.8 Automatic Gain Control............................................................................... 12

2.9 Automatic Frequency Control...................................................................... 13

2.10 Receiver Selectivity and Spurious Response ............................................... 14

2.11 Diversity Receiver........................................................................................ 15

3. Radio Design............................................................................................................ 17

3.1 Transmitter ................................................................................................... 18

3.1.1 Block Diagram .............................................................................. 18

3.1.2 Technical Specifications ............................................................... 19

3.1.3 Design Approach and Analysis..................................................... 20

3.1.3.1 Peak-to-Average Factor ................................................. 20

3.1.3.2 Power Amplifier Requirement ....................................... 27

3.1.3.3 Receiver Desensing........................................................ 27

3.1.3.4 Transmit Power Control................................................. 29

3.1.4 Circuit Level Design ..................................................................... 29

3.1.4.1 Digital-to-Analog Conversion Board............................. 29

Table of Contents v

3.1.4.2 Modulator Board ............................................................ 32

3.1.4.3 Transmit Power Control................................................. 35

3.1.4.4 Power Amplifier............................................................. 36

3.1.4.5 Duplexer – Transmitter Part........................................... 38

3.2 Receiver........................................................................................................ 41

3.2.1 Block Diagram .............................................................................. 42


3.2.3 Design Approach and Analysis..................................................... 45

3.2.3.1 Receiver Noise Figure.................................................... 45

3.2.3.2 Heterodyne Architecture and Spurious Analysis ........... 47

3.2.3.3 Cascaded Receiver Chain Analysis................................ 56

3.2.3.4 Automatic Gain Control................................................. 63

3.2.4 Circuit Level Design ..................................................................... 65

3.2.4.1 Duplexer – Receiver Part ............................................... 65

3.2.4.2 Receiver Board............................................................... 65

3.2.4.3 Demodulator Board........................................................ 72

3.2.4.4 Analog-to-Digital Converter (ADC) Board ................... 73

3.2.4.5 Automatic Gain Control (AGC) Driver ......................... 73

3.2.4.6 Automatic Frequency Control (AFC) Board.................. 76

3.3 Synthesizer ................................................................................................... 78

3.3.1 Block Diagram .............................................................................. 79


3.3.3 Synthesizer Board ......................................................................... 80

3.3.3.1 Design Modifications..................................................... 80

3.3.3.2 Loop Filter ..................................................................... 85

3.3.4 Splitter Board ................................................................................ 87

3.3.4.1 RF Channel .................................................................... 87

3.3.4.2 IF Channel...................................................................... 88

4. Radio Performance................................................................................................... 90

4.1 Transmitter ................................................................................................... 90

4.1.1 Transmit Power ............................................................................. 90

Table of Contents vi

4.1.2 Transmit Power Control................................................................ 94

4.2 Receiver........................................................................................................ 96

4.2.1 Receiver Noise Figure................................................................... 96

4.2.2 Automatic Gain Control (AGC) Performance .............................. 97

4.2.3 Receiver Desense .......................................................................... 99

4.2.4 Adjacent Channel Selectivity........................................................ 99

4.2.5 Intermodulation Selectivity......................................................... 100

4.2.6 Automatic Frequency Control (AFC) Characteristic .................. 102

5. Conclusions............................................................................................................ 103

5.1 Summary .................................................................................................... 103

5.2 Recommendations ...................................................................................... 103

Appendix A. Radio Specifications................................................................................. 105

Appendix B. Block Diagram.......................................................................................... 107

Appendix C. Schematics ................................................................................................ 108

Appendix D. Spurious Analysis..................................................................................... 114

Appendix E. PLL Programming Information ................................................................ 121

References ....................................................................................................................... 125

Vita ................................................................................................................................ 127

Introduction 1

1. Introduction

1.1 Motivation

Wireless communications is going under explosive growth. Today, there are

approximately 100 million mobile subscribers. The number of mobile users is expected to

reach 1 billion by 2010 [1]. In Japan, this enormous growth of the mobile users is

especially prominent. Currently, subscribers are increasing at a monthly rate of 0.8-1

million. The total number of mobile users was approximately 31.5 million at the end of

March 1998 [2]. Because of the high growth rate, Japan has an aggressive plan for

developing 3rd-generation mobile systems to solve the spectrum shortage of the current

2nd-gerneration communications systems - Personal Handyphone System (PHS) and

Personal Digital Cellular (PDC).

The main goal of the 3rd-generation cellular system is to offer seamless wideband

services across a variety of environments, including 2 Mbps in an indoor environment,

384 kbps in a pedestrian environment and 144 kbps in a mobile environment [2]. The

Japanese 3rd generation system employs wideband code division multiple access (W-

CDMA) technology. The International Telecommunications Union (ITU) is also

considering W-CDMA technology for a global standard - IMT-2000. The ITU is an

international standards body of the United Nations. The system approach is leading to a

revolutionary solution instead of an evolutionary solution from the current IS-95 CDMA

system. IS-95 was designed based on the needs of voice communications and limited data

capabilities, but the 3rd-generation requirements include wideband services such as high-

speed Internet access, high-quality image transmission and video conferencing [3]. The

current IS-95 CDMA standard specifies 1.25MHz channel bandwidth and 1.2288Mchip/s

chip rate. The relatively narrow bandwidth and low chip rate makes it impossible for IS-

95 to meet the data rate requirement of the 3rd-generation. While the cdma2000 system,

which supports CDMA over wider bandwidths for capacity improvement and higher data

rates, will maintain backward compatibility with existing IS-95 CDMA systems, the W-

CDMA system will use dual-mode terminals to retain the backward compatibility.

Introduction 2

NTT DoCoMo, Japan’s biggest cellular operator, intends to introduce the 3rd-generation

mobile system based on W-CDMA [4]. According to NTT DoCoMo’s schedule, a system

trial took in place in Tokyo by the end of 1997. The first indoor tests were scheduled to

begin in April 1998, with outdoor tests commencing in October 1998 [4]. Texas

Instruments is one of the participants in the experiments with this revolutionary

technology. Texas Instruments approached CWT to participate in the experiments and to

develop the W-CDMA radio.

1.2 Objective

Once the system is commercialized at the beginning of 2001 [2], the demand of mobile

terminal equipment is expected to be huge. Mobile communications has become a

demand-led industry. Short time-to-market is very critical to the success of a terminal

product. A systematic design procedure of the radio portion of terminal equipment is

important to shorten the product design cycle. In order to formulate a design procedure

for this revolutionary system, a clear understanding of the system and signal

characteristics is necessary to parameterize the radio design.

The primary goal of the research work is to build a radio transceiver that fully complies

with the radio specifications of the W-CDMA system and to establish a systematic design

procedure. The focus of this work is on the radio portion, while the baseband portion is

handled by the sponsor, Texas Instruments. Appendix A is a summary of the radio

specifications. Analysis and simulations have been performed to explain some of the

requirements of the radio design.

1.3 Outline of Thesis

The presentation of this thesis is organized from the system level down to the circuit

level. The outline is as follows: Chapter 2 gives an overview of the system. Chapter 3

discusses the design detail of the radio. Chapter 3 comprises three main sections. Each

section presents a major sub-system of the radio. They are the transmitter, the receiver

Introduction 3

and the synthesizer. The block diagram of the sub-system is given at the beginning of the

section. Following is a summary of the technical specification. The design approach and

analysis are discussed next. Finally, the discussion is down to the circuit level of

describing the part selection and circuit topologies. Chapter 4 presents the performance of

the radio. Chapter 5 concludes the thesis and gives a recommendation for extending this

work.

System Overview 4

2 System Overview

This chapter gives an overview of W-CDMA systems that is relevant to the radio design.

2.1 Operating Band Structure

The W-CDMA radio of this work operates in the 1920-1980MHz band for the uplink

(from mobiles to base stations) and 2110-2170MHz band for the downlink (from base

stations to mobiles). These are the main bands for IMT-2000 and are designated as Band

A for the uplink and Band A′ for the downlink [2]. These two bands are in the 230MHz

global spectrum identified by the ITU World Administrative Radio Conference (WARC-

92) [5] for a worldwide standard called the Future Public Land Mobile Telephone System

(FPLMTS) – renamed International Mobile Telecommunication 2000 (IMT-2000) in

mid-1995. The FPLMTS is a 3rd generation globally compatible digital mobile radio

system that would unify the diverse systems such as paging, cordless, and cellular

systems, as well as low earth orbit (LEO) satellites, into a common flexible radio

infrastructure. Figure 1 shows the frequency plan of the 230MHz global spectrum in

Japan [2].

MSS: Mobile satellite service

PHS: Personal Handyphone System – a standard supports indoor and local

loop applications in Japan

(1) A (1920-1980 MHz), A′ (2110-2170 MHz) – the radio operating band

(2) B (2010-2025 MHz) – Time-division-duplex (TDD) system

(3) C (1885-1895 MHz, 1918.1-1920 MHz) – PHS use

Figure 1. The frequency plan of the 230MHz global spectrum for IMT-20000 in

Japan.

C PHS A MSS↑ B A′ MSS↓

1885 1920 1980 2025 2110 2170 2200 MHz2010

1893.5 1919.6

System Overview 5

The W-CDMA is a frequency division duplex (FDD) system. FDD allows a simultaneous

two-way communication by employing two separate frequency channels. The frequency

separation between the transmit and receive channels is 190MHz. The lower band (A)

carries information from the mobile terminals to the base stations. On the other hand, the

upper band (A‘) carries information from the base stations to the mobile terminals. The

traffic from the mobile terminals to the base stations is called the uplink, while the traffic

from the base stations to the mobile terminals is called the downlink.

Both the A and the A‘ bands are 60MHz wide. Both of them are divided into twelve

frequency channels. Each frequency channel is 5MHz wide. Two channels, which are

190MHz apart, are called a duplex pair. A duplex pair provides simultaneous two-way

communication. Figure 2 shows the operating band structure for the mobile terminals.

Figure 2. Operating band structure to mobile terminals.

The twelve duplex pairs permit frequency division multiple access (FDMA). FDMA

means that a number of two-way communications can be conducted simultaneously by

assigning each communication to a different duplex pair. This operating band structure

provides for twelve channels in terms of FDMA. This is very low. However, the

multiplexing power in W-CDMA is not from the FDMA. It is from the code division

multiple access (CDMA). Fukasawa [6] showed that the 5MHz channel capacity of the

W-CDMA is 82. It is 3.4 times the capacity of current analog cellular systems (AMPS).

1 2 3 10 11 12 1 2 3 10 11 12

5MHz

190MHz

fo

Tx - Lower Band60MHz

Rx - Upper Band60MHz

Single channel having centerfrequency fo

System Overview 6

2.2 Code Division Multiple Access (CDMA)

W-CDMA is a direct sequence spread spectrum (DSSS) system. Code division multiple

access (CDMA) is a unique trait of spread spectrum systems. The terminologies of

CDMA and spread spectrum basically refer to the same type of systems. In cellular

applications, CDMA is generally used to emphasize the multiple access nature of the

systems.

The direct sequence spreading process multiplies an information stream with a high chip

rate pseudo-noise (PN) code. Since the information stream is relatively low data rate as

compared to the chip rate, the spectrum of the spread output is considerably wider than

the original information stream. The PN code is the signature of the spread signal. This

embedded signature allows despreading with a synchronized replica of the PN code at the

receiving end.

W-CDMA systems spread the bandwidth of an information stream to a much wider

bandwidth and lower the power spectral density (PSD) accordingly. As a result of PN

codes, a spread signal has a noise-like quality. The transmit spread signal from an

additional user causes a slight rise in the noise floor to the current users in the channel.

The degradation of the performance of the receivers due to this additional power from the

transmitter ultimately limits the system capacity. This is the most important characteristic

of the W-CDMA system. Power becomes the common shared resource for users [7]. The

interference power is shared between the mobile terminals in the cell and each terminal

contributes to the interference. Radio resource management is to allocate power to each

user such that the maximum interference is not exceeded. The system can easily add a

user on the spectrum until the interference becomes intolerable. This is the real advantage

of the W-CDMA. In cellular terms, frequency reuse is one. Everyone shares all the

frequencies and the interference is uniformly spread over all the users. On the other hand,

FDMA and TDMA systems have a well-defined number of users based on the available

spectrum and time slots respectively. Therefore, the W-CDMA gives more flexibility on

cell capacity management.

System Overview 7

Power management provisions and tolerance of co-channel interference in W-CDMA

systems allow the use of the same frequency in adjacent cells. A frequency assignment

plan is no longer needed. In FDMA and TDMA cellular systems, each cell only uses a

part of the whole operating band in order to avoid adjacent channel interference. The

number of available channels of a cell is inversely proportional to the cluster size. A

cluster in cellular systems is a group of cells that collectively use the whole operating

band. A typical cluster size is 7. Thus, the available channels of a cell are only a seventh

of the total. On the other hand, all the cells can use the whole operating band in the W-

CDMA. W-CDMA can boost the system capacity dramatically.

2.3 Data and Chip Rate

The radio of this work is specified for 128Kbps data rate and 4.096Mcps chip rate. The

full W-CDMA specification allows variable data rates and chip rates at

1.024/4.096/8.192/16.385Mcps [3]. Spreading involves the data and chip sequences. The

data sequence is the information stream and the chip sequence is the spreading code. The

information stream is a relatively low bit rate sequence, while the spreading code is a

relatively high chip rate sequence. The ratio of the chip rate to the data rate defines the

processing gain (PG) of the system.

⋅=

data

chip

R

RPG log10 dB (2.1)

The PG for the specified chip rate and data rate of the radio is 15dB.

2.4 Channel Bandwidth

As mentioned in Section 2.1, the channel bandwidth is 5MHz. The full W-CDMA

specification allows the channel bandwidths of 1.25/5/10/20MHz [3]. The 5MHz

bandwidth is the direct result of the choice of the chip rate and the pulse shaping filter.

W-CDMA specifies a square root raised cosine pulse shaping filter with roll off factor of

System Overview 8

0.22. The use of a pulse shaping filter is to conserve the channel bandwidth. The square

root raised cosine filter satisfies the Nyquist criterion such that the introduction of the

pulse shaping does not cause intersymbol interference. Rectangular pulses without

shaping requires the channel bandwidth to be double of the pulse rate. However, if

rectangular pulses are shaped with the filter, the channel bandwidth is give by

chipss RBW ⋅+= )1( α (2.2)

where

22.0=α : is the roll-off factor of the square-root raised cosine filter.

The channel bandwidth is found to be 4.997MHz≈5MHz.

The choice of a wide channel bandwidth can achieve high data rate. For instance, the

5MHz bandwidth can support a data rate up to 384Kbps. The use of a wide channel

bandwidth enables RAKE receivers to resolve more multipaths. This improves the

receiver sensitivity or lowers the transmit power requirement for mobile terminals.

Adachi and Sawahashi [8] demonstrated the decrease of the transmit power with

increasing the spreading bandwidth on a field experiment in Tokyo. Thus the W-CDMA

can accommodate more users on a frequency channel.

2.5 Spreading and Modulation

W-CDMA specifies a two-layered spreading structure. The 1st spreading code is a short

code for channelization purposes. The code is derived from a Walsh/Hadamard function.

The spreading code for the 2nd layer spreading is a long Gold code for randomization.

The spreading process is not included in this work. It is performed in the baseband

processor. A detail discussion can be found on [9]. The baseband processor sends the

direct (I) and quadrature (Q) spread sequences in digital format to the radio. The radio

uses quadrature phase shift keying (QPSK) technique to modulate the sequences on the

carrier.

System Overview 9

2.6 Transmit, Adjacent Channel and Spurious Power

The transmitter is specified to have the maximum output power in the range from 29dBm

to 33dBm. The output power is controllable over 70dB range - the minimum output

power is from –41dBm to –37dBm. The power control step size is 1dB.

Transmitter power control (TPC) is essential to direct sequence spreading spectrum

(DSSS) systems. It is required to combat the near-far problem. The near-far problem

refers to a neighboring transmitter that can overpower a desired signal from a far

transmitter. Without power control, interference will not be spread uniformly over all

users. The near-far problem can degrade the system capacity tremendously.

W-CDMA provides TPC on both the uplink and the downlink. There are two types of the

TPC: open-loop TPC and closed-loop TPC [10].

Open loop TPC is used when closed-loop TPC cannot be applied. For instance, a mobile

terminal wants to access the system. Since the mobile terminal is not talking with the

base station, it has to estimate the path loss of the channel by measuring the received

power level of the perch channel from the base station. The perch channel provides the

transmission level of the base station. The perch is a uni-directional channel from base

stations to mobile terminals. Based on the measured result and the given transmission

level, the mobile station can calculate the path loss and determine the transmit power.

Once the connection is established between the mobile station and base station, the

closed-loop TPC is used. The closed-loop TPC is based on the signal-to-interference ratio

(SIR). Figure 3 show an example of the TPC process configuration.

System Overview 10

Figure 3. An example of TPC process configuration.

The closed-loop TPC involves two sub-loops: the inner loop and the outer loop. The

outer loop adjusts the target SIR based on the quality of the received signal. The inner

loop measures the SIR of the received signal. If the measured SIR is higher than the

target SIR, a bit called the TPC is set to “0”. This TPC bit commands the transmitter to

lower the transmit power by 1dB. Whereas, the TPC is “1”, the transmitter has to increase

the transmit power by 1dB.

W-CDMA specifies the power control cycle to be 0.625ms. The fast control cycle makes

possible tracking rapid multipath fading. The fast TPC can always minimize the transmit

power according to the traffic load. Thus, the mutual interference between users is

minimized or the channel capacity is maximized. Moreover, keeping the transmit power

low helps to conserve the battery power. The battery life is prolonged.

W-CDMA specifies 5MHz channel bandwidth and 4.997MHz spread signal bandwidth.

There are almost zero guard bands between adjacent channels. This imposes a stringent

requirement on the adjacent channel power. Table 1 lists spectral leakage specifications

of the radio. Figure 4 shows the specification pictorially.

MatchedFilter

RakeCombiner

ViterbiDecoder

SIRMeasurement

Inner LoopControl

Outer LoopControl

Frame ErrorDetector

ReceivedSignal

Transmitter PowerUp/Down Command

Frame Error Rate

TargetSIR

Measured SIR

System Overview 11

Table 1. The spectral leakage specification of the radio.

Adjacent Channel Leakage -40dBc in 5MHz band 5MHz from the center

-60dBc in 5MHz band 10MHz from the center

Spurious Emission -60dBc or less All spurs other thanadjacent channel leakage

Transmitter Intermodulation -60dBc or less External CW interferer

Figure 4. The spectral leakage diagram.

The use of QPSK linear modulation raises a design conflict with the adjacent power

requirement. QPSK signals are passed through the square root raised cosine filter to limit

the signal bandwidth in 5MHz. The QPSK signals lose their constant envelope property

after this filter operation. The peak-to-average factor of the filtered envelope of a QPSK

signal is around 4.6dB on average.

Non-constant envelope signals must be amplified by linear amplifiers to prevent spectral

regrowth. Because of the large peak-to-average factor of the QPSK modulated signal, the

back off from the 1dB output compression point of the amplifier is large. The large back

off causes inefficient power amplification or less battery life. The power handling

capability of the amplifier has to be considerably greater than the required average power

output.

40dB60dB

Transmit Signal Spectrum

33dBm

Receive Band

2110 2170

5MHz

10MHz

MHz

fo

System Overview 12

2.7 Receiver Sensitivity

W-CDMA employs pilot symbol-aided coherent detection to optimize receiver

sensitivity. The pilot symbols associates in the both uplink and downlink as shown in

Figure 5 [10].

Figure 5. Multiplexing of pilot symbols.

The pilot symbols on the downlink are time multiplexed with the TPC command and the

data; while the pilot symbols on the uplink are IQ multiplexed. The pilot symbols are

used for channel estimation at the receivers. The estimation allows the coherent detection

and automatic frequency control. Detection can achieve 10-3 BER at 6dB or less Eb/No on

the traffic channel. The specified minimum input power is –113dBm at the receiver.

2.8 Automatic Gain Control (AGC)

1st-generation analog cellular systems used frequency modulation (FM). FM receivers use

very high gain IF amplifiers with a limiter. The output to the detection circuits is fairly

constant regardless the received signal strength. AGC is generally not found in analog

cellular mobile units. However, this hard-limited non-linear amplification is not

acceptable for quadrature phase shift keying (QPSK) modulated signals. In this case, an

Data

TPCPilotQ

I

Downlink

Data

TPCPilotQ

I

Uplink

System Overview 13

AGC circuit is essential to maintain a constant input to analog-to-digital converters

(ADC). The AGC dynamic range is specified to be 80dB.

2.9 Automatic Frequency Control (AFC)

The channel estimation with pilot symbols gives a frequency estimation. The frequency

estimation gives an input to the AFC so that the received signal can be converted to

baseband precisely [11].

Let’s assume the received signal to be

])())(cos[()()( 00000 θττωωττ +−Φ+−∆+⋅−=− tttAtr c (2.3)

where

)(tΦ : is the instantaneous phase.

00 ,, θωτ ∆ : are the unknown time delay, frequency error and phase offset

respectively. They need to be estimated by the receiver.

The radio gets the estimated frequency error from the processor to drive the AFC so that

the signal can be converted to baseband precisely. (2.3) can be resolved to the in-phase

and quadrature components as

])()(cos[)()( 0000 θττωωωτ +−Φ+⋅∆+−⋅∆⋅−= tttAtI cr (2.4)

])()(sin[)()( 0000 θττωωωτ +−Φ+⋅∆+−⋅∆⋅−= tttAtQ cr (2.5)

Figure 6 shows the rotating phasor of (2.4) and (2.5).

])()([exp)(

)()()(

0000 θττωωωτ +−Φ+⋅∆+−⋅∆⋅⋅−=⋅+=

ttjtA

tQjtItR

c

rr (2.6)

System Overview 14

Figure 6. Phasor of the received signal.

If the carrier can be tracked by the AFC such that 0=∆ω , the received signal will be a

delayed version of the transmitted signal with a phase shift of 00 θτω +⋅− c . The received

signal can be detected as the delay and phase estimations are found from the signal

processing. However, if the AFC can’t track the signal for a zero frequency error, a

constant-rate phase rotation of t⋅∆ω keeps continuous moving of the signal constellation

and detection is impossible. To accomplish the precise tracking, the AFC is specified to

have very high frequency resolution at 0.03125ppm per step. The full tracking range is

±2ppm.

2.10 Receiver Selectivity and Spurious Response

To achieve the objective of maximizing the radio link performance, W-CDMA specifies

the receiver selectivity and the spurious response. Table 2 lists the selectivity and

spurious response to the radio. Figure 7 depicts the adjacent channel selectivity

specification, while Figure 8 depicts the spurious response specification.

000 )()( θττωωω +−Φ+⋅∆+−⋅∆ tt c

)( 0τ−tA

)(tQr

)(tI r

System Overview 15

Table 2. The selectivity and spurious response specification of the radio.

Adjacent Channel Selectivity 33dB or more @ 5MHz from the center

Intermodulation Response 60dB or more @ 10 and 20MHz from the center

Spurious Response 60dB or more @ 10MHz from the center

Figure 7. The adjacent channel selectivity.

Figure 8. The spurious response.

2.11 Diversity Receiver

W-CDMA employs two receivers in the radio. One is the main receiver and the other is

the diversity receiver. Providing 2-branch antenna diversity can significantly reduce the

Adjacent ChannelInterference

33dB

center

5MHz

desiredsignal

IntermodulationPair

Spurious

60dB

center

10MHz

20MHz

10MHz

desiredsignal

System Overview 16

target Eo/No for a specific BER. Adachi and Sawahashi [8] have shown 3dB diversity

gain for 10-3 BER on a field experiment in Tokyo.

The diversity receiver also facilitates the inter-frequency handover operation. W-CDMA

employs hierarchical cell structures (HCSs) that overlay macrocells on top of smaller

micro- or picocells. The HCSs boost system capacity and offer full coverage in urban

environments. However, cells of different cell layers will operate on different frequencies

as shown in Figure 9 [6]. This requires inter-frequency handover ability in the mobile

terminals.

Figure 9. Inter-frequency handover in HCS scenario.

In order to perform the seamless inter-frequency handover, the mobile terminal has to

carry out a cell search on frequency channels different from the current frequency

channel with no interruption to the current data flow. One of the receivers temporarily

branches from diversity reception to perform cell search until the handover is completed.

Macrocell

Microcell

MacrocellMacrocell

Microcell

f2

f1 f1

Inter-frequency handover

Radio Design 17

3. Radio Design

The radio is the radio front-end of a mobile terminal. The radio consists of three major

sub-systems: the transmitter, the receiver and the synthesizer. The radio has two identical

receivers for the antenna diversity purposes. Additionally, the power control (PC),

automatic frequency control (AFC) and automatic gain control (AGC) sub-circuits are

essential for the W-CDMA system objectives. The digital-to-analog converters (DAC)

and the analog-to-digital converters (ADC) are used for the interfaces between the radio

and the baseband processor. Appendix B is a full block diagram of the radio.

The discussion in this chapter includes three major sections. Each section describes one

of the sub-systems. The beginning of each section is the block diagram of the sub-system.

Referring to the block diagram, the technical specification, the design approach and

analysis, and the circuit implementation are presented.

Radio Design - Transmitter 18

3.1 Transmitter

The transmitter supports the uplink of the W-CDMA system. It provides a digital

interface for the baseband processor. The baseband processor sends the spread baseband

signal through the digital interface to the transmitter. The transmitter modulates the

baseband signals on a radio frequency (RF) carrier. The modulated RF signal is then

amplified, filtered and transmitted to the base station through the air link. To combat the

near-far problem, the transmitter operates in conjunction with a transmit power control

(TPC) to maintain the transmit power at an appropriate level. The control determines the

power level based on the digital command from the baseband processor. Figure 10 is a

block diagram of the transmitter.

3.1.1 Block Diagram

DAC - Digital-to-Analog ConverterLPF - Baseband Low Pass FilterATT - AttenuatorAMP - AmplifierBPF - RF Bandpass FilterTPC - Transmit Power ControlPA - Power AmplifierDUP-Tx - RF Duplexer (Transmitter Part)

Figure 10. Transmitter block diagram.

DAC LPF

DAC LPF

DAC

ATT ATT BPF

TPC

AMP

PA1

PA2

DUP-Tx

+45°

-45°

Local oscillatorfrom

Synthesizer


3.1.2 Technical Specifications

The key specification for the transmitter is to deliver transmit power at 1.6 W +20%, -

50% over the transmitting band (1920 – 1980 MHz). A digital command from the

baseband processor can control the transmit power over a 70dB range. The digital

command is 7-bits long. The command code is a binary number between 0000000B and

1000110B (or 0 to 70 decimal). The code 0000000B produces the maximum power

output, while the code 1000110B produces 70dB less than the maximum output. The

power control cycle time is 0.625ms.

The data rate is 128Kbps. The data sequence is spread with the spreading codes at

4.096Mcps chip rate. The modulation type is QPSK. The baseband processor sends the

direct (I) and quadrature (Q) baseband signals to the transmitter in two separate channels.

The baseband processor samples the baseband signals at 32.768Msps. The sample rate is

eight times the chip rate. The signals are sent in 8-bit digital format. The transmitter

digital-to-analog converters (DAC) reconstruct the analog signals and these signals are

filtered by 0.22 roll-off, square root raised cosine (RRC) filter. The resulting analog

signals are applied to the transmitter modulator.

As mentioned in Section 2.6 of the system overview, the zero guard bands between

adjacent channels of the W-CDMA systems imposes a stringent requirement on the

adjacent channel power. The adjacent channel power is measured with modulated signals.

The adjacent channel power of the output spectrum is 40dBc less than the inband output

power. The inband power is the total power in a 4.096MHz bandwidth about the carrier

frequency. The adjacent channel power is the total power in the 4.096MHz bandwidth

about the frequency that is ±5MHz away from the carrier frequency. The next adjacent

channel power is the total power in the 4.096MHz bandwidth about the frequency that is

±10MHz away from the carrier frequency. The next adjacent channel power is 60dBc less

than the inband power.


The spurious and intermodulation emission is measured with a continuous wave (CW).

The emission should be 60dBc less than the CW carrier.

The full specifications of the transmitter are listed in Appendix A.

3.1.3 Design Approach and Analysis

3.1.3.1 Peak-to-Average Factor

As mentioned the system overview, a QPSK signal after pulse shaping will lose its

constant envelope property. Non-linear power amplification of a non-constant envelope

signal causes spectral regrowth. Understanding the peak-to-average factor of the QPSK

signal is important in selecting the power amplifiers to avoid non-linear amplification.

A simulation was performed to find the peak-to-average factor based on the model shown

in Figure 11.

Figure 11. Simulation model for QPSK peak-to-average factor.

The model in Figure 11 is hypothetical. It does not include the W-CDMA spreading

process but a random data generator was used to approximate the PN sequence. The

QPSK modulation scheme is defined in Table 3 [12].

Random DataGenerator

QPS

KI

and

QG

ener

ator

Pulse ShapingFilter

Pulse ShapingFilter

22ss QI +

SignalEnvelope

IQPSK

QQPSK

IS

QS


Table 3. The QPSK modulation scheme.

Two Consecutive Bits Signal Phase00 225°01 135°10 315°11 45°

The pulse shaping filters are 0.22 roll-off, square root raised cosine filters. The filter

outputs are used to evaluate the signal envelope. The model is based on the complex

baseband envelope which avoids the necessity of simulating the high frequency carrier.

QPSK

QPSK is a bandwidth efficient modulation scheme. As compared to the BPSK

modulation scheme, QPSK gives the same BER performance but carries twice the data

rate in the same bandwidth. The implementation of modulation and demodulation is

simple, and, therefore, QPSK is very attractive for use in wireless communications.

The phase of a QPSK signal can take one of four possible values. The four values are

equally spaced. They are practically chosen to be 45°, 135°, 225° and 315°. The QPSK

can be mathematically represented by [13]

[ ])(2cos)( ttfAtS icQPSK θπ +⋅⋅= (3.1.1)

where

sTt ≤≤0 : sT is the symbol duration.

.4,3,2,1=i

.4

7,

4

5,

4

3,

4 4321

πθπθπθπθ ====

A : signal amplitude.

cf : carrier frequency.


For a symbol interval, (3.1.1) can be written as

[ ] [ ] )2sin()(sin)2cos()(cos)( tftAtftAtS ciciQPSK ⋅⋅⋅−⋅⋅⋅= πθπθ (3.1.2)

The direct (I) and quadrature (Q) components of the signal are defined as

[ ])(cos)( tAtI iQPSK θ⋅= (3.1.3)

[ ])(sin)( tAtQ iQPSK θ⋅= (3.1.4)

The I and Q components are baseband signals that ease the simulation.

Square Root Raised Cosine Filter

The pulse shaping filter is a square root raised cosine filter. The pulse shaping reduces the

intersymbol effects and the spectral bandwidth of baseband signals. The roll-factor of the

filter is 0.22. The transfer function of the filter in frequency domain is given by [14]

s

ss

s

s

sRRC

Tf

Tf

T

Tf

Tf

TfH

2

1

2

1

2

1

2

10

0

2

1cos1

2

1

1

)(

α

αα

α

αα

π

+>

+≤<−

−≤≤

−−+

= (3.1.5)

where

α : is the roll-off factor.


Figure 12 illustrates the ideal spectral characteristic of the square root raised cosine filter

with a 0.22 roll-off factor. The x-axis is normalized to the symbol rate. As shown in the

figure, the filter response is absolute zero after 0.61/Ts .

Figure 12. Spectral Characteristic of square root raised cosine filter with a 0.22 roll-

off.

The number of points used to sample the spectrum is 1024. An Inverse Fourier transform

(IFT) is used to obtain the time-domain impulse response of the filter. However, the

resulting filter is non-causal. The impulse response is an infinite time waveform about the

time zero. This impulse response cannot be implemented practically. Thus, the impulse

response is delayed by four symbol intervals. The first eight symbol intervals are

considered and the rest are truncated. Figure 13 shows the delayed and truncated impulse

response of the filter.

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Frequency Response of Square Root Raised Cosine Filter at 0.22 Roll-off

Frequency (normalized to the symbol rate)

Mag

nitu

de -

|Hrr

c(f)|

Spectral Characteristic of Square Root Raised Cosine Filter with a 0.22 Roll-Off

Frequency (normalized to the symbol rate)

Mag

nitu

de -

|HR

RC(f

)|


Figure 13. Delayed and truncated impulse response of the square root raised cosine

filter with a 0.22 roll-off.

Pulse Shaped I and Q signals

Pulse shaping is done by passing the I and Q signals through the filters individually.

Mathematically, it is equivalent to convolve the signals with the impulse response.

)()()( thtItI RRCQPSKs ⊗= (3.1.6)

)()()( thtQtQ RRCQPSKs ⊗= (3.1.7)

0 1 2 3 4 5 6 7 8-0.02

-0.01

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07Impulse Response of Square Root Raised Cosine Filter

Time, Tb

Mag

nitu

de

Impulse Response of Square Root Raised Cosine Filter with a 0.22 Roll-Off

h RR

C(t

)

Time (normalized to the symbol period)


Simulation

A simulation was used to generate 512 bits of random data. Two bits form a QPSK

symbol. The QPSK symbols generate the I and Q symbols. Each symbol is sampled for

16 samples. Convolution is performed on the I and Q sampled sequences with the filter

impulse response. Figure 14 shows a 50-sample segment of the I and Q signals before

and after pulse shaping.

Figure 14. A 50-sample segment of the I and Q signals before and after shaping.

50 55 60 65 70 75 80 85 90 95 100-1.5

-1

-0.5

0

0.5

1

1.5Direct Signal (I-Channel) Time Waveform

Am

plitu

de, vo

lts

Original InputShaped Output

50 55 60 65 70 75 80 85 90 95 100-1.5

-1

-0.5

0

0.5

1

1.5Direct Signal (Q-Channel) Time Waveform

Symbol Period, Ts

Am

plitu

de, vo

lts

Original InputShaped Output

Direct Signal (I-Channel) Time Waveform

Am

plitu

de, V

Am

plitu

de, V

Symbol Periods, Ts

Quadrature Signal (Q-Channel) Time Waveform


The complex envelope of the pulse shaped QPSK signals for the 50-sample segment is

shown in Figure 15.

Figure 15. The shaped signal envelope of the 50-sample segment.

Referring to the Figure 14, the original I and Q signals are digital waveforms and the

amplitude is -0.707V or 0.707V. This results in unity envelope amplitude. Figure 15

shows that the envelope of the shaped signal is no longer constant. The peak-to-average

factor can be found from the simulated samples of the signal envelope waveform by

(3.1.8).

∑=

+⋅

+=

N

kss

ssavgpk

kQkIN

kQkIF

1

22

22

/

)()(1

))()(max((3.1.8)

where

N : total number of samples

k : sample index from 1 to N

Evaluating (3.1.8) results in a peak-to-average factor of approximately 4.6dB.

50 55 60 65 70 75 80 85 90 95 100-1.5

-1

-0.5

0

0.5

1

1.5Signal Envelope Time Waveforms

Mag

nitu

de, vo

ltsSignal Envelope Time Waveform

Am

plitu

de, V

Symbol Periods, Ts


3.1.3.2 Power Amplifier Requirement

According to the specifications, the average output power of the transmitter should be

1.6W within a tolerance of -50% to +20% at the antenna port. The stringent adjacent

channel power requirement and the non-constant envelope QPSK signal prevent the use

of high-efficiency non-linear amplifiers. However, the use of linear power amplifiers for

high output power results in much higher power drain and implementation cost. To

compromise the shortcomings of linear amplification, we set the target output power of

the transmitter at 1W or 30dBm.

As shown in the block diagram in Section 3.1, there is a duplexer filter before the power

is delivered to the antenna. The insertion loss imposed by the filter is unavoidable. This

insertion is estimated to be 1.5dB. Thus, the power amplifier has to deliver 31.5dBm

average power. The power amplifier should not introduce non-linear distortion at the

peak of the QPSK signal that has a 4.6dB peak-to-average factor. Thus, the power

handling capability of the amplifier should be 36dBm or more. Power amplification of

the modulator output level to 30dBm is difficult to achieve in one stage. Two-stage

power amplifiers were used.

3.1.3.3 Receiver Desensing

The power amplification not only boosts the power level of the desired transmit signal

but also raises the noise floor of the spectrum. The rise of the spectrum noise floor can

include the receiving band (2110-2170MHz) which is 190MHz higher than the

transmitting band. However, the transmitter and the receiver share an antenna through the

duplexer. The duplexer is a three-port filter. The three ports accommodate the transmitter,

the receiver and the antenna simultaneously. The use of the duplexer saves an antenna.

On the other hand, it introduces a physical path between the transmitter and the receiver.

If the power in the receiving band due to the transmitter is not properly suppressed,

turning on the transmitter will degrade the receiver sensitivity. This phenomena is called

receiver desensing.


A power budget study is done to ensure no receiver desense. Figure 16 depicts the

specified transmit power spectrum.

Figure 16. The specified transmit power spectrum.

The transmit power spectrum specifies for a 30dBm transmit carrier. The adjacent

channel power and out-band suppressions are 40dBc and 60dBc respectively. The

transmit power spectrum has 60dB suppression in the receiving band. The noise floor in

the receiving band due to the transmitter is –30dBm (i.e. 30dBm – 60dB). This noise

floor is much greater than the specified –113dBm receiver sensitivity. The transmitter can

cause serious receiver desense.

Filtering the transmit power spectrum is necessary to drive down the noise floor in the

receiving band by 83dB or more. The duplexer and the RF bandpass filter (BPF) in the

transmitter are the devices used to provide the suppression. They will be discussed in the

circuit level design section.

40dB60dB

Target Transmit Power Spectrum

30dBm

Receive Band

2110 2170

5MHz

10MHz

MHz

fo

Less than –113dBm83dB

Filter Suppression


3.1.3.4 Transmit Power Control (TPC)

The transmitter should provide 70dB transmit power control range. Specifying the target

output power as 30dBm, the range of the transmit output power is from –40dBm to

30dBm. In order to achieve the power control, RF attenuators are used to adjust the

power amplifier drive level. It is difficult to use one attenuator to provide the 70dB

control range. The board feed-through can limit the maximum isolation between two

nodes on the printed circuit board. If the intended attenuation of an attenuator is greater

than the board feed-through, the attenuation becomes board limited rather than device

limited. The attenuation of the attenuator beyond the board limit becomes unpredictable.

Two attenuators were employed in the transmitter chain to ensure that the attenuation is

device limited.

3.1.4 Circuit Level Design

Following the flow of the signal as shown in the block diagram in Section 3.1.1, the

discussion of this section proceeds from the digital interface to the duplexer. Detailed

schematics are in Appendices C-1 and C-2. The discussion of the circuits refers to the

schematics for the component designators. The hardware implementation of the

transmitter comprises five assemblies. They are the digital-to-analog board, the

modulator board, the power control, the power amplifier and the duplexer. Each assembly

is discussed in following sub-section.

3.1.4.1 Digital-to-Analog Conversion (DAC) Board

The DAC board provides the interface between the baseband processor and the

transmitter. It accepts the I and Q baseband signals in 8-bit digital format from the

baseband processor and outputs the I and Q signals in analog form to the modulator.

Figure 17 is the DAC block diagram. The full schematic is in Appendix C-1.


Figure 17. Block diagram of the DAC board.

AD9708 DAC

The AD9708 is a 8-bit digital-to-analog converter from Analog Devices. There are two

AD9708’s (Appendix C-1: U1, U3) on the board. Each device corresponds to one (I or Q)

baseband channel. They convert the digital baseband signals from the baseband processor

to analog signals. The devices are capable of 100Msps but actually operate at

32.765Msps. The devices are set for a full range differential output at 0.5V peak.

AD8072 Operational Amplifier

The outputs of the DACs are connected to the Analog Devices AD8075 operational

amplifiers. There are two AD8075’s (Appendix C-1: U2, U4) on the board. Each device

corresponds to one baseband channel. Each AD8075 package contains two operational

amplifiers. One of the amplifiers buffers the DAC from the baseband low pass filter

(LPF) and provides a voltage gain of two. The other amplifier buffers the LPF output

from the modulator. The voltage gain of this amplifier is adjusted so that the full-scale

output to the modulator is 0.5V peak.

DAC LPF

DAC LPF

Quadrature (Q) Channel

Direct (I) Channel

AMP - operational amplifierLPF - Low Pass Filter

AMP

AMP AMP

AMP

0.5Vpk

0.5Vpk

to modulator


Baseband Low Pass Filter

The baseband low pass filters are from Soshin. They are 0.22 roll-off square root raised

cosine filters. There are two filters (Appendix C-1: F1, F2) on the board. Each filter

corresponds to one baseband channel. They are pulse shaping and anti-aliasing filters.

Pulse shaping is performed to limit the baseband signal bandwidth. The DAC outputs are

composed of the baseband spectrum and the replicas of the baseband spectrum at every

integer multiple of the 32.768MHz sampling frequency. The filters remove all the

replicas to prevent aliasing. The measured frequency response of the filter is shown in

Figure 18.

Figure 18. Frequency response of the Soshin baseband low pass filter.

The filter starts to roll-off at 1.6MHz and the absolute cut-off is at 2.6MHz. Comparing

the theoretical response of the filter given in Figure 12 of Section 3.1.3.1 that the actual

roll-off starts at 1.64MHz and the absolute cut-off is 2.46MHz. There are small

Frequency Response of Baseband Square Root Raised Cosine Filter

-40

-35

-30

-25

-20

-15

-10

-5

0

0 500000 1000000 1500000 2000000 2500000 3000000

Frequency in Hz


differences between the theoretical values and the measured values. These are the

measurement errors. The measurement error at the absolute cut-off is larger because the

signal to be measured at the absolute cut-off is small. The measurement accuracy is more

vulnerable to the noise influence in the system.

3.1.4.2 Modulator Board

The modulator board performs the modulation and power control functions. Figure 19 is

the block diagram. The full schematic is in Appendix C-2.

Figure 19. Block diagram of the modulator board.

RF2422 Modulator

The modulator chip (Appendix C-2: U4) is a RFMD RF2422. It modulates the baseband

signals on the RF carrier (1.92GHz – 1.98GHz). The RF carrier level is set at –1.5dBm,

while the both I and Q baseband signal levels are set at 0.5V peak. This baseband input

was set to maintain low adjacent channel power. The modulated output has 50dB

adjacent channel power suppression that gives 10dB margin for the subsequent power

amplifier with respect to the –40dBc specification.

ATT ATT

AMP

+45°

-45°

I-Channel

Q-Channel

RF Carrier-1.5dBm

Power ControlVoltage

BPF

0.5Vpk

0.5Vpk

-13dBm


AT-108 Attenuator

There are two M/A COM AT-108 attenuators on the modulator board. One (Appendix C-

2: U2) is at the modulator output and the other (Appendix C-2: U1) is at the output of an

amplifier. The attenuator has 40dB attenuation range but the design makes use of a 35dB

range to meet the 70dB control range requirement. The attenuation is determined by a

control voltage from the transmit power control. The control voltage can run between 0 to

5V. A 5V voltage gives a minimum attenuation of 3.5dB which is the insertion loss of the

attenuator. As the voltage decreases, the attenuation increases till the total attenuation is

43.5dB (the 40dB attenuation plus the 3.5dB insertion loss). For the 35dB attenuation

range, the minimum control voltage is set at approximately 0.5V.

Amplifier

A Mini-Circuits ERA-5 monolithic amplifier (Appendix C-2: U3) is used as a gain block

to compensate for the miscellaneous losses in the circuit, such as the insertion losses of

the attenuator and the filter. The gain of this amplifier is 20dB. This amplifier has 50Ω

standard input and output ports. It is easy to use and stable. The bias circuit is simple as

shown in Figure 20 [15].

Vcc

Cs R bias

Lbias

ERA

O U T

Cc

IN

Cc

Figure 20. Bias Configuration for ERA amplifiers.

Vd

Ibias


The RF choke should be chosen such that its reactance is at least 500Ω. Based on this

criterion, a 39nH choke is used.

The ERA-amplifiers are biased with a supply voltage )( ccV higher than the device

voltage )( dV for stable performance. The higher supply voltage allows larger bias

resistances )( biasR and hence the variation of the bias conditions against temperature is

reduced [15]. However, a large voltage difference is not favorable to the use of chip

resistors because more voltage difference causes more power dissipation in the bias

resistor. To allow the use of chip resistors, the 6V supply is chosen. The bias resistance is

calculated (3.1.9) based on the bias parameters of the amplifiers from the data sheets.

( )bias

dccbias I

VVR

−= (3.1.9)

RF Bandpass Filter (BPF)

This is a dielectric filter (Appendix C-2: U7) from Soshin. Its passband band covers the

transmit band with a 2.5dB insertion loss. Its out-band rejection is 30dB. It removes the

spectral impurity of the signals. As mentioned in Section 3.1.3.3, there is a need for 83dB

power suppression in the receiving band. This BPF produces 30dB of the suppression.

Resistive Pad

There are two π-type resistive pads. Resistance values for π-type resistive attenuator is

given in [16]. One (Appendix C-2: R11, R13, R16) is at the output of the modulator chip

and the other (Appendix C-2: R70, R71, R72) is at the output of the RF BPF. The use of

the pads improve the stability of the PA driver. They set the output level of the modulator

at –13dBm. The –13dBm output level prevents the subsequent power amplifier from

operating in saturation to ensure good adjacent channel power suppression.


3.1.4.3 Transmit Power Control (TPC)

The TPC resides on the automatic frequency control (AFC) board that will be discussed

in the receiver section. The control includes an ADC and a level shifting circuit as shown

in the block diagram in Figure 21. The schematic is in Appendix C-5.

Figure 21. Block diagram of the power control.

The TPC accepts a 7-bit digital command from the baseband processor and provides a

scaled analog voltage to drive the attenuator on the modulator board. The control voltage

is connected to the two attenuators in parallel. The required attenuation is evenly

distributed between the two attenuators. The command code is between 0000000B and

1000110B (or 0 to 70 decimal). The analog voltage output is from 5V to 0.5V. The code

0000000B produces 5V analog voltage output, while the code 1000110B produces 0.5V

analog output.

AD557 DAC

The AD557 (Appendix C-5: U5) is a 8-bit digital-to-analog converter (DAC) from

Analog Devices. It is the interface between the baseband processor and the TPC. The

DAC has one bit more than the command length. In order to fully utilize the output range

of the DAC, the command digits are tied to the most significant 7-bits of the DAC and

the least significant bit is held high. Thus, the command is effectively multiplied by a

factor of 2. Table 4 lists the input-output relationship of the DAC.

Table 4. The input-output relationship of the DAC.

Output Power Command AD557 DAC out (V)30dBm maximum 0000000 0.01-40dBm minimum 1000110 1.41

DAC TPC Analog Voltage Outputto Modulator Board


The 10mV residual voltage is a result of the least significant bit being tied high. The

maximum output settling time of the DAC is 1.5µs so that the DAC easily supports the

0.625ms power control cycle time.

Level Shifting Circuit

The level shifting circuit is built with a LM6132 (Appendix C-5: U10) chip from

National Semiconductor. The device contains two operational amplifiers. The two

amplifiers form a two-stage level shifting circuit. The 1st stage is a voltage follower

(Appendix C-5: U10A) required to buffer the DAC output. The 2nd stage is an inverting

amplifier (Appendix C-5: U10B) needed to produce the phase inversion and the level

shifting as shown in Table 5.

Table 5. The input-output relationship of the level shifting circuit.

Output Power Analog in from DAC (V) Analog out (V)

30dBm maximum 0.01 5

-40dBm minimum 1.41 0.5

The exact level shifting is not well defined in practice because of the variation of the RF

attenuation. Two variable resistors (VR) are used to provide the adjustment of the level

shifting so that the variation can be compensated. One VR (Appendix C-5: R19) is used

to shift the analog output up or down. The other VR (Appendix C-5: R18) is used to set

the slope of the input-output relationship. The two adjustments provide the flexibility to

set the maximum and minimum of the analog output.

3.1.4.4 Power Amplifier

The power amplifier boosts the –13dBm transmit signal from the modulator board to

31.5dBm. The output should have 40dBc or more adjacent channel power suppression.


The required gain of the amplifier is 44.5dB. As mentioned in Section 3.1.3.2, the power

handling capability of the amplifier should be 36dBm to address the 4.6dB peak-to-

average factor of QPSK signals.

The power amplifier is a two-stage implementation for the high gain and high power

requirement. Figure 22 is the block diagram.

Figure 22. Two-stage power amplifier.

Both stages are built with Celeritek devices. The 1st stage is the CCS1933 evaluation

board from Celeritek. The first trial of the power amplifier implementation only utilized

the CCS1933. However, the adjacent channel power suppression was unsatisfactory

because the CCS1933’s power handling capability is 33dBm (3dB below the

requirement). To address this problem, a 2nd stage is to be added after the CCS1933.

CFH2162-P3 was chosen for this stage because it has 36dBm power handling capability.

The 1st stage of the CCS1933 evaluation board produces 35dB gain and boosts the

transmit power to 22dBm. Experiments reveal that the adjacent channel power

suppression at the 22dBm power output is 41dBc.

The CCS1933 board consists of a driver amplifier (CMM1301) and a matched power

amplifier (CFK2162-P3). Both of them operate from a 5Vdc supply. The CMM1301

drive amplifier is biased for 150mA drain current with a negative gate voltage. The

CFK2162-P3 power amplifier is matched on board for 50Ω. It is biased for 1.2A drain

current with another negative gate voltage. Both the negative gate voltages are derived

from a –5Vdc supply through resistive potential dividers. The potential dividers are built

CeleritekCCS1933

CeleritekCFH2162-P3

-13dBmfrom modulator board

31.5dBmto duplexer


with multi-turn potentiometers to facilitate a precise bias adjustment. To prevent damage

to the two amplifiers, the negative bias voltages must be applied to the amplifiers before

the 5Vdc drain supply.

The 2nd stage being considered is the Celeritek CFH2162-P3 power amplifier. The 1dB

output compression point of the amplifier is 36dBm. This meets the required power

handling capability of 36dBm. The input to this amplifier is around 22dBm and the

amplifier delivers 31.5dBm transmit power. The 31.5dBm output power is 4.5dB below

the 1dB output compression point so that linear operation of the amplifier will contribute

insignificant adjacent channel power. Thus the specified 40dBc adjacent channel power

suppression can be achieved.

3.1.4.5 Duplexer – Transmitter part

The duplexer was designed and built by Dr. Sweeney. It is a three-port filter device. It

includes a transmitting bandpass filter and a receiving bandpass filter. The use of the

duplexer allows the radio to simultaneously transmit and receiver on a single antenna.

This saves the cost of a separate antenna and eases the system construction. Figure 23

depicts the physical layout of the duplexer.

Figure 23. Physical layout of the duplexer.

1920MHz 1980MHz 2110MHz 2170MHz

Antenna Port

Transmitter Port Receiver Port


The output of the power amplifier is connected to the transmitter port of the duplexer.

The insertion loss of the duplexer in the transmitting band is 1.5dB. Thus the available

transmitter power at the antenna is 30dBm. As mentioned in Section 3.1.3.3, the use of

the duplexer may cause the receiver desense if the suppression of the noise at the

receiving band is not adequate. The transmitting bandpass filter of the duplexer is

designed to have a notch at the receiving band. The notch gives 70dB rejection to the

receiving band. This 70dB rejection and the 30dB rejection from the RF BPF makes up

100dB receiving band rejection that is higher than the required 83dB rejection. Thus the

receiver desense problem is well addressed. Figure 24 shows the simulated characteristics

of the duplexer.

Figure 24. Duplexer Characteristics.

Tx BandRejection ≅76dB

Tx Filter Rx Filter

Rx BandRejection ≅76dB

TI Duplexer Characteristics

-120

-96

-72

-48

-24

0

1.90 1.95 2.00 2.05 2.10 2.15 2.20

Frequency (GHz)

-20

-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Rx - S21 Tx - S31 Return Loss - S11


The receiving filter response curve (Rx-S21) shows that the transmit power rejection is

approximately 76dB. The transmitting bandpass filter also provides approximately 76dB

rejection to the receiving band as shown in the transmitting filter response curve (Tx-

S31). The return losses of the filter in the receiving band and the transmitting band are

both approximately 13dB as shown the return loss curve (Return Loss–S11).

The measured performance of the duplexer is tabulated in Table 6. The measured data

match the simulated data well.

Table 6. Measured performance of the duplexer.

Transmitting Band Receiving Band

Insertion Loss (dB) 1.8 1.0

1dB Bandwidth (MHz) 71.3 66.3

3dB Bandwidth (MHz) 76.3 73.8

Receiving Band Rejection (dB)

2110 MHz 74

2140 MHz 71

2170 MHz 72

Transmitting Band Rejection (dB)

1920 MHz 74

1950 MHz 73

1980 MHz 74

Radio Design – Receiver 41

3.2 Receiver

The receiver supports the downlink of the W-CDMA system. It receives the radio

frequency signal from a distant base station. The front-end of the receiver processes the

radio frequency (RF) and intermediate frequency (IF) signals. The demodulator of the

receiver recovers the baseband signals from the IF signals. The last stage of the receiver

consists of analog-to-digital converters (ADC). These converters are the interface

between the receiver and the baseband processor. The converters digitize the baseband

signals and provide the digital outputs to the baseband processor.

The receiver operates in conjunction with the automatic gain control (AGC) and the

automatic frequency control (AFC). The AGC improves the dynamic range of the

receiver by maintaining a constant signal level at the input of the ADCs. The AFC

improves the receiver sensitivity by producing precise baseband demodulation.

There are two identical receivers in the radio. One of the receivers shares the antenna

with the transmitter through the duplexer and is called the main receiver. The other

receiver has its own diversity antenna and is called the diversity receiver. The two

receivers provide an antenna diversity gain to improve the reception performance and

facilitate the inter-frequency handover.

Figure 25 in the following section is the block diagram of the receiver. Only the main

receiver is shown but the block diagram applies to the diversity receiver as well. The

main and diversity receivers are identical.


3.2.1 Block Diagram

DUP-Rx - RF Duplexer (Receiver Part) AMP - AmplifierLNA - Low Noise Amplifier AGC - Automatic Gain ControlATT - Attenuator DEMOD - DemodulatorBPF - Bandpass Filter BB - BasebandRF - Radio Frequency LPF - Low Pass FilterMIX - Mixer DAC - Digital-to-Analog ConverterLO - Local Oscillation ADC - Analog-to-Digital ConverterIF - Intermediate Frequency AFC - Automatic Frequency Control

Figure 25. Receiver block diagram (Only the main receiver is shown in the diagram.

The main and diversity receivers are identical.)

ATTBPFBPF

BPF

ADC LPF

ADC LPF

÷2

-45°

DAC AGC

+45°

AFC

DEMOD

MIX 2 AMP 2 AMP 1IF 1 MIX 1

AMP 3 AMP 4IF 2

LNA

DAC

DUP-Rx

LO 1LO 2

AGC AMPBB AMP

BB AMP

RF



The key specification for the receiver is the reception sensitivity. The receiver produces

10-3 bit-error-rate (BER) at –113dBm or less input power level on the traffic channel.

This received power level produces 6dB or greater Eb/No for the baseband processor to

perform the detection. The traffic channel throughput is 128Kbps. The operating band of

the receiver is 2110-2170MHz. The dynamic range of the receiver is 80dB. This means

that the receiver can receive a signal from –113dBm to –33dBm. The AGC adjusts the

gain of the receiver chain to maintain a constant signal level at the ADC inputs. The

baseband processor provides the control command for the AGC. This digital command is

7-bit long. The command code is a binary number between 0000000B and 1010000B (or

0 to 80 in decimal). The code 0000000B produces the maximum gain of the receiver

chain, while the code 1010000B produces a gain of 80dB less than the maximum.

The received signal is a QPSK modulated direct sequence spread spectrum signal. The

bandwidth of the signal is 5MHz. The carrier frequency of the signal is in the receiving

band (2110-2170MHz) which is 190MHz higher than the transmitting band.

The receiver uses a double-conversion superheterodyne architecture. The 1st down-

conversion converts the received RF signal to a 190MHz IF. The 2nd down-conversion

converts the 190MHz IF to a 70MHz IF. A QPSK demodulator recovers the baseband I

and Q signals from the 70MHz IF. The I and Q signals are filtered and digitized. Finally,

the digitized samples are sent to the baseband processor.

The 1st down-conversion requires a local oscillation (LO) from 1920MHz to 1980MHz

(the transmit band) so that the received frequency from 2110MHz to 2170MHz is

converted to 190MHz. The 2nd down-conversion requires a LO at 260MHz to convert the

190MHz IF to the 70MHz IF. The LOs are generated by the synthesizer that will be

discussed in Section 3.3.


As mentioned in Section 2.9 of the system overview, the AFC is essential for precise

demodulation and optimum detection. The AFC is a 140MHz local oscillator. The

140MHz LO is fed to the QPSK demodulator. The demodulator uses the 140MHz LO to

recover the baseband I and Q signals. The nominal frequency of the AFC is 140MHz.

The adjustable range of the frequency is ±2ppm and the frequency resolution of the

adjustment is 0.03125ppm per step. The baseband processor commands the AFC with a

7-bit command code. The command code is a binary number between 0000000B and

1111111B (or 0 to 127 in decimal). The code 0000000B produces a –2ppm shift from

140MHz, while the code 1111111B produces a +2ppm shift. The drift also affects the

transmit and LO frequencies.

The demodulator has a divide-by-two divider that divides the 140MHz LO to two 70MHz

LOs. The two 70MHz LOs have a 90° phase difference. The in-phase LO is used to

recover the I signal, while the quadrature LO is used to recover the Q signal.

The I and Q signals are separately filtered and digitized. The baseband filters are 0.22

roll-off, square root raised cosine filters. The sampling rate of the digitization is

32.768Msps. The digital samples are 8-bit long.

The adjacent channel selectivity, intermodulation selectivity, and the spurious response of

the receiver were tested with continuous wave (CW) signals. The adjacent channel

selectivity is required to be greater than 33dBc. The intermodulation selectivity and the

spurious response are both required to be greater than 60dBc. The W-CDMA system

provides twelve frequency channels for FDMA operation. Poor receiver selectivity

results in interference from users at adjacent channels and limits the system performance.

As mentioned before, two identical receivers are installed in a radio to provide antenna

diversity. The technical specifications apply to the both receivers.

The full specifications of the receivers are listed in Appendix A.


3.2.3 Design Approach and Analysis

3.2.3.1 Receiver Noise Figure

The receiver must produces a BER of 10-3 at –113dBm or less input power level on the

traffic channel. This received power level produces 6dB or greater Eb/No for the baseband

processor to perform the detection. The traffic channel throughput is 128Kbps. The

required noise figure can be found as follows [17].

The thermal noise, N, in communication receivers is modeled as an additive white

Gaussian noise (AWGN) that is given be

BTkN e ⋅⋅= (watts) (3.2.1)

where

k : is Boltzmann’s constant, 1.38x10-23 J/K.

Te : is the effective system noise temperature in Kelvin.

B : is the bandwidth in Hz.

Hence, the noise power spectral density, No, (noise power in 1 Hz bandwidth) is

eo kTN = (W/Hz) (3.2.2)

The bit energy, the bit period, the noise power spectral density and the received power

are related by (3.2.3).

o

br

o

b

N

TP

N

E ⋅= (3.2.3)


where

RTb

1= : is the bit period or the reciprocal of the data rate.

(3.2.2) and (3.2.3) are combined to obtain

RkN

EPT

o

bre ⋅

⋅

⋅=

−1

1

(3.2.4)

or

)log(10)log(10)()()log(10 RkdBN

EdBWPT

o

bre ⋅−⋅−

−=⋅ (3.2.5)

According to the specifications of the –113dBm received power and the 6dB Eb/No

dBWdBmPr ⋅−=⋅−= 143113

dBN

E

o

b ⋅=

6

dBRkbpsR ⋅=⋅⇒⋅= 51)log(10128

dBHzKdBWdBdBWdBTe ⋅=−−+−−= 6.2851)/(6.228)(6)(143)(

or

KTe ⋅= 44.724

The receiver noise figure, nf, is

5.3290

1 =+= eTnf or dBNF ⋅= 4.5


3.2.3.2. Heterodyne Architecture and Spurious Analysis

The receiver uses a double-conversion superheterodyne front-end. The superheterodyne

architecture helps to bring down high frequency signals at much lower intermediate

frequencies (IF) so as to relax the Q requirement of the channel-select filter [18].

However, if the high frequencies are brought down to low frequencies in one conversion,

image frequencies are difficult to reject at a satisfactory level from the image-rejection

filter. Double-conversion allows a higher IF for the first conversion so that image

suppression is easier. The second-conversion allows a lower IF for better channel

selectivity. However, double-conversion introduces more image frequencies to the

system. Figure 26 illustrates the superheterodyne architecture used in the receiver.

Figure 26. Block diagram of the superheterodyne receiver.

Choosing IF Frequencies

190MHz and 70MHz were chosen to be the 1st ( IFf _1 ) and the 2nd ( IFf _2 ) IF frequencies

respectively. The corresponding 1st ( LOf _1 ) and 2nd ( LOf _2 ) local oscillation (LO)

frequencies are 1920-1980MHz and 260MHz respectively. This section explains the

reasons for choosing these two IF frequencies.

The 1st IF was chosen to match the channel offset of 190MHz between the transmitting

and receiving bands. Therefore, the radio only needs one RF synthesizer. The output of

the synthesizer can be used for the transmitter as well as the LO of the 1st down-

conversion of the receiver.

Duplexer BPF

1st Mixer 2nd Mixer

BPF

190MHz

70MHz

260MHz1920–1980MHz

2110-2170MHz

LNA 2110-2170MHz


The choice of the IF frequencies is based on the performance of the spurious response.

Each down-conversion introduces an image frequency. The image can be mixed to the

same IF as the desired signal. In considering the middle receiving channel of the W-

CDMA system, MHzf RF 5.2142= and MHzf LO 5.1952_1 = are the desired RF and 1st

LO frequencies respectively. This is a low-side injection scheme because the 1st LO

frequency is lower than the RF frequency. The 1st IF frequency is found by

MHzffff IFLORFIF 1905.19525.2142_1_1_1 =−=⇒−= (3.2.6)

However, there is a frequency on the other side of the 1st LO frequency which produces

the same 1st IF frequency.

MHzffff IMGIMGLOIF 5.17621905.1952_1_1_1_1 =−=⇒−= (3.2.7)

This frequency is the 1st image frequency. For the double-conversion receiver, there are

two more image frequencies. The 2nd conversion is a high-side injection scheme because

the LO frequency is higher than the input frequency.

IFLOIF fff _1_2_2 −= (3.2.8)

The image frequency at the 2nd conversion is

MHzffff IMGIFIFLOIMGIF 33070260__2_2_2__2 =+=⇒+= (3.2.9)

The two additional image frequencies in the RF band are

MHzffff IMGIMGIFLOIMG 5.16223305.1952_2__2_1_2 =−=⇒−= (3.2.10)

MHzffff IMGIMGIFLOIMG 5.22823305.1952_3__2_1_3 =+=⇒+= (3.2.11)


Figure 27 shows these frequencies pictorially.

MHzf LO 260_2 = MHzf RF 5.2142=

MHzf IF 190_1 = MHzf LO 5.1952_1 =

MHzf IMGIF 330__2 = MHzf IMG 5.1762_1 =

MHzf IMG 5.1622_2 =

MHzf IMG 5.2282_3 =

Figure 27. Images of the double-conversion receiver

Removing the images depends on the choice of the IF frequencies and filters. If the 2nd IF

frequency is chosen to be small, the 3rd image frequency is close to the desired RF band.

The front-end filter has little rejection on the 3rd image. Therefore, the rejection of the 3rd

image depends on the 1st IF filter which is the filter following the 1st down-conversion.

The center frequency of this 1st IF filter is 190MHz.

Substitute (3.2.29) into (3.2.11)

IFLOLOIMG ffff _2_2_1_3 ++= (3.2.12)

Substitute (3.2.8) into (3.2.6). The desired RF frequency is

IFLOLOIFLORF ffffff _2_2_1_1_1 −+=+= (3.2.13)

f

f1_LOf2_LO fRFf1_IF

f2_IF_IMG f1_IMGf2_IMG f3_IMG

1st IF Band RF Band


Then, the difference between the 3rd image frequency and the desired RF frequency is

MHzMHzfff IFRFIMG 1407022 _2_3 =⋅=⋅=− (3.2.14)

The passband of the W-CDMA system is 60MHz. The above example is worked on the

middle channel. The passband is ±30MHz about the middle channel. Therefore, the 3rd

image frequency is outside the passband by 110MHz (=140-30MHz). The front-end filter

can provide a good rejection to this 3rd image frequency. The subsequent 190MHz SAW

filter also suppresses the image significantly.

Many analog systems choose 455KHz as the 2nd IF. Technically, those systems allow the

image in the RF passband and need the 1st IF filter to take care of the rejection. This

approach requires high-selectivity 1st IF filters.

In addition to the images, there is an additional spurious response. It is called the half-IF

response. It is due to the second harmonic generations of mixers.

The 1st half-IF frequency at the 1st conversion is given by

MHzfff LORF 5.2047)5.19525.2142(2

1)(

2

1_1

21_1

=+⋅=+⋅= (3.2.15)

and

MHzfffff IFLORFRF 951902

1

2

1)(

2

1_1_1

21_1

=⋅=⋅=−⋅=− (3.2.16)

(3.2.16) reveals that the 1st half-IF frequency is away from the desired RF frequency by a

half of the 1st IF frequency. The 1st half-IF spur is close to the receiver passband.

The 2nd half-IF spur may produce the 2nd IF image which is given by (3.2.9).


MHzfff LOIMGIF 5.21175.19523302

1

2

1_1__2

21_2

=+⋅=+⋅= (3.2.17)

Substitute (3.2.6) and (3.2.9) into (3.2.17)

MHzffff IFIFRF 251902

170

2

1_1_2

21_2

−=⋅−=⋅−=− (3.2.18)

The 2nd half-IF frequency is in the receiver passband.

The half-IF spurs are close or in the receiver passband. The front-end filter may not reject

it. Figure 28 shows the half-IF spurs and the system passband pictorially. The 2th-order

distortion of the mixers must be minimized; otherwise, the half-IF spur can be significant.

Balanced mixers, which suppress the even harmonics, are used in the radio to reduce

some of the spurious mixing products.

Figure 28. Half_IF spurs.

Computer analysis using the program called Spurious and Filter Analysis [19] was

performed to verify the spurious response of the frequency plan. The simulation is based

on the selected Mini-Circuit mixers (1st mixer SCM-2500 and 2nd mixer TUF-3SM) and

filters (front-end duplexer designed and built by Dr. Sweeney, Soshin post-LNA filter

and NDK 1st IF SAW filter).

21_1

f2

1_2f

RFf

2110MHz 2170MHz

Receiver Passband


Table 7 shows the critical spurious of the frequency plan. The significant spurs on this

table are the 2nd half-IF frequencies of 2117.5MHz and 2142.5MHz because they are in

the receiver passband. Because of the non-ideal filter characteristic, the 2nd half-IF

frequency of 2087.5MHz can be significant as well.

Table 7. Critical spurious frequencies in the frequency plan.

Spurious Bottom Channel

2112.5 MHz

Middle Channel

2142.5 MHz

Top Channel

2167.5 MHz

1st Image 1732.5 1762.5 1787.5

2nd Image 1592.5 1622.5 1647.5

3rd Image 2252.5 2282.5 2307.5

1st Half-IF 2017.5 2047.5 2072.5

2nd Half-IF 2087.5 2117.5 2142.5

Spurious and Filter Analysis can evaluate a single-conversion system. The inputs for the

program are the device parameters and the system parameters. The device parameters are

the frequency response of the filter and the mixing product table of the mixer. These

parameters can be obtained from the manufacturer data sheets. The mixing product table

provides the output levels of the mixer products. The mixer products are the frequencies

of LORF fnfm ⋅±⋅ . The m and n are integers. The manufacturers provide the output

levels in a quantity relative to the desired output of LORF ff ± . The products are provided

for m and n from 0 to 10. The system parameters are the desired RF frequency, the LO

frequency and the target IF frequency. The program can find the RF spurs (or

frequencies) which produce the target IF frequency, and the relative level of the spurs

with respect to the desired RF frequency. Therefore, the spur attenuation of the

conversion is obtained.

Since the program can only evaluate one conversion at a time, the analysis of a double-

conversion system has three parts. The first part is to evlauate the 1st conversion for the


1st image and the 1st half-IF. The system parameters are the desired RF frequency

( MHzf RF 5.2142= ), the 1st LO frequency ( MHzf LO 5.1952_1 = ) and the 1st IF frequency

( MHzf IF 190_1 = ) for the middle channel. The device parameters are the combined

frequency response of the duplexer and the Soshin post-LNA filter, as well as the mixing

product table of the Mini-Circuits SCM-2500 mixer. Appendix D-1 contains the result of

this analysis. Figure 29 is a copy of Appendix D-1 and is shown here as an example. It

shows all spurs associated with the 1st down-conversion process in the middle channel

(2142.5MHz). The spurious attenuation is found to be at least 110dB. The rejections of

the 1st image (1762.5MHz) and the 1st half-IF (2047.5MHz) are 110dB and 159.3dB

respectively. The rejection is much larger than the 60dB minimum requirement.

Therefore, the spurious response of the 1st down conversion meets the specifications.

Figure 29. Example of the part 1 spurious analysis (Appendix D-1).

1st Image

1st Half-IF


The second part is to evlauate the 1st conversion for the 2nd and 3rd images, and the 2nd

half-IF. The system and device parameters are the same except the target IF frequency

( MHzf IMGIF 330__2 = ). It is the image frequency associated with the 2nd conversion

process. Appendix D-2 contains the analysis results and is shown here as Figure 30. It

shows that the rejections of the 2nd (1622.5MHz) and 3rd (2282.5MHz) images are 110dB

and 75.4dB respectively. They meet the specifications. The 2nd (2117.5MHz) half-IF

rejection is 49dB. The 1st IF SAW filter must provide further rejection. The low 2nd half-

IF rejection is because the 2nd half-IF falls in the receiver passband. This highlights the

importance of IF SAW filters in rejecting the in-band spurious.


2nd Image

3rd Image

2nd Half-IF


The third part is to evaluate the 2nd half-IF rejection of the 2nd conversion. The system

parameters are the desired 1st IF frequency ( MHzf IF 190_1 = ), the 2nd LO frequency

( MHzf LO 260_2 = ) and the 2nd IF frequency ( MHzf IF 70_2 = ). The device parameters

are the frequency response of the NDK SAW filter, and the mixing product table of the

Mini-Circuits TUF-3SM mixer. Appendix D-3 contains the results of this analysis and is

shown here as Figure 31. It shows that the 2nd conversion provides 40dB rejection to the

image (330MHz). Therefore, the total rejection of the 2nd half-IF is 89dB and meets the

specifications.


2nd IF Image


Similar computer analysis was carried on the bottom and top channels. The third part of

the analysis is same to all channels because the 2nd conversion is channel independent.

The analysis results on these channels can be found in Appendix D-4 through D-7. Table

8 summarizes the analysis results. The frequency plan meets the specifications on all

channels.

Table 8. Summary of the spurious rejection of the frequency plan.

Spurious Rejection

in dB

Bottom Channel

2112.5 MHz

Middle Channel

2142.5 MHz

Top Channel

2167.5 MHz

1st Image 110 110 110

2nd Image 150 150 150

3rd Image 101.2 115.4 125.1

1st Half-IF 193.6 159.3 121.4

2nd Half-IF 131.7 89 89

Channel Selectivity

The IF filters determine the channel selectivity of the radio. The filter bandwidth is equal

to the 5MHz channel bandwidth. SAW filters are commonly used as IF filters because

their high-selectivity frequency response. The receiver has two IF SAW filters at

190MHz and 70MHz. The adjacent channel rejections of the 190MHz 1st and 70MHz 2nd

IF filter are 45dB and 50dB respectively. The total channel selectivity is 95dB; that is

well above the specified 33dB channel selectivity.

3.2.3.3. Cascaded Receiver Chain Analysis

The receiver is a cascaded system with amplifiers, filters and mixers. The cascaded

system has to meet the noise figure requirements, signal gain requirement, and

intermodulation specifications simultaneously. The required noise figure is 5.4dB as

discussed in Section 3.2.3.1. The cascaded gain should be large enough to bring up the


signal from the specified minimum level (i.e. –113dBm) to a specified drive level of the

demodulator.

Intermodulation distortion is due to the non-linearity of the receiver, especially the 3rd-

order distortion. Intermodulation distortion is harmful because the distortion is caused by

the adjacent channel interferers. Since the interferers are in-band signals, the front-end

filter provides no rejection. Consider a scenario that the receiver is detecting a weak

signal that is accompanied by two strong interferers. The frequency of the desired signal

is sf . The frequencies of the interferers are fff si ∆+=1_ , and fff si ∆⋅+= 22_ . f∆ is

channel bandwidth. Figure 32 shows them pictorially.

Figure 32. Intermodulation interference.

The non-linearity of the receiver can be expressed as a power series (3.2.19).

.....33

2210 ++++= vavavaavo (3.2.19)

The first two terms ( vaa 10 + ) are the linear terms. The terms with power of 2 or more are

the non-linear terms that create distortion.

The two interferers are represented by [20]

twtwv ii 2_1_ coscos += (3.2.20)

where

1_1_ 2 ii fw π= and 2_2_ 2 ii fw π=

fs fi_1 fi_2

∆f ∆f


For simplicity, assume that the terms with power of 4 or higher of (3.2.19) are

insignificant. Substituting (3.2.20) into (3.2.19) produces the following 3rd order

products.

)3cos4

13cos

4

1

)2cos(4

3)2cos(

4

3

)2cos(4

3)2cos(

4

3

2_31_3

1_1_32_1_3

1_1_32_1_3

twatwa

twwatwwa

twwatwwa

ii

iiii

iiii

⋅+⋅

++⋅++⋅

+−⋅+−⋅

(3.2.21)

The third to sixth terms are three times the in-band frequency. They can be easily filtered,

but the 1st and 2nd terms are the in-band products. Figure 32 shows that the 1st term falls

on the desired signal. This is the intermodulation distortion.

sssiidistrd ffffffff =∆⋅−−∆⋅+⋅=−⋅= 2222 2_1__3 (3.2.22)

If the desired signal is weak, the intermodulation distortion can corrupt the desired signal.

According to the specifications, the level of the interferers producing the intermodulation

distortion should be 60dB greater than the desired signal. This specification can be shown

to be the determinant of the cascaded input intercept point.

The receiver is considered to have the same amplification for the weak desired signal and

the strong interferers [18].

in

out

insig

outsig

P

P

P

P

int_

int_

_

_ ≈ (3.2.23)

Since

outIM

in

out PP

IIPP _32

int_

23

int_ ⋅= (3.2.24)


where

insigP _ : is the desired signal input power.

outsigP _ : is the desired signal output power.

inPint_ : is the interferer input power.

outontP _ : is the interferer output power.

outIMP _3 : is the output power of the 3rd-order intermodulation product.

3IIP : is the cascaded input intercept point.

From (3.2.23) and (3.2.24), we have

3int_

_2

3

_3

_

in

insig

outIM

outsign

P

PIIP

P

P ⋅= (3.2.25)

For the same output level of the desired signal and the intermodulation distortion

2int_

23

_

int_

ininsig

in

P

IIP

P

P= : is the intermodulation suppression. (3.2.26)

In logarithmic scale

insigdBdB

dBindB

dBinsig

indB

PIMIIP

PIIPP

PIM

__3

_int__3

__

int_

222

22

⋅−⋅−⋅=

⋅−⋅=

=

(3.2.27)

Therefore

insigdBdB PIMIIP __3 2

3 +⋅= (3.2.28)


The input power of the desired signal is defined from the minimum signal level

dBmIIP dB 23113602

3_3 −=−⋅=

The 3rd order input interception point of the cascaded system should be –23dBm at least.

Figure 33 shows the cascaded receiver chain of the radio.

Figure 33. Receiver chain of the radio.

The following equations can be used to evaluate cascaded systems [21].

Cascaded Gain: ∑=M

iisys GG in dB (3.2.29)

Cascaded Noise Figure

∏−

⋅−++−

+=1

1

21

1)1(.....

1 M

i iMsys g

nfg

nfnfnf in scale (3.2.30)

)log(10 syssys nfNF ⋅= in dB (3.2.31)

where

Mggg ,.....,, 21 : are the gain of individual blocks in scale.

DUP ATT BPF BPF

BPF

MIX 2

MIX 1 AMP 1 AMP 2

AMP 3 AMP 4

IF 1

IF 2

LNA RF


Cascaded Output Intercept Point

⋅⋅⋅⋅⋅⋅⋅

⋅−= ∑++

M

i Miiisys gggoip

OIP213

1log103 in dB (3.2.32)

Cascaded Input Intercept Point

syssyssys GOIPIIP −= 33 in dB (3.2.33)

The calculation can be performed with spreadsheet programs such as Excel. Table 9 is

the spreadsheet for the cascaded receiver chain of Figure 33. The device parameters of

each block are the gain, the noise figure and the 3rd order output interception point. They

can be found in the data sheets. 3rd order output interception points of passive filters are

large and are set to a hundred. The cascaded performances are 4.62dB for the noise

figure, 46.94dB for the overall gain and –19.35dBm for the 3rd-order input intercept

point. All of them meet to the design requirements.


Table 9. Cascaded receiver chain analysis.

Block Gain Noise Figure Output Intercept Point Noise Figure Gain Input Intercept Point

G, dB NF, dB OIP3, dBm NF, dB G, dB IIP3, dBmDUP -2 2 100 2.00 -2 102.00LNA 23.7 1.9 16 3.90 21.7 -5.70ATT -3.5 3.5 15 3.91 18.2 -7.64RF BPF -2.5 2.5 100 3.93 15.7 -7.64MIX 1 -5.88 5.88 5 4.06 9.82 -9.46AMP 1 20.2 4.3 32.5 4.35 30.02 -9.73IF 1 BPF -18 18 100 4.45 12.02 -9.73AMP 2 20.2 4.3 32.5 4.61 32.22 -10.15MIX 2 -4.78 4.78 11 4.62 27.44 -17.36AMP 3 14 5.2 33 4.62 41.44 -17.88IF 2 BPF -8.5 8.5 100 4.62 32.94 -17.88AMP 4 14 5.2 33 4.62 46.94 -19.35

DUP - Duplexer AMP 2 - Mini-Circuits ERA-5 AmplifierLNA - HP Low Noise Amplifier MIX 2 - Mini-Circuits TUF-3SM MixerATT - M/A COM RF Attenuator AT-108 AMP 3 - Mini-Circuits ERA-4 AmplifierRF BPF - Soshin RF Bandpass Filter IF 2 BPF - SAWTEK 70M SAW FilterMIX 1 - Mini-Circuits SCM-2500 Mixer AMP 4 - Mini-Circuits ERA-4 AmplifierAMP 1 - Mini-Circuits ERA-5 AmplifierIF 1 - NDK 190MHz SAW Filter

Cascaded System PerformanceDevice Parameters

DUP ATT BPF BPF

BPF

MIX 2

MIX 1 AMP 1 AMP 2

AMP 3 AMP 4

IF 1

IF 2

LNA RF

CascadedOutput


3.2.3.4 Automatic Gain Control (AGC)

The AGC dynamic range is specified to be 80dB. The entire 80dB range in one stage is

difficult to obtain without compromising noise figure and intermodulation sensitivity.

Equations (3.2.30) and (3.2.32) show that high gain at front-end devices gives good noise

figure but produces poor 3rd-order intercept point and vice versa. Therefore, the 80dB

control range of the AGC is broken into two parts. 40dB control is put on the front-end

and the other 40dB is on the back-end. The AGC tracks the input signal, as it is going up

from the minimum (-113dBm), with the 40dB control at the back-end. Therefore, the

front-end can provide high gain without noise figure degradation. After the back-end

AGC provides the 40dB control, the input signal is –73dBm. The system becomes

intermodulation limited rather than noise figure limited. Then the following 40dB control

at the front-end is activated. The front-end AGC keeps a constant stress level on the

front-end devices and maintains the intermodulation distortion level. Analysis was

performed to reveal the system performance with the intervention of the AGC. Figure 34

shows the results of the simulation.

Figure 34. Simulation of the system performance over the AGC tracking range.

Receiver In-Band Analysis

-20

-10

0

10

20

30

40

50

-120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20

Input Level (dBm)

IF Amp Gain Reduction (dB)

RF Attenuation (dB)

SNR (dB)

Output IMD Ratio (dBc)


The IF Amplifier Gain Reduction curve shows the increase of the attenuation from the

back-end AGC as the input signal increases from –113 to –73 dBm. The front-end AGC

(i.e. RF attenuation) takes over the gain control function from –73 to –33 dBm as shown

by the RF attenuation curve.

Since the AGC gain reduction is put at the back-end of the receiver for a –113 to –73

dBm the input level, the system noise figure can be maintained. The signal-to-noise ratio

(SNR) improves at the same rate as the input level as shown by the triangle curve.

However, the Output IMD Ratio curve shows the increase of the intermodulation product

as a result of increasing stress on the front-end devices. Further increase of the input level

from –73dBm activates the front-end AGC. The SNR levels off at approximately 37dB

and provides very good signal detection. After the attenuation is inserted at front-end, the

stress level to the front-end devices is kept constant and causes no more intermodulation

products.

It should be noted that the SNR is less than zero as the input range for –113 to –103 dBm.

This is a result of the bandwidth needed to pass the spread spectrum of the W-CDMA

system. As mentioned in Section 2.4 of the system overview, the bandwidth is 5MHz.

The radio processes signals before despreading and hence the RF bandwidth must be

5MHz. A larger bandwidth means that more noise is present in the radio. However, after

despreading done by the baseband processor, the noise bandwidth is restored back to

(1+0.22)*128K=156.16KHz and the SNR increases. The SNR improvement is equal to

the processing gain (PG) of the system. The PG is found to be 15dB in Section 2.3 of the

system overview. For instance, at –113dBm input level, the SNR of the signal from the

radio is –11dB as shown in Figure 34. After the despreading, the SNR of the signal is

restored to 4dB.


3.2.4 Circuit Level Design

Following the flow of the signal as shown in the block diagram in Section 3.2.1, the

discussion of this section proceeds from the duplexer to the digital interface. The detailed

schematics are in Appendix C-3, C-4 and C-5. The discussion of the circuits refers to the

schematics for the component designators. The hardware implementation of the receiver

comprises six assemblies. They are the duplexer, the receiver board, the demodulator

board, the analog-to-digital (ADC) board, the AGC driver and the AFC board. Each

assembly is discussed in following sub-section.

3.2.4.1 Duplexer – Receiver Part

This is the same duplexer mentioned in Section 3.1.4.5. The receiver part of the duplexer

with designator U10, is shown in the schematic in Appendix C-3. Since the transmitter

and the receiver share the same antenna for air interface, a physical path exists between

the transmitter and the receiver. The transmitter delivers a high-power signal to the

antenna. The high-power signal has to be isolated from the receiver very well; otherwise,

the high-power signal drives the receiver into saturation and blocks the access of the

desired small signal to the receiver. The duplexer is placed at the 1st stage of the receiver

chain to isolate the high-power transmit signal and to pass the desired small signal to the

receiver. It also provides part of the image rejection. It has 70dB rejection in the

transmitting band and just 1.8dB loss to the receiving band. The operating band of the

duplexer is 2110-2170MHz.

3.2.4.2 Receiver Board

The receiver board performs RF and IF signal processes such as amplification, down-

conversion and filtration. It receives the RF signal from the duplexer. It is a double down-

conversion reciver. The 1st stage converts the RF signal to a 190MHz 1st IF and the 2nd

stage converts the 1st IF to a 70MHz 2nd IF. It includes the 40dB front-end AGC.


Figure 35 is the block diagram of the receiver board. Its full schematic is shown in

Appendix C-3.

Figure 35. Block diagram of the receiver board.

Low Noise Amplifier (LNA)

The LNA should be high gain and low noise figure to compensate the tremendous

insertion loss of the 1st IF SAW filter which insertion loss is 18dB. The HP MGA-86576

LNA (Appendix C-3: U1) was chosen for its high gain (23.7dB) and low noise figure

(1.9dB). The recommended minimum 10Ω bias resistance (Appendix C-3: R10) is used

at +5Vdc supply. The bias current is 13mA. The inductor (Appendix C-3: L10) works as

an RF choke to isolate the DC supply line from high frequency signals. This is a 39nH

choke and provides approximately 500Ω reactance. It is 10 times 50Ω. To optimize the

noise figure or the sensitivity of the receiver, a small inductance 1.8nH (Appendix C-1:

L11) is placed in series with the LNA input.

ATTBPFBPF

BPF

MIX 2

AMP 2 AMP 1IF 1 MIX 1

AMP 3 AMP 4IF 2

LNA

LO 1

LO 2

RF

2110-2170MHz RF in

RF Stage1st IF Stage

2nd IF Stage

70MHz IF out


Front-End Attenuator

The front-end 40dB AGC is realized with an attenuator AT-108 (Appendix C-3: U2)

from M/A COM. Its attenuation is controlled with a DC voltage from 0 to 5V on the pin

5. A 5V voltage gives a minimum attenuation of 3.5dB that is the intrinsic insertion loss

of the attenuator. As the voltage increases, the attenuation increases until the total

attenuation is 43.5dB (i.e. 40dB AGC attenuation plus the 3.5dB insertion loss).

RF Bandpass Filter (BPF)

The post-LNA filter (Appendix C-3: U30) is a dielectric filter from Soshin. Rejecting

interferers solely by the duplexer demands a high selectivity filter design. The high

selectivity filter design is associated with a drawback of high insertion loss. Since the

duplexer is placed at the 1st stage of the receiver chain, its high insertion loss makes low

noise figure receiver impossible. Therefore, part of the interference rejection is done after

the LNA to allow low duplexer insertion loss for the sake of the receiver noise figure and

to compensate the insufficient interference rejection of the duplexer. The filter prevents

the transmitter power from saturating the mixer. This filter not only relaxes the duplexer

requirement but also suppress the noise at the received image frequency. It has 30dB out-

band rejection and 2.5dB in-band insertion loss.

Mixers

Mini-Circuits balanced diode mixers are used at the 1st and 2nd down-conversion stages.

The merits of these mixers are their predictable behavior, low harmonic generation, high

port-to-port isolation, and high intercept point. The shortcomings are the high conversion

loss and the need of high LO drives. Their shortcomings can be compensated easily by

using amplifiers. On the other hand, their merits are the primary concerns for the radio.


The 1st and 2nd down-conversion stages operate at different frequencies, leading to the use

of different mixers. SCM2500 is used at the 1st conversion (Appendix C-3: U3) and TUF-

3SM at the 2nd conversion (Appendix C-3: U7). However, the design approach is the

same for both.

The mixers are standard 50Ω devices. There is no special matching need for in-band

signals. However, attention has to be paid to terminate out-band signals properly. This is

done because out-band signals reflected back into the mixers can degrade the 3rd-order

performance. Diplexers are put at the outputs of the mixers to terminate out-band signals.

The diplexer is formed with a LC tuned circuit in series with a 50Ω resistor. The LC

circuit is tuned to the in-band frequencies. Therefore, to the in-band signals, the diplexer

looks like a high impedance device and has no interaction with the other circuits. To the

out-band signals, the diplexer looks like a 50Ω resistor that gives termination to the

signals and stops their reflection. The parts C30, L30, and R30 in the schematic in

Appendix C-3 form the diplexers to the 1st mixer, and the parts C70, L70, and R70 form

the diplexers to the 2nd mixers.

In addition to the diplexers, low pass filters (LPF) are put at the mixer outputs to remove

the unwanted mixing products. The LPFs are 3-order Butterworth type. The parts of the

LPF for the 1st mixer are L31, L32, and C31, while the parts of the LPF for the 2nd mixer

are L71, L72, and C71. They are shown in the schematic in the Appendix C-3. Figure 36

depicts the circuit realization of the diplexers and LPFs.


MIXER OUT

Ct Lt

Lf

Cf

Lf

DIPLEXER/LPF OUT

50

Figure 36. Circuit realization of the diplexer and LPF.

Figure 37 and 38 are the Eclipse simulations of the frequency response and return loss of

the diplexers and LPFs for the 1st and 2nd mixers respectively. The S21 curve shows the

low pass response due to the LPF. The S11 curve shows the wide band termination (i.e.

return loss > 10dB) due to the diplexer. Figure 37 and 38 show that the diplexers and

LPFs for both the mixers have similar characteristics except the passband frequencies.

Figure 37. Frequency Response and Return Loss of Diplexer and LPF for 1st Mixer.

Frequency Response & Return Loss of D iplexer and LPF for 1st M ixer

-45.00

-40.00

-35.00

-30.00

-25.00

-20.00

-15.00

-10.00

-5.00

0.00

100.00 200.00 300.00 400.00 500.00 600.00 700.00 800.00 900.00 1000.00

Frequency (M Hz)

S21 Frequency Response

S11 Return Loss


Figure 38. Frequency Response and Return Loss of Diplexer and LPF for 2nd Mixer.

IF Filters

The IF filters set the channel selectivity and remove the half-IF interferers as identified in

Section 3.2.3.2. NDK’s SAW filter was selected for the 190MHz 1st IF (Appendix C-3:

U5). It gives 45dB channel selectivity or interference rejection. The filter’s shortcoming

is its tremendous insertion loss of 18dB. This loss imposes a stringent requirement to the

LNA.

The 70MHz 2nd IF SAW filter (Appendix C-3: U9) is from SAWTEK. It gives another

50dB channel selectivity and interference rejection at the expense of 8.5dB insertion loss.

Hence, the total channel sensitivity is 95dB.

Frequency Response & Return Loss of Diplexer and LPF for 2nd Mixer

-70

-60

-50

-40

-30

-20

-10

0

0 100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

S21 Frequency Response

S11 Return Loss


To use these filters effectively, attention must be paid to the impedance matching and the

layout. Improper matching at the input and output ports of the filters causes serious

distortion of the passband characteristics of the filters. Improper layout produces too

much board feed-through and the out-band attenuation characteristics of the filters cannot

be predicted. The filters’ data sheets provide the topologies and values of the matching

components, as well as recommended layout patterns. It is important to point out that the

filters are not symmetrical with respect to required matching networks.

Amplifiers

As in the modulator board of the transmitter (Section 3.1.4.2), Mini-Circuits ERA

monolithic amplifiers are used as gain blocks in the receiver. Devices were chosen to

make the compromise between noise figure, gain and intermodulation sensitivity. Four

gain blocks are distributed along the chain according to the results from Section 3.2.3.3.

Two of them are ERA-5 (Appendix C-3: U4, U6) at the 190MHz 1st IF stage, which are

used for their high gain. The other two are ERA-4 (Appendix C-3: U8, U10) at the

70MHz 2nd IF stage where lesser gain is favorable.

The bias RF chokes were chosen such that their reactance is at least 500Ω. Based on this

criterion, a 1uH (Appendix C-3: L41, L60) choke was used for the ERA-5 and a 1.8uH

chokes (Appendix C-3: L82, L102) was used for ERA-4.

As mentioned in Section 3.1.4.2, the amplifiers should be biased with a supply voltage

higher than the device voltages for a low variation of the bias condition against

temperature. A 7V supply was chosen. The bias resistance is calculated with the equation

(3.1.9) shown in Section 3.1.4.2. The bias resistance for the ERA-5 is 32Ω. Two 16Ω

resistors are connected in series to produce the 32Ω resistance (Appendix C-3: R41, R42,

R60, R61). This approach allows the bias power to be shared between the two resistors

and to relax the power handling requirement of each resistor. The bias resistance for the


ERA-4 is 24Ω. Two 12Ω resistors are connected in series to produce the 24Ω resistance

(Appendix C-3: R82, R83, R102, R103).

3.2.4.3 Demodulator Board

The IF amplifier, back-end AGC, and demodulator are contained in a RF2667 device

from RF Micro Devices (RFMD). The RFMD evaluation board for the RF2667 was used.

The evaluation board contains all the required support circuitry. There are three devices

in the board. One is the RF2667. The other two are the wideband operational amplifiers

(CLC426-CL) from National Semiconductor. The amplifiers provides voltage gain to the

I and Q baseband outputs of the demodulator chip. Figure 39 is the block diagram of the

board.

Figure 39. Block diagram of the demodulator board.

The RF2667 chip demodulates the 70MHz IF signal for the baseband signals. It contains

an IF amplifier and an IQ demodulator. The IF amplifier is gain controllable. The IF

amplifier allows 100dB of gain control range by varying gain from -50 to 50dB. The

back-end AGC utilizes the control range of the amplifier from 10dB to 50dB. The gain is

controlled by voltage.

÷2

-45°

+45°

RFMD 2667

AGC AMPBB AMP17.7dB

BB AMP17.7dB

1Vpp

1Vpp


After the IF amplifier, there is the IQ demodulator where the baseband signal is

recovered from the IF signal. The LO signal injected into the demodulator has a

frequency of 140MHz. The LO signal is divided by two and split into two 70MHz LOs.

One is shifted by 45° and fed to the in-phase arm of the demodulator. The other one is

shifted by -45° and fed to the quadrature arm. The demodulator extracts the in-phase and

quadrature signals from the IF signal through the down-conversion process.

The demodulator outputs are amplified to 1Vpp by the baseband amplifiers. The 1Vpp is

the specified input range of the ADC. The gain of the baseband amplifiers in the

evaluation board was set to 17.7dB to produce the 1Vpp output.

3.2.4.4 ADC Board

The ADC board is the AD9059 evaluation board from Analog Devices. It performs the

analog-to-digital conversion for the digital format of the baseband signals to facilitate the

digital processing in the processor. The level of the baseband signals is kept at 1Vpp

through the AGC tracking. The 1Vpp level allows better utilization of the dynamic range

of the ADCs. The AD9059’s are capable of 60Msps but actually operate at 32.768Msps.

3.2.4.5 AGC Driver

There are two identical AGC drivers, one for each receiver. Both drivers are on one

board. Figure 40 is the block diagram one driver and the full schematic is shown in

Appendix C-4.

Figure 40. AGC driver block diagram.

BufferDAC

Front-EndDriver

Back-EndDriver

Analog Voltage Outputto Receiver Board

Analog Voltage Outputto Demodulator Board


The driver accepts a digital command from the baseband processor and provides a

corresponding analog voltage to drive the back-end and front-end attenuators. Since there

are two AGCs, the driver is designed to have two channels. As mentioned in Section

3.2.2, the gain control is 1dB per step and the range is 80dB. The digital command is

code is a binary number between 0000000B and 1010000B (or 0 to 80 in decimal). An

Analog Devices AD557 DAC (Appendix C-4: U1 or U3) is used as the interface between

the processor and the AGC driver. Based on the control characteristics of the ADC,

RFMD RF2667 and M/A COM AT-108, and the control sequence of from the back-end

AGC to the front-end AGC as signals going low to high, the driver has to map the

command code to the analog voltage according to Table 10.

Table 10. Mapping table of the command code to driver voltage

RF In (dBm) Command AD557 Out (V) RF2667 Drive (V) AT-108 Drive (V)

-113 0000000 0.01 2.5 5

-73 0101000 0.81 1.6 5

-33 1010000 1.61 1.6 0

The DAC is 8-bit device that has one bit more than the command digits. In order to fully

utilize the output range of the DAC, the command digits are tied to the most significant

7-bits of the DAC and the least significant bit is held high. Thus, the command is

effectively multiplied by a factor of 2 and the output voltage of the DAC is from 0.01 to

1.61V. The 10mV residual voltage is a result of the least significant bit being tied high.

An operation amplifier (Appendix C-2: U7A or U7B) configured as the voltage follower

is placed at the DAC output.

The back-end AGC of the RF2667 is activated in the region of low input levels. The

relationship between the command code and the gain is inversely proportional. This

means that a low command value causes a high gain. This driver has two stages to realize

the mapping shown in Table 10. The 1st stage is a non-inverted amplifier (Appendix C-4:


U2B or U4B) that drives the 2nd stage and a diode limiter. The diode (Appendix C-4: D1

or D2) is used to limit the output of the 1st stage. The 2nd stage is an inverted amplifier

(Appendix C-4: U5A or U5B) to produce the phase inversion and the level shifting. The

back-end driver voltage is limited at 1.6V as the DAC output goes higher than 0.8V

because of the diode limiter. A variable resistor (Appendix C-4: R29 or R30) is used to

facilitate the level shifting adjustment because of the high gain-to-voltage sensitivity of

RF2667 (i.e. 40dB/0.9V=44.4dB/V).

The front-end AGC by AT-108 is activated as the DAC output goes higher than 0.8V.

This driver provides phase inversion as well. However, the design of this driver is

relatively simple because there is no limiting voltage. A single inverting amplifier

(Appendix C-2: U2 or U4) is sufficient. There is no level shifting adjustment required

because the gain-to-voltage sensitivity of AT-108 is small (i.e. 40dB/5V=8dB/V).

However, using the operational amplifier for 5V output swing with a 5V supply demands

rail-to-rail amplifiers. A National Semiconductor LM6132 was selected. Figure 41 is the

PSPICE simulation of the drivers. The driver characteristics match Table 10 very well.

The drivers have very linear characteristics over their control regions. The 1.6V limited

voltage of the back-end AGC driver is well defined.

Figure 41. AGC driver characteristics.

DAC AD557 Output Voltage (V)

AGC Driver Characteristic

Back-end

Front-end

Dri

ver

Out

put V

olta

ge (

V)


3.2.4.6 AFC Board

The AFC board includes the transmit power control (TPC) that has been described in

Section 3.1.4.3. It provides the local oscillators (LO) for the 70MHz IF demodulation.

The baseband processor commands the AFC board through DAC devices to adjust the

oscillation frequency. Figure 42 is the block diagram of the AFC board and the full

schematic is shown in Appendix C-5.

VCTCXO - Voltage Controllable Temperature

Compensated Crystal Oscillator

BPF - Bandpass Filter

AMP - Amplifier

Figure 42. AFC block diagram.

The dual receiver architecture requires two 140MHz LOs, one for the main and one for

the diversity receiver. However, in contrast to the VGC drivers, it is not necessary to have

independent LOs because the signals intercepted by the diversity antenna may be

different in amplitude and phase but not frequency. Thus, the AFC just has one signal

generation circuit. At the final stage, the generated signal is split into two LOs with a

Mini-Circuits splitter (Appendix C-5: U9).

A voltage controllable temperature compensated crystal oscillator (VCTCXO) (Appendix

C-5: U12) with high tuning linearity from Oscillatek is the tuning element in the AFC.

The VCTCXO not only serves the AFC but also provides the reference frequency to the

synthesizer. Therefore, the frequency tuning affects the transmit frequency and the

receiver LO frequencies produced by the synthesizer. The normal oscillation frequency of

DAC AFCDriver

VCTCXOx14

Multiplier BPF

Split

ter

AMP

to MainReceiver

to DiversityReceiver

To Synthesizer


the VCTCXO is 10MHz. In order to get 140MHz, the 10MHz signal is fed to the

inverters. The inverters operate as non-linear amplifiers (Appendix C-5: U3) and generate

the harmonics. A high frequency selective TOKO filter (Appendix C-5, U8) removes the

harmonics except the 140MHz signal. Since the filter is a 50Ω device, three inverters are

connected in parallel to lower their output impedance or to increase the driving

capability. Finally the 140MHz signal is amplified and split. The amplifier (Appendix C-

5: U4) is the Mini-Circuits ERA-1 monolithic amplifier. The splitter (Appendix C-5: U9)

is the Mini-Circuits LRPS-2-1 1-to-2 splitter.

An Analog Devices AD557 DAC (Appendix C-5: U1) is the interface between the AFC

board and the processor. The command code from the process is 7 bits long. The bits are

tied to the most seven significant bits of the DAC. The least significant bit of the DAC is

held high. Effectively the command code is multiply by a factor of 2. A two-stage

amplifier (Appendix C-5: U2A,B) processes the DAC output for the tuning voltage to the

VCTCXO. The VCTCXO has a measured ±10ppm frequency deviation at 2.5V ±1.5V.

The tuning range required by the system is ±2ppm over the command range 0~127 (or

0~1111111B). This 2ppm tuning effect applies to all the output frequencies – the transmit

signal, the 1st and 2nd LOs, and the 140MHz LO for the demodulation. Thus the amplifier

maps the DAC output to a narrower tuning voltage as shown in Table 11.

Table 11. Mapping table of the digital command to tuning voltage.

Command AD557 Out (V) Tuning Voltage

0000000 0 2.2

0111111 1.26 2.5

1111111 2.54 2.8

Radio Design – Synthesizer 78

3.3 Synthesizer

The synthesizer provides the local oscillators (LO) used in the radio. There are two LO

synthesizers. One of the synthesizers produces the LO frequency at the transmitting band

(1920-1980MHz). It is the RF synthesizer. The output of this synthesizer is split into

three outputs, one for the transmitter modulator and the other two outputs are the first LO

for each receiver. The other synthesizer produces an LO frequency at 260MHz. Its output

is split for the 2nd down-conversion of the two receivers.

The synthesizer consists of three units: the synthesizer board, the splitter board and the

10MHz voltage controllable temperature compensated crystal oscillator (VCTCXO). The

VCTCXO is on the AFC board. The VCTCXO supplies the reference frequency for the

synthesizer.

The synthesizer is a modified Harris HFA3524 evaluation board. The synthesizer board

contains a Harris HFA3524 dual phase-lock-loop (PLL) chip. It provides the

simultaneous radio frequency (RF) and intermediate frequency (IF) LO generation.

The splitter board splits and distributes the outputs of the synthesizer board to different

parts of the radio. Figure 43 is the block diagram of the synthesizer.


3.3.1 Block Diagram

VCO - Voltage Controllable OscillatorLPF - Low Pass FilterAMP - AmplifierATT - Attenuator

Figure 43. Synthesizer block diagram.

VCTCXO

÷R

PhaseComparator Loop Filter VCO

÷NR

ATT

Split

ter

Split

ter

ATT

ATT


÷NI

LPF ATT

Split

ter

ATT

to Transmitter

to MainReceiver

to MainReceiver



Splitter Board RF

IF

RFSynthesizer Board

IF

divider

divider

divider

AMP

AMP

AMP

ATT



The RF synthesizer is programmed for the transmitting frequencies from 1922.5 to

1977.5 MHz in 5MHz increments. The IF synthesizer provides a fixed frequency LO at

260MHz. The requirements for the two synthesizers are different but the design approach

and the PLL architecture for each are the same. The discussion of the PLL architecture is

based on the RF synthesizer; however the discussion is applicable to the IF synthesizer as

well. The differences will be noted.

The 10MHz VCTCXO output is divided by four to obtain a 2.5MHz reference frequency

for the RF and IF synthesizers. The frequency accuracy of the synthesizer outputs is

equal to the accuracy of the VCTCXO output. The VCTCXO has a trim adjustment to

facilitate the frequency setting. The frequency accuracy is set within ±1ppm to comply

with the specifications. It also has an electronic adjustment for the AFC. The AFC may

tune the VCTCXO ±2ppm from the nominal frequency. Therefore, the RF and IF

synthesizer outputs can accommodate a ±2ppm frequency drift.

The splitter board amplifies and splits the LOs from the synthesizer board. The LO power

level for the transmitter is –1dBm. This level is within the specified LO drive level of the

RF2242 modulator device. The 1st LO power level for the SCM-2500 mixers of the

receivers is 7dBm. The 2nd LO power level for the TUF-3SM mixers is 10dBm.

3.3.3 Synthesizer Board

3.3.3.1 Design Modifications

The component designators used in the discussion of this section refer to the schematic

shown on the Harris application note AN9630 [22].


RF Synthesizer Modification

The RF synthesizer was originally designed for the 2132-2204 MHz frequency band [22].

The RF VCO was replaced with Zcomm SMV1960L for the desired operational band

(1920-1980 MHz). The output attenuation pad was changed from -8dB to -2dB for 8dBm

output power. Figure 44 shows the block diagram of the RF synthesizer and indicates the

modified parts.

Figure 44. RF synthesizer block diagram and the modifications.

IF Synthesizer Modification

The IF oscillator, which is built on board, was modified from the original 560MHz

oscillation frequency to the desired 260MHz. The oscillator is a common collector

Colpitts oscillator. Figure 45 shows the oscillator with the frequency determining

components.

VCTCXO ÷RPhase

Comparator Loop Filter VCO

÷NR

ATT

divider

Modified partsRF Synthesizer 1920-1980 MHz8dBm


L

Loop Filter, Vt

L1

Cv Ca

C2

C1 Re

Figure 45. Frequency determining components of the Colpitts oscillator.

The oscillation frequency is determined by the circuit inductance (L) and capacitance (C).

CLfo ⋅⋅

=π2

1(3.3.1)

where

)()2(

121

avo CCfLL

+⋅⋅−=

π(3.3.2)

21

21

CC

CCC

+⋅

= (3.3.3)

vC is the capacitance developed by the varactor diode. It changes the capacitance, vC ,

based on the bias voltage from the loop filter. Thus, the oscillation frequency changes

until the PLL locks to the target frequency of 260MHz. aC provides a fine tune to the

oscillator. 1C and 2C form a capacitive voltage divider to derive a feedback from the

output to the base-emitter junction of the transistor. A closed oscillation loop is

established. 1C and 2C are in series to give the circuit capacitance.


Evaluating (3.3.3) with pFCC 1521 == results in pFC 5.7= .

Evaluating (3.3.1) with pFC 5.7= and MHzfo 260= results in nHL 50= .

Referring to the data sheet of the varactor, vC is estimated to be 20pF.

Evaluating (3.3.2) with nHL 50= , pFCv 20= , pFCa 7.4= and MHzfo 260= results

in nHL 651 = . A standard value, 68nH was chosen for 1L .

Additionally, the RF (L2) choke for the oscillator was changed from 12nH to 680nH to

give better isolation to the power supply.

The IF oscillator is followed with a three-section, π-Butterworth low pass filter (LPF). It

is used to suppress the harmonic output from the oscillator. It was modified for the cutoff

at 350MHz. Figure 46 shows the block diagram of the IF synthesizer and indicates the

modified parts.

Figure 46. IF synthesizer block diagram and the modifications.

Miscellaneous Changes

In order to unify the power supplies for the radio, the supply voltage of the synthesizer

board is 5V which is different from the original 3V design. This change requires the


÷NI

LPF ATT

divider

VCTCXO ÷R

260 MHz7dBm

Modified partsIF Synthesizer


change of the PLL control signal levels (LE, Clock and Data). The resistors of RA23,

RA24, and RA25 were changed from 10KΩ to 5.1Ω to obtain the level shift.

The chosen VCTCXO is transistor-transistor-logic (TTL) compatible output. Therefore,

the 50Ω termination (RREF ) at the reference input of the synthesizer board was removed.

As a summary, Table 12 lists all the changes of the components on the synthesizer board

that were made to comply with the requirements of the radio.

Table 12. Component changes on the Harris synthesizer board.

Part Designator Was Is Change for

VCO Z-Comm

SMV2100L

Z-Comm

SMV1960L

RF Synthesizer

L1 12 nH 68 nH IF Synthesizer

L2 12 nH 680 nH IF Synthesizer

LF1 12 nH 39 nH IF Synthesizer

CF1 5.6 pF 8 pF IF Synthesizer

CF2 5.6 pF 8 pF IF Synthesizer

RA4 20 Ω 5.5 Ω RF Synthesizer

RA5 20 Ω 5.5 Ω RF Synthesizer

RA6 51 Ω 220 Ω RF Synthesizer

RA21 10 KΩ 5.1 KΩ 5V Supply



RREF 50 Ω Nil VCTCXO TTL Output


3.3.3.2 Loop Filter

The loop filter is the most important part of the PLL design. It is the part available for

designers to optimize the PLL performance, as the other parts are off-the-shelf

components.

The loop filter was designed to obtain a 25KHz loop bandwidth and the 45° phase

margin. The 25KHz loop bandwidth is a hundredth of the 2.5MHz loop reference. This

provides good suppression of the reference and eliminates the modulation sidebands. The

radio stays on the channel over the course of a conversation. Therefore, the lock in time

of the loop is not a critical requirement. The stability of the loop becomes the design

criterion. The phase margin of the loop provides the stability and was chosen to be 45°.

The loop was chosen to be type-2, 4th-order. The required loop filter is shown in Figure

47.

From Charge Pump - I

C0

R1

R2

C2

To VCO - V

C1

Figure 47. The realization of the loop filter.

The transfer function for the loop filter is given by

))([

1)(

2102112122021012102122

11

CCCCCRCCRCCRCCRsCCCRRss

CsRsK f +++++++

+=

(3.3.4)


The detailed design procedure of a PLL can be found in [23]. Figure 48 and 49 are the

simulated gain and phase response of the loop respectively.

Figure 48. Gain response of the type-2, 4th-order loop.

Figure 49. Phase response of the type-2, 4th-order loop.

102

103

104

105

106

107

-100

-80

-60

-40

-20

0

20

40

60

80

100Loop Gain Response Comparison

Frequency in Hz

Mag

nitu

de o

f G(s

)H(s

) in

dB

Loop Bandwidth≈30KHz

2.5MHz ReferenceSuppression> 80dB

102

103

104

105

-180

-175

-170

-165

-160

-155

-150

-145

-140Loop Phase Response Comparison

Frequency in Hz

Pha

se o

f G(s

)H(s

) in

Deg

ree

Phase Margin≈38°


The simulation is based on the loop response for the middle channel (1952.5MHz). The

choice of the channel affects the N-divider values of the PLL. The divider values to

program the PLL is given in Appendix E. The use of the standard component values

produces the performance deviation between the target and simulation. The deviation is

small and is not a problem. No potential instability of the loop was experienced in the

laboratory evaluation.

3.3.4 Splitter Board

The splitter board has the RF and IF channels, and supplies the LOs at specified power

levels and provides adequate reverse isolation. The full schematic is in Appendix C-6.

3.3.4.1 RF Channel

Figure 50 is the block diagram of the RF channel.

Figure 50. RF channel block diagram.

As shown in Figure 50, the RF synthesizer output level is 7dBm. The RF2422 modulator

requires an LO power between –3 and 3dBm. The splitter is designed to deliver -1dBm

to the transmitter. The splitter supplies the LOs at 7dBm to the receiver 1st mixer.

The first two stages of the channel are a 20dB attenuator (Appendix C-6: R350-352) and

a 20dB gain block (Appendix C-6: U35). They provide a reverse isolation between the

synthesizer and the modulator. Without the buffer, the modulation process in the

Split

ter

Split

ter

ATT

ATT

to Transmitter

to MainReceiver


RF

AMP

AMP

ATT

from the RFSynthesizer

-20dB 20dB -4dB

-4dB

-4dB

12dB -4dB

-1dBm

7dBm

7dBm

7dBm


modulator caused a disturbance at the VCO output of the RF synthesizer. The loop will

not compensate for any disturbance outside the loop bandwidth. The modulation

sidebands of the disturbance developed at the synthesizer output. Since the receivers

share the same synthesizer output, these sidebands became a noise source to the

receivers. The attenuator and the gain block provide a total of 43dB reverse isolation. The

ERA-3SM was selected for its small reverse transmission (S12= –23dB).

Mini-Circuits LRPS-2-25 splitters were selected. One-to-two splitting causes the output

to be 3dB lower than the input. The splitter has 1dB insertion loss. Therefore, the total

signal attenuation of the splitter is 4dB. A splitter (Appendix C-6: U30) divides the RF

signal into two outputs. One output is attenuated by 4dB (Appendix C-6: R300-302) and

supplied to the transmitter modulator as shown in the upper chain of Figure 50. The

power level of this output is –1dBm. The other output is further divided by a splitter

(Appendix C-6, U32) into two to supply the two receivers as shown in the lower chain of

Figure 50. A Mini-Circuits ERA-1SM amplifier (Appendix C-6: U33) compensates the

loss due to the attenuator (Appendix C-6: R310-312) and the splitters so that the output

power of the two outputs is 7dBm.

3.3.4.2 IF Channel

The IF channel provides one-to-two splitting for the IF synthesizer output. This channel

has 2dB gain so that the IF LOs are 10dBm. Figure 51 is the block diagram of the IF

channel.

Figure 51. IF channel block diagram.

Split

ter

ATT

to MainReceiver

to DiversityReceiverAMP

from the IFSynthesizer

8dBm

10dBm

10dBm-6dB -4dB12dB


The splitter (Appenidx C-6: U33) is different from the splitter used in the RF channel

because the IF frequency is much lower than the RF frequency. The splitter is Mini-

Circuits LRPS-2-1. The splitter causes 4dB signal attenuation. The resistive attenuator

(Appendix C-6: R330-331) is a 6dB pad and the same ERA-1SM amplifier (Appendix C-

6, U33) is used as the gain block. The total gain of the channel is 2dB; therefore, an

8dBm input produces a 10dBm output.

Radio Performance 90

4. Radio Performance

This chapter presents the performance of the radio.

4.1 Transmitter

4.1.1 Transmit Power

W-CDMA test signals were not available. Therefore, the transmit power is measured on

the continuous-wave (CW) output. The QPSK modulation is equivalent a single-sideband

generator, if the direct (I) and quadrature (Q) signals are the same but the I signal leads

the Q signal by 90°. A modulation generator was built as shown in Figure 52 for

generating the test carrier. The generator produces two TTL compatible square waves.

The square waves are 90° out-of-phase. The frequency of the square waves is 1.25MHz

which is inside the passband of the baseband filters.

I20MHz CLK

1 2

74HCT04

10K

3 4

74HCT04

+5V

D 12 Q 9

CLK 11

Q 8

PR

10

CL

13

74HCT74

+5V

D 2 Q 5

CLK 3

Q 6

PR

4

CL

174HCT74

+5V

D 12 Q 9

CLK 11

Q 8

PR

10

CL

13

74HCT74

+5V

D 2 Q 5

CLK 3

Q 6

PR

4

CL

174HCT74

Q

1.25MHz

+5V+5V

+5V+5V

33pF

20MHz

33pF

Figure 52. Modulation generator.

The square waves are fed to the DAC board of the transmitter. The phase-lead square

wave is applied to the I channel DAC. All the input pins of the DAC are tied together.

This provides the codes between 00000000B and 11111111B to the DAC. The output of

the DAC is a 0.5V square wave. The baseband filter removes the harmonics of the DAC

output and provides a 1.25MHz tone signal. Similarly, a 1.25MHz tone, which is 90°

phase lag, is generated on the Q channel.


The two tones are fed to the transmitter modulator to generate the single-sideband CW

output. The CW output is 1.25MHz away the modulator LO as shown in Figure 53. After

the power amplification, the CW output can be measured for the transmit power. Figure

54 shows the measurement setup.

Figure 53. Single-sideband generation.

Figure 54. Transmit power test setup.

The computer is used to load the commands to the synthesizer for setting the channel of

the radio. The test is conducted on the middle channel. The TPC code generator provides

the command code to set the transmit power level. The modulation generator provides the

signals for the single-sideband generation. The spectrum analyzer measures the

transmitter output.

DAC LPF

DAC LPF

+45°

-45°

Local fromSynthesizer90°

fo

1.25MHz

1.25MHz

fo fo + 1.25MHz

ModulationGenerator

Transmitter

ComputerTPC

Code Generator

SpectrumAnalyzer


Measurement Procedure:

1. Set the transmitter to operate on the middle channel (i.e. 1952.5MHz).

2. Set the TPC command code for 0 (i.e. 0000000B binary).

3. Adjust the variable resistor (Appendix C-5: R18) in the AFC board for the

maximum transmit power, approximately 32dBm.

4. Set the TPC command code for 70 (i.e. 1000110B binary).

5. Adjust the variable resistor (Appendix C-5: R19) in the AFC board for the 70dB

transmit power attenuation.

6. Repeat the procedure 2 to 5 until the maximum transmit power and the 70dB

transmit power attenuation are simultaneously obtained.

7. Measure the single-sideband output with the spectrum analyzer for the transmit

power.

Figure 55 shows the output spectrum of the transmitter.

Figure 55. Transmitter output power spectrum.

The output power meets the specification of 1.6W +20% -50%. This is the measured data

of the single-stage power amplifier design. This design can provide sufficient transmit

power but fails the adjacent channel power specification.

fo +1.25MHz +2.5MHz +3.75MHz-1.25MHz-2.5MHz

fo = 1952.5MHz

31.85dBm = 1.53W

-26dBc

-34dBc

-25dBc

-31.5dBc

-57dBc


Figure 56 shows the test setup for the adjacent channel power measurement. Figure 57 is

the measured spectrum of the QPSK modulated transmit signal.

Figure 56. Adjacent channel power test setup.

Figure 57. The measured spectrum of the QPSK modulated transmit signal.

The signal generator is HP4433B. The generator is an RF signal generator but it also

provides the analog I and Q filtered baseband signals at its back panel. The symbol rate

was 4.096Msps and the 0.22 roll-off square root raised cosine pulse shaping was applied

on the symbols. Since the baseband signals were in analog form, the signals were fed to

Spectrum of QPSK ModulatedTransmit Signal

-60

-50

-40

-30

-20

-10

0

-12.5 -7.5 -2.5 2.5 7.5 12.5

Offset Frequency (MHz) from 1952.5MHz (Middle Channel)

I modulation

Q modulation

Signal Generator Transmitter SpectrumAnalyzer

ComputerTPC

Code Generator

5MHz

-25dBc


the transmitter modulator instead of the digital interface. The modulator output was set to

–2dBm to minimize the adjacent channel power generated by the single-stage power

amplifier. The modulator output less than –2dBm could not deliver the required transmit

power. However, the adjacent channel power was –25dBc as shown in Figure 57. The

adjacent channel power is higher the specification of –40dBc.

A two-stage power amplifier design is being considered to improve the adjacent channel

power suppression as mention in Section 3.1.4.4. The design improvement is in progress.

The test data is not available at the time of this writing.

4.1.2 Transmit Power Control (TPC)

The test setup in Figure 54 is applicable to this measurement.


1. Set the transmitter to operate on the middle channel (i.e. 1952.5MHz).

2. Set the TPC command code for 0 (i.e. 0000000B binary) for the maximum transmit

power.

3. Record the transmitter output power and the power control voltage.

4. Increase the TPC command code by 10.

5. Repeat the procedure 3 to 4 until the command code is 70 (i.e. 1000110B binary).

Figure 58 is the measurement results.


Figure 58. Transmit power control characteristic.

The transmit power control voltage curve (Pcont) shows that the transmit power control

voltage responds to the command code linearly, while the transmit power curve (Tx Pwr)

shows that the transmit output power responds to the command code non-linearly. The

transmit power behaves non-linearly because of the non-linear attenuation-to-voltage

characteristic of the AT-108 attenuators. However, the transmit output power has a

monotonic decrease characteristic. The objective of the power control can be performed.

Also, the control range meets the 70dB specification.

Transmit Power Control (TPC) Characteristics

-50

-40

-30

-20

-10

0

10

20

30

40

0 10 20 30 40 50 60 70

Command Code (0-70)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Tx Pwr (dBm)

Pcont (V)


4.2 Receiver

4.2.1 Receiver Noise figure

Without the W-CDMA base station, it is not possible to do a direct measurement of

sensitivity. Therefore, the minimum detectable signal (MDS) is measured to estimate the

noise figure of the receiver. The MDS is an RF input level at the receiver so that the

receiver analog output is equal to the noise output. The noise figure can be approximately

estimated by

)(log10)(174)()( dBBdBmdBmMDSdBNF ⋅−+= (4.1)

where

B : is the channel bandwidth of 5MHz.

174 dBm : is the thermal noise power.

Compare the estimated noise figure to the desired noise figure of 5.4dB (Section 3.2.3.1)

for a confidence of the receiver sensitivity. The measurement setup is shown in Figure

59.

RMS – Root Mean Square

Figure 59. Receiver sensitivity test setup.

The computer is used to set the channel of the radio. The test is conducted on the middle

channel. The AGC code generator provides the command code to set the receiver gain.

SignalGenerator

Receiver

ComputerAGC

Code Generator

RMSVoltmeter

analog outputI or Q


The signal generator provides the RF test signal. The receiver output is the I or Q analog

signal from the receiver. The root-mean-square (RMS) voltmeter measures the receiver

output.


1. Set the receiver to operate on the middle channel (i.e. 2142.5MHz).

2. Set the AGC command code for 80 (i.e. 1010000B binary) for the minimum receiver

gain.

3. Set the output frequency of the signal generator for 2142.6MHz and the output level

for -33dBm. Offset the frequency of the signal generator by 100KHz to produce a

100KHz tone at the I and Q analog outputs for measurement.

4. Measure the I (or Q) analog output with the RMS voltmeter. Adjust the variable

resistor (Appendix C-4: R29 or R30) in the AGC board for 350mVrms (or 1Vpp)

analog output.

5. Set the RF level of the signal generator for –113dBm and turn off the RF output.

6. Set the AGC command code for 0 (i.e. 0000000B binary) for the maximum receiver

gain.

7. Measure the I (or Q) analog output with the RMS voltmeter. It measures the noise

level in the receiver.

8. Turn on the RF output of the signal generator.

9. Increase the RF level of the signal generator until the RMS reading increases by 3dB.

The 3dB increase means that the power of the receiver output is equal to the noise

power. The RF output level of the signal generator is equal to the MDS of the

receiver.

The measured MDS is approximately –102dBm and gives 5dB noise figure.

4.2.2 AGC Performance

The test setup in Figure 59 is applicable to this measurement.


Measurement Procedure


2. Set the AGC command code for 80 (i.e. 1010000B) for the minimum receiver gain.

3. Set the output frequency of the signal generator for 2142.6MHz and the output level

for -33dBm. Offset the frequency of the signal generator by 100KHz to produce a

100KHz tone at the I and Q analog outputs for measurement.

4. Measure the I (or Q) analog output with the RMS voltmeter. Adjust the variable

resistor (Appendix C-4: R29 or R30) in the AGC board for 350mVrms (or 1Vpp)

analog output.

5. Increase the AGC command code by 5.

6. Reduce the output level of the signal generator to restore the analog output level of

procedure 4.

7. Record the output level of the signal generator, and the voltages of the front-end and

back-end AGC drivers.

8. Repeat the procedure 5 to 7 until the I analog output is too noisy to measure. It is

likely at the command code of 5 (i.e. 0000101B binary).

Figure 60. AGC performance.

Receiver AGC Characteristic

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 10 20 30 40 50 60 70 80

AGC Command Code in decimal (0-80)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

RF Input

Front-end AGC

Back-end AGC


The curves of the front-end AGC driver voltage (Front-end AGC) and the back-end AGC

driver voltage (Back-end AGC) show that the performance of the AGC drivers matches

the PSPICE simulation result shown in Figure 41.

The receiver RF input power curve (RF Input) shows that the back-end AGC of the

receiver responds to the command code linearly but the front-end AGC behaves non-

linearly. The back-end AGC operates at the 70MHz IF frequency, while the front-end

AGC operates at the 2142.5MHz RF frequency. The device linearity is better at the low

frequency than at the high frequency. The analog output becomes too noisy to measure as

the RF input level is less than –100dBm. However, interpolating the curve for the RF

input power level at the zero AGC command code shows that the level is –113dBm and

meets the design target of 80dB control range.

4.2.3 Receiver Desense

The receiver desense is measured based on the minimum detectable signal (MDS)

degradation. The setup in Figure 59 is applicable to the this measurement. The MDS of

the receiver, when the transmitter is turned off, is measured to be -102dBm. The

transmitter is turned on and the MDS measurement is repeated. The difference of the

MDS readings is the receiver desense. The measurement shows no observable receiver

desense.

4.2.4 Adjacent Channel Selectivity

The adjacent channel selectivity is measured based on the MDS comparison. The setup in

Figure 59 is applicable to this measurement.


1. Set the output frequency of the signal generator for 2147.5MHz (5MHz or 1

channel away the middle channel).


2. Turn on the transmitter of the radio.



gain.

5. Turn off the RF output of the signal generator.




8. Increase the RF output level until the measured level of the RMS voltmeter

increases by 3dB.

Compare the RF output level of the signal generator to the MDS of the receiver measured

in Section 4.2.1. The difference of the readings is the adjacent channel selectivity. The

measured adjacent channel selectivity is 70dB and meets the above 33dB specification.

The measured 70dB adjacent channel selectivity is less than the predicted 95dB

selectivity. The discrepancy is due to the board feed-through.

4.2.5 Intermodulation Selectivity

The intermodulation selectivity is measured based on the MDS comparison. Two signal

generators and a power combiner are required to generate the intermodulation products.

The measurement setup is shown in Figure 61.

Figure 61. Intermodulation selectivity test setup.

SignalGenerator

Receiver

ComputerAGC

Code Generator

RMSVoltmeter

analog output

I or Q

SignalGenerator

PowerCombiner

10dBPAD



1. Set the output frequency of one signal generator for 2152.5MHz (10MHz or 2

channels away the middle channel) and the output frequency of the second signal

generator for 2162.5MHz (20MHz or 4 channels away the middle channel).

2. Turn on the transmitter of the radio. The 10dB pad between the radio and the signal

generator prevents too much transmit power from getting into the signal generator.



gain.

5. Turn off the RF output of the signal generator.




8. Increase the RF output levels of the two signal generators and keep the generators at

the same output levels. Increase the generator level until the measured level of the

RMS voltmeter increases by 3dB.

Compare the RF output levels of the generators to the MDS of the receiver measured in

Section 4.2.1. The difference of the readings is the intermodulation selectivity. The

measured intermodulation selectivity is 62dB and meets the above 60dB specification.


4.2.6 AFC Characteristic

This measures the frequency error of the AFC output verse the AFC command code (1-

127). The nominal frequency of the AFC is 140MHz. The AFC provides a ±2.2ppm

control range as shown in Figure 62. This is close to the ±2ppm specification.

Figure 62. The AFC characteristic.

Automatic Frequency Control (AFC) Characteristic

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

0 20 40 60 80 100 120 140

AFC Command Code in decimal (0-127)

Conclusions 103

5. Conclusions

5.1 Summary

A radio that complies with the radio specifications of the W-CDMA system was built.

The design methodology and hardware implementation of the radio has been presented.

The radio meets all the specifications except the adjacent channel power. The linear

QPSK modulation and the zero guard band of the W-CDMA system imposed a stringent

adjacent channel power specification on the transmitter design. The use of the single-

stage power amplifier failed to meet this stringent specification. An peak-to-average

factor simulation was performed. Based on the simulated peak-to-average factor, the

analysis suggested a two-stage power amplifier design.

The traditional receiver design technique was found applicable to this radio. The W-

CDMA test signals are not available in the laboratory. Therefore, the direct sensitivity

measurement could not be conducted. However, using MDS to estimate the receiver

performance provided a level of confidence that the receiver would perform well in the

field. The TPC did not behave linearly. However, the objective of the 70dB power control

range was achieved. The two stage AGC design successfully maintained the noise figure

and the intermodulation sensitivity of the receiver. The smooth and linear transition

between the back-end and the front-end AGCs was obtained and the 80dB control range

was achieved. The use of a diode for voltage limiting performed well. The AFC provided

the required ±2ppm tuning range.

The approach of this radio design is to study the system requirements up front and then to

translate the system requirements into circuit level requirements. This design process was

successful. Only two iterations of the hardware implementation were needed before

meeting all the specifications except for the adjacent channel power. The sophisticated

and expensive W-CDMA test equipment was not available. Therefore, some indirect

Conclusions 104

performance measurement techniques were introduced. These techniques successfully

indicated the radio performance.

5.2 Recommendations

The problem of insufficient adjacent channel power suppression needs to be addressed.

The proposed two-stage power amplifier approach needs to be verified.

The power amplifier is class A for high linearity and remains the bias condition regardless

the output power level. The drawback of this scheme is inefficient. For mobile terminals,

power amplifier efficiency is important for the battery life.

However, power amplifiers optimized for efficiency at maximum output power do not

effectively increase battery life in W-CDMA systems. Due to the power control, the

average output power is much less than the maximum power [24]. A suggestion for

future research is the design of power amplifiers that can maximized the amplifier

efficiency over the entire transmit power range. For the W-CDMA radio, the transmit

power range is from –40dBm to 30dBm.

Radio Specifications 105

Appendix A: Radio Specifications

Mobile Receiver

Parameter Requirement Comments

Spreading Method Direct Sequence

Radio Access Interface CDMA FDD

Frequency Range 2112.5 – 2167.5 MHz

Modulation (Down Link) Data QPSK

Spreading QPSK

AFC Function 0.015 ppm per step

Receiver Sensitivity -113 dBm (conductive) Static BER = 10-3

Diversity Two Rx Antennas Switch Diversity

Spurious Response 60dB or more at 10MHzfrom Fo

CW test signal at Psens+3dB

Adjacent ChannelSelectivity

33dB or more at 5MHz fromFo

CW test signal

Receiver IntermodulationSensitivity

60dB or more Psens +3dB at 10 and20MHz from Fo

AGC >80dB Dynamic Range

Traffic Channel Eb/No 6dB or less Under selective fadingwithout power controlAverage BER = 10-3

Control Channel Eb/No 6dB or less Under selective fadingwithout power controlAverage Frame Error Rate= 2x10-2

High Data Rate Eb/No 6dB or less Under selective fadingwithout power control,200ms or less delay,Average BER = 10-6

Input Impedance Nominally 50Ω

Radio Specifications 106

Mobile Transmitter

Parameter Requirement Comments

Radio Interface Direct SequenceCDMA FDD

Frequency Range 1922.5 – 1977.5 MHz

Modulation (Up Link) Data QPSKSpreading QPSK

Modulation BandwidthLimit

Root-Nyquist Roll-off(R=0.22)

99% within 4.096MHz

Maximum AverageTransmit Power andInformation Bit Rate

Type II 1.6W 128 kbps Control Range:+20%, -50%

Frequency Stability Within ± 1.0 ppmWithin ± 1.0 ppm

Absolute accuracyRelative to base stationpilot, using AFC at receiver

Transmission ON/OFFRatio

With voice activity 25 dBWith carrier on/off 70 dB

Power Control Range 70 dB

Power Control Step Size + or –1 dB Toggled by digital signal

Modulation Accuracy 12.5% or less Error Vector Magnitude

Adjacent Channel Leakage -40dBc in 5MHz band-60dBc in 5MHz band

5 MHz from Fo10MHz from Fo

Transmitter Intermodulation -60dBc or less External CW interferer

Spurious Emissions -60dBc or less All spurs

Output Impedance Nominally 50Ω

Block Diagram 107

Appendix B: Block Diagram

Not shown diversity receiver is identical.

DAC LPF

DAC LPF

DAC

ATT BPF

PC

ATTBPFBPF

BPF

ADC LPF

ADC LPF

÷2

-45°

DAC AGC

+45°

AFC

RF2667

VCO

VCO

Synthesizer

260M

1.9G

TUF-3SM ERA-5 ERA-5190M SCM-2500

ERA-4 ERA-470M

2.1G

RF2422

ERA-1 1.9G

PA2

DUPLEXER

LNA

SPLITTER

140M

Main Receiver

Transmitter

DAC

To diversityreceiver

ATT+45°

-45°PA1

Schematics 108

Appendix C-1: DAC Board

C71u

R6

510DVCC

AVCC

CLK 28 AVDD

24

DVDD

27

REFLO 16

REFIO 17

IOUTA 22

IOUTB 21

FSADJ 18

COMP2

23

COMP1

19

SLEEP 15

DB7 1

DB6 2

DB5 3

DB4 4

DB3 5

DB2 6

DB1 7

DB0 8

ACOM

20

DCOM

26

U1AD9708

C3

.01u

R727

R4

240 3

2 1

8

4

U2AAD8072

C8.01u

R8

51

-V

4 1

2 3

F1

SOSHIN LPF

R951

R10

240

R11

510

I

C9

.1u

5

6 7

U2BAD8072

AVCCR3

240

R5510

C61u C5

.01u

R12K

C420p

R227

1937183617351634153314321331123011291028 927 826 725 624 523 422 321 220 1

J1

DB37

C2.01u

C1

.01u

AVCC

R16

510

+12V

VI GND

VO

U5LM78L05

C201u

DVCC

C21.1u

-12V

VI GND

VO

U7LM79L05

-V

C25.1u

C241u

AVCC

C23.1u

-V

VI GND

VO

U6LM78L05

C221u

C171u

C18.01u

R1727

AVCC

DVCC

CLK 28 AVDD

24

DVDD

27

REFLO 16

REFIO 17

IOUTA 22

IOUTB 21

FSADJ 18

COMP2

23

COMP1

19

SLEEP 15

DB7 1

DB6 2

DB5 3

DB4 4

DB3 5

DB2 6

DB1 7

DB0 8

ACOM

20

DCOM

26

U3AD9708

C13.01u

C1420p

R14

240 3

2 1

8

4 U4AAD8072 R18

51

4 1

2 3

F2

SOSHIN LPF

R1915

R21

240

R22

510

5

6 7

U4BAD8072

Q

C19

.1u

AVCCR13

240

R15510

C161u

C15.01u

R122K

R2027

C12.01u

C11

.01u

AVCC

Schematics 109

Appendix C-2: Modulator Board

+5V

R142.2K

C7100p

C70.01u

+5V

R218

R310

C20.01u

C21470p

L139n

+6V +5V

R110

C4

100p C40.01u

to PA

R72300

U7R70

18

R71300

3

1268

5

4

7

U1AT-108

C2

100p

C5

100p

C1

100p

U3

ERA-5R13*

R16*

R11

0

3

1268

5

4

7

U2AT-108

C131u

C14.01u

C3100p

R610K

R710K

R1510K

I

R510K

R410K

Q

LO

GND

3

GND

4

GND

5

GND

10

GND

12

GND

13

GND

14

RFOUT 9

VCC2 11

VCC1 7

PD 8

ISIG 16

QSIG 15

IREF 1

QREF 2

LO 6

U4RF2422

C90.01u VCC

R1210

C9100p

R910

C6100p

R810

C8100p

+5V

VI GND

VO

U5LM78L05

VCR90

10

VCCR13

10 C60470p

C10100p

C100.01u

C16.01u

C121uF

C111uF

C17.01u

+12V

C1510u

VI GND

VO

U6LM78L06 +6V

Schematics 110

Appendix C-3: Receiver Board

+5V

L1039n

C2021u

Id=50uAVd=5V

VIGND

VO

U20LM78L05

+7V

C201.1u

3

1 2 6 8

5

4

7

U2AT-108

C24.01u C25

47p

Vd=5VId=13mA meas

C13.01u

C1447p

R1010

Ant

U10

2140M

Off-board Duplexer

C10

47p

CN1 L11

1.8n

U1

MGA86576

C21

47p

-10.49dBm^

R20100

C22

47p

C2347p

On-board for the Soshin BPF

Off-board for Dr. Sweeney’s BPF

Front End Out

U30

-15.24dBm^

-13.3dBm^

Vgc2

12

CN8

HEADER 2

-33dBm^

External Connections: Signals x2 - Vgc2

GND

C60470pR61

16

R60

16

+7V

C44.01u

C63470p

C43470p

R4216

R41

16

190M IF

U3SCM2500

L31

39n

C40470pL32

39n

U4

ERA-5SM

Vd=4.9VId=65mA

L411u U5

190M

C51

12p

C52

3p

C61

470p

U6

ERA-5SM

Vd=4.9VId=65mA L60

1u U7TUF-3SM

70M

C70

33p

L70150n

^R7050

2nd LO

CN5

^

-3.95dBmL5127n

L5268n

-22.9dBm^

-3.2dBm

C3118p

-23.61dBm^

L3039nC30

18p

^-15.24dBm

1st LO

CN4

+7V

R3050

R83

12

R82

12

+7VR102

12

R103

12

RF2667

C101

.01u

Vd=5V

CN6

Id=78mA measL1021.8u

C100

.01u

U10

ERA-4SM

C104.01u C105

.01u

U9

70M

L91

150n

C81

.01u

L90

180n

Vd=5VId=78mA meas

U8

ERA-4SM

C80

.01u

C85.01u

L821.8u

L72

120n

C84.01u

70M

L71

120n

Off-board Parts

C7147p -10.3dBm

^

Is=410mAExternal Connections:

3.67dBm^ -4.8dBm

^ 8.77dBm^

To RF2667

1st LO IN

2nd LO IN

+7V

C214.01u

SMA Coax x3 -

R211R

C21310u

Pd=2W

C2121000p

VI GND

VO

U21LM317

+12V

C211.1u

12

CN20

R212R

Power x2 - +12Vdc x1

Power GND x1

Schematics 111

Appendix C-4: VGC Driver Board

R2,19

110K

3

2 1

8

4U2,4A

LM6132

R1,22

680K

12

CN31

HEADER 2

Vgc3,4 AT-108

R3,12 10K

R4,233.9K

C2,4.1u R5,13

0 5

6 7

U7A,BLM6132

R8,1615K

R6,20

10K

R7,21

9.1K

R25,26

12K

Vgc1,2 RF2667

12

CN32

HEADER 2R29,30

5K

5

6 7

U5A,B

LM6132D1,21N4148R27,28

10K

R10,11

10K

5

6 7

U2,4B

LM6132

R9,17

10K

+5V

B8 1

B7 2

B6 3

B5 4

B4 5

B3 6

B2 7

B1 8

VO 16

VO_A 15

VO_B 14

GND 13

GND 12

VCC 11

/CS 10

/CE 9

U1,3

AD557

R14,24

12

U3,P4

U3,P5

U3,P6U3,P7

U3,P8

NC

1325122411231022 921 820 719 618 517 416 315 214 1

J5

CONNECTOR DB25

U1,P8

+12Vdc

U3,P1

U3,P2

U3,P3GND

GND

GND

GND

GND

U1-J5,P15;U3-J5,P8U1-J5,P14;U3-J5,P9U1-J5,P1;U3-J5,P10U1-J5,P2;U3-J5,P11U1-J5,P3;U3-J5,P12U1-J5,p4;U3-J5,P13U1-J5,P5;U3-J5,P25U1-J5,P6;U3-J5,P24

C3,6no part

R15,18

0

+5V

C7.1u

+12VdcVIGND

VO

U6LM78L05

+5V

C61u

C61.01uU1,P3

U1,P4

U1,P5

U1,P6

U1,P7GND

GND

U1,P1

U1,P2

Non-used parts because they are difficult to place on the layout.

added part

Schematics 112

Appendix C-5: AFC Board

R9

4.7K

R5

20KR8

100K

R2

100K

5

6 7U2BLM6132

1325122411231022 921 820 719 618 517 416 315 214 1

J2

DB25 F

B8 1

B7 2

B6 3

B5 4

B4 5

B3 6

B2 7

B1 8

VO 16

VO_A 15

VO_B 14

GND 13

GND 12

VCC 11

/CS 10

/CE 9

U1

AD557C1.1u

R130K

R620K

R7

30K

+5VD

+5VD

3

2 1

8

4

U2ALM6132

R430K

+5VAC15.1u

C171U

G

4

VC 3 VO 2VCC

1

U12

10M VCTCXO

C7

.01u

11

10U3E

13

12

U3FR185K R15

8.2KR14

2.4K

+10V

3

2 1

8

4

U10ALM6132

B8 1

B7 2

B6 3

B5 4

B4 5

B3 6

B2 7

B1 8

VO 16

VO_A 15

VO_B 14

GND 13

GND 12

VCC 11

/CS 10

/CE 9

U5

AD557

+5VD

5V

-12V

C13.1u

+5VD

+10V R17

30K

5

6 7

U10BLM6132

Vc

Tx Power Control

Synthesizer

U3 P7

U3 P14

C8.1u

+5VA

R162K

R195K

+5VD

VI GND

VO

U6LM78L05

+12V

VI GND

VO

U13LM78L05

+5VA

L12.2u

R13

150C12.01u

+10V

3 4

U3B

5 6

U3C

9 8

U3D

74HC04

1 2

U3AR12

51

C9

.01u

C10

.01u

U8140M

C11

.01u

U4ERA-1SM

U9

LRPS-2-1

CN1

CN2

+10V

Rx1

VI GND

VO

U7LM78L10

C141u

Rx2

Toyo 272MT-1008A

Schematics 113

Appendix C-6: Splitter Board

+7V

R353

180

C35247p

R354180

L35056nH

stacking assembly

~38mAR301220

R300

24R302220 R314 120

stacking assembly

CN31

-1.5dBm

CN32

7dBmC320

47p

U32

LRPS-2-25

U31ERA-1SM

C31147p

~55mA

L31056nH

~3.7V

*

R313

120

+7V

C310

47p

C312.01u

4dB PAD

R310

24

U30

LRPS-2-25

C351

47p

C350

47p

R35262

U35ERA-3SM

~4.8VCN30

1950MR350

240

R35162

20dB PAD

R311220

4dB PAD

R312220

CN33

7dBm

~55mA

R334 120

R333

120

stacking assembly

+7VSupplier - the 7V off-board LM317 Regulator

120MCN34

R331150

R330

36R332150

C331

470p

C333.01u

U33ERA-1SM

C340

470p

C332470p

L3301uH

~3.7V

U34

LRPS-2-1

CN35

CN36

10dBm

10dBm

6dB PAD

* Non-used decoupling parts because power traces are short on the layout.

Spurious Analysis 114

Appendix D-1: Spurious Analysis Part 1 – Middle Channel

Input Spurious, Select LO, Tune Input, Input Filter

System Input/Output Parameters

Output Frequency = DifferenceInput Start Frequency 997.5 MHzInput Stop Frequency 3002.5 MHzLO Frequency Selected 1952.5 MHzMaximum Spur Table Level 65 dB

Input Butterworth BPF with Fixed Bandwidth

Number of Sections 7Filter Center Frequency 2142.5 MHzFilter Bandwidth Frequency 60 MHzFilter Corner Attenuation 0.1 dBFilter Maximum Attenuation 110 dB

Spurious Data

Input Output Input Output Mixer Mixer Mixer InputFreq. Freq. Spur Spur Spur Spur Table Filter

Freq. Level Atten. Atten.MHz MHz MHz (dB) MxSPUR NxLO (dB) (dB)

2142.5 190. 1071.25 263. 2 -1 43 110.2142.5 190. 1762.5 110. -1 1 0 110.2142.5 190. 1857.5 269. -2 2 49 110.2142.5 190. 1889.167 377. -3 3 47 110.2142.5 190. 2015.833 266.4 3 -3 47 73.12142.5 190. 2047.5 159.3 2 -2 49 55.22142.5 190. 2142.5 0 1 -1 0 02142.5 190. 2540. 394. -3 4 64 110.2142.5 190. 2666.67 394. 3 -4 64 110.2142.5 190. 2833.75 261. -2 3 41 110.


Appendix D-2: Spurious Analysis Part 2 – Middle Channel






Spurious Data



1622.5 330. 1141.25 263. 2 -1 43 110.1622.5 330. 1622.5 110. -1 1 0 110.1622.5 330. 1787.5 269. -2 2 49 110.1622.5 330. 1842.5 377. -3 3 47 110.1622.5 330. 2062.5 180.4 3 -3 47 44.51622.5 330. 2117.5 49. 2 -2 49 .1622.5 330. 2282.5 75.4 1 -1 0 75.41622.5 330. 2493.333 394. -3 4 64 110.1622.5 330. 2713.333 394. 3 -4 64 110.1622.5 330. 2763.75 261. -2 3 41 110.


Appendix D-3: Spurious Analysis Part 3 - Middle Channel



Output Frequency = DifferenceInput Start Frequency 100 MHzInput Stop Frequency 400 MHzLO Frequency Selected 260 MHzMaximum Spur Table Level 65 dB


Number of Sections 7Filter Center Frequency 190 MHzFilter Bandwidth Frequency 4.6 MHzFilter Corner Attenuation 1 dBFilter Maximum Attenuation 40 dB

Spurious Data



190 70. 110. 166. 3 -1 46 40.190 70. 150. 169. -3 2 49 40.190 70. 165. 134. 2 -1 54 40.190 70. 177.5 221. -4 3 61 40.190 70. 190. 0 -1 1 0 0190 70. 196.667 169. 3 -2 49 40.190 70. 212.5 221. 4 -3 61 40.190 70. 236.667 169. -3 3 49 40.190 70. 246. 259. -5 5 59 40.190 70. 274. 259. 5 -5 59 40.190 70. 283.333 169. 3 -3 49 40.190 70. 298. 264. -5 6 64 40.190 70. 307.5 224. -4 5 64 40.190 70. 323.333 174. -3 4 54 40.190 70. 326. 264. 5 -6 64 40.190 70. 330. 40. 1 -1 0 40.190 70. 342.5 224. 4 -5 64 40.190 70. 350. 255. -5 7 55 40.


Appendix D-4: Spurious Analysis Part 1 - Bottom Channel






Spurious Data



2112.5 190. 1056.25 263. 2 -1 43 110.2112.5 190. 1732.5 110. -1 1 0 110.2112.5 190. 1827.5 269. -2 2 49 110.2112.5 190. 1859.167 377. -3 3 47 110.2112.5 190. 1985.833 306.6 3 -3 47 86.52112.5 190. 2017.5 193.6 2 -2 49 72.32112.5 190. 2112.5 .1 1 -1 0 .12112.5 190. 2500. 394. -3 4 64 110.2112.5 190. 2626.667 394. 3 -4 64 110.2112.5 190. 2788.75 261. -2 3 41 110.2112.5 190. 2978.75 261. 2 3 41 110.


Appendix D-5: Spurious Analysis Part 2 – Bottom Channel






Spurious Data



1592.5 330. 1126.25 263. 2 -1 43 110.1592.5 330. 1592.5 110. -1 1 0 110.1592.5 330. 1757.5 269. -2 2 49 110.1592.5 330. 1812.5 377. -3 3 47 110.1592.5 330. 2032.5 239.9 3 -3 47 64.31592.5 330. 2087.5 91.7 2 -2 49 21.41592.5 330. 2252.5 61.2 1 -1 0 61.21592.5 330. 2453.333 394. -3 4 64 110.1592.5 330. 2673.333 394. 3 -4 64 110.1592.5 330. 2718.75 261. -2 3 41 110.


Appendix D-6: Spurious Analysis Part 1 – Top Channel






Spurious Data



2167.5 190. 1083.75 263. 2 -1 43 110.2167.5 190. 1787.5 110. -1 1 0 110.2167.5 190. 1882.5 269. -2 2 49 110.2167.5 190. 1914.167 377. -3 3 47 110.2167.5 190. 2040.833 225.1 3 -3 47 59.42167.5 190. 2072.5 121.4 2 -2 49 36.22167.5 190. 2167.5 . 1 -1 0 .2167.5 190. 2573.333 394. -3 4 64 110.2167.5 190. 2700. 394. 3 -4 64 110.2167.5 190. 2871.25 261. -2 3 41 110.


Appendix D-7: Spurious Analysis Part 2 – Top Channel






Spurious Data



2307.5 330. 1153.75 263. 2 -1 43 110.2307.5 330. 1647.5 110. -1 1 0 110.2307.5 330. 1812.5 269. -2 2 49 110.2307.5 330. 1867.5 377. -3 3 47 110.2307.5 330. 2087.5 111.1 3 -3 47 21.42307.5 330. 2142.5 49. 2 -2 49 02307.5 330. 2307.5 85.1 1 -1 0 85.12307.5 330. 2526.667 394. -3 4 64 110.2307.5 330. 2746.667 394. 3 -4 64 110.2307.5 330. 2801.25 261. -2 3 41 110.

PLL Programming Information 121

Appendix E: PLL Programming Information

The Harris PLL chip provides the following possible divider values.

Dual Modulus Prescaler P: 32/33 or 64/65 (RF) 8/9 or 16/17 (IF)

7-Bit Swallow Divider A: 0 ~ 127 (RF) 0 ~ 15 (IF)

11-Bit Program Divider B: 3 ~ 2047

RF Synthesizer

To operate the RF synthesizer for the transmitting band (1922.5-1977.5MHz), the change

of the divider values is on the swallow divider. All the other dividers are kept no change.

Table E-1 lists all the divider values to the channels.

Table E-1. Divider values to the RF synthesizer. Note that the least significant bit is

on left rather than on right as usual.

NDividers R A B PDecimal 4 * 24 32

LSB Control R Divider Prog Mode MSB

C1 C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20RF R dvdr 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0

Control N Divider ProgMode

A Divider B DividerC1 C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 * A (MHz)

RF N dvdr 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1922.51 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 3 1927.51 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 5 1932.51 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 7 1937.51 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 9 1942.51 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 11 1947.51 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 13 1952.51 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 15 1957.51 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 17 1962.51 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 19 1967.51 1 1 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 21 1972.51 1 1 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 23 1977.5


RF R-Divider

The first two bits identify which dividers to be programmed. Here they are ‘01’ for the

RF R-divider. Then the bits 1 to 15 form the divider value that always is 4 to the radio.

The final five bits are the program modes and they are:

Description ‘0’ ‘1’ Set

Bit 16 RF Phase Detector Polarity -ve +ve 1

17 RF ICPO – Charge Pump Current low high 0

18 RF Detector O/P State normal high Z 0

19 RF Lock Detect no yes 1

20 RF FO Out no yes 0

RF N-Divider

Again, the first two bits identify the selected divider and they are ‘11’. The bits 1 to 7 are

the A-swallow divider value. Its value is changed based on the wanted frequency and the

used values are listed in Table E-1. Then the bits 8 to 18 form the B-divider value and it

always is 24. The last two bits select the prescaler P-counter value (32 or 64) and power

mode (up or down). Set the bit 19 to ‘0’ for P-counter=32 and the bit 20 to ‘0’ for power

up.


260MHz IF Synthesizer

This is a fix frequency synthesis. All of divider values are fixed for the wanted frequency

of 260MHz. The IF synthesizer needs to program once as long as it is powered on. Table

E-2 lists the divider values.

Table E-2. Divider values to the IF synthesizer. The least significant bit is on left.

N Dividers R A B P decimal 4 0 13 8

LSB Control R Divider Prog Mode MSB

C1 C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IF R dvdr 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 Control N Divider Prog

Mode

A Divider B Divider C1 C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IF N dvdr 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0

IF R-Counter

The first two bits identify which dividers to be programmed. Here they are ‘00’ for the IF

R-counter. Then the bits 1 to 15 form the divider value that always is 4 to the radio. The

final five bits are the program modes and they are:

Description ‘0’ ‘1’ Set

Bit 16 IF Phase Detector Polarity -ve +ve 1

17 IF ICPO – Charge Pump Current low high 0

18 IF Detector O/P State normal high Z 0

19 IF Lock Detect no yes 1

20 IF FO Out no yes 0


IF N-Counter

Similarly, the first two bits identify the divider to be selected. In this case, they are ‘10’.

The bits 1 to 7 are the A-swallow divider value. It always is 0 for 260MHz. Then the bits

8 to 18 form the B-counter value and it always is 13. The last two bits select the prescaler

P-divider value (8 or 16) and power mode (up or down). Set the bit 19 to ‘0’ for P-

counter=8 and the bit 20 to ‘0’ for power up.

Remark:

- The divider values are stored individually. Changing the value of one divider does not

affect the values of the other dividers.

- In practice, program the R-counter and then the N-counter in a program cycle.

- The divider values will stay as long as Vcc is supplied. However, refreshing them in

every program cycle is valid.

- Send the data to the synthesizer with the MSB at first and a timing diagram is shown

Figure E-1.

Data

Clock

LE

or

LE

MSB

#20 #19 #10 #9 #1 Control bit:LSB

LSB

Figure E-1. Timing diagram of loading divider values

References 125

References

[1] Michael H. Callendar, “International Mobile Telecommunications – 2000Standard Efforts of the ITU,” IEEE Personal Communications, vol. 4, no. 4, pp.6-7, August 1997.

[2] Akio Sasaki, Masami Yabusaki and Syuichi Inada, “The Current Situation ofIMT-2000 Standardization Activities in Japan,” IEEE Communications Magazine,vol. 36, no. 9, pp. 145-153, September 1998.

[3] Fumiyuki Adachi, Mamoru Sawahashi and Hirohito Suda, “Wideband DS-CDMAfor Next Generation Mobile Communications Systems,” IEEE CommunicationsMagazine, vol. 36, no. 9, pp. 56-69, September 1998.

[4] Stephen McClelland and Bhawani Shankar, “Mobilizing the Third Generation,”Telecommunications (Americas Edition), vol. 31, no. 11, pp. 50-52,54, November1997.

[5] Fabio Leite, Richard Engelman, Shunsuke Kodama, Horst Mennenga and SabahTowaij, “Regulatory Considerations Relating to IMT-2000,” IEEE PersonalCommunications, vol. 4, no. 4, pp. 14-19, August 1997.

[6] Atsushi Fukasawa, Takuro Sato, Yumi Takizawa, Toshio Kato, Manabu Kawabeand Reed E. Fisher, “Wideband CDMA System for Personal RadioCommunications,” IEEE Communications Magazine, vol. 34, no. 10, pp. 116-123, October 1996.

[7] Erik Dahlman, Bjorn Gudmundson, Mats Nilsson and Johan Skold, “UMTS/IMT-2000 Based on Wideband CDMA,” IEEE Communications Magazine, vol. 36, no.9, pp. 70-80, September 1998.

[8] Fumiyuki Adachi and Mamoru Sawahashi, “Wideband Multi-rate DS-CDMAMobile Radio Access,” 1997 Asia Pacific Microwave Conference Proceedings,vol. 1 of 3, pp. 149-152, December 2-5, 1997.

[9] Esmael H. Dinan and Bijan Jabbari, “Spreading Codes for Direct SequenceCDMA and Wideband CDMA Cellular Networks,” IEEE CommunicationsMagazine, vol. 36, no. 9, pp. 48-54, September 1998.

[10] Japan’s Revised Proposal for Candidate Radio Transmission Technology on IMT-2000: W-CDMA, Revised Proposal (ver. 1.1), Association of Radio Industriesand Business (ARIB) IMT-2000 Study Committee, September 1998.

[11] Raymond A. Birgenheier, “Overview of Code-Domain Power, Timing, and PhaseMeasurements,” Hewlett-Packard Journal, vol. 47, no. 1, pp. 73-93, February1996.

References 126

[12] Theodore S. Rappaport, Wireless Communications Principles and Practice,Prentice-Hall PTR, New Jersey, 1996.

[13] Victor Fung, “Bit Error Simulation of FSK, BPSK, and π/4 DQPSK in Flat andFrequency-Selective Fading Mobile Radio Channels using Two-Ray andMeasurement-Based Impulse Response Models”, Master Thesis in ElectricalEngineering, Virginia Tech., August 1991.

[14] John G. Proakis, Digital Communications, WCB/McGraw-Hill, 1995.

[15] Biasing ERA Amplifiers, Mini-Circuits Application Note AN-60-010, September18, 1998.

[16] The ARRL Handbook for Radio Amateurs, 26th Edition, American Radio RelayLeague, Connecticut, 1992.

[17] Bernard Sklar, Digital Communications Fundamentals and Applications,Prentice-Hall PTR, New Jersey, 1988.

[18] Behzad Razavi, RF Microelectronics, Prentice-Hall PTR, New Jersey, 1998.

[19] Robert R. Kyle, Spurious and Filter Analysis, Artech House Inc., 1996.

[20] William E. Sabin and Edgar O. Schoenike, editors, Single-Sideband Systems andCircuits, McGraw-Hill, 1987.

[21] Charles W. Bostian, “EE4606 Radio Engineering Lecture Notes”, Spring 1998.

[22] Tim Bozych, “Using the HFA3524 Evaluation Board,” Harris Application NoteAN9630, November 1996.

[23] William F. Egan, Phase Lock Basics, Wiley, 1998.

[24] John F. Sevic, "Statistical Characterization of RF Power Amplifier Efficiency forCDMA Wireless Communication Systems," Proceedings of 1997 WirelessCommunications Conference, pp. 110-113, August 1997.

Vita 127

Vita

Cheung, Tze Chiu was born in Hong Kong, on July 3, 1966. He received his Higher

Diploma in Electronic Engineering from the Hong Kong Polytechnic in June 1987. After

his graduation, he worked as a Product Engineer in Video Technology Engineering

Limited. In January 1989, he was transferred to Technophone Manufacturing Limited, a

joint-venture company between Video Technology Engineering Limited and

Technophone, as a Senior Test Engineer. In 1992, he joined Wong’s Electronics

Company, Limited as a Senior RF Engineer, where he worked on the design and

development of cordless and analog cellular phones.

In March 1995, he moved to America and resided in Brooklyn, New York. He pursued

his undergraduate degree in Polytechnic University and received his Bachelor of Science

degree in Electrical Engineering in June 1997. From 1996 to 1997, he worked in

Newtronix Communications, Inc. as a part-time engineer. He came to Virginia Tech in

the fall of 1997 for his master study in Electrical Engineering. In January 1998, he joined

the Center for Wireless Telecommunications at Virginia Tech, where he worked on the

2GHz W-CDMA radio transceiver as his master thesis topic.

2 ghz w-cdma radio transceiver

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