19-3842; rev 0; 10/05 evaluation kit available dual ... · pdf filegeneral description the...
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General DescriptionThe MAX12558 is a dual, 3.3V, 14-bit analog-to-digitalconverter (ADC) featuring fully differential widebandtrack-and-hold (T/H) inputs, driving internal quantizers.The MAX12558 is optimized for low power, small size,and high dynamic performance in intermediate frequen-cy (IF) and baseband sampling applications. This dualADC operates from a single 3.3V supply, consumingonly 756mW while delivering a typical 71.7dB signal-to-noise ratio (SNR) performance at a 175MHz input fre-quency. The T/H input stages accept single-ended ordifferential inputs up to 400MHz. In addition to low oper-ating power, the MAX12558 features a 330µW power-down mode to conserve power during idle periods.A flexible reference structure allows the MAX12558 touse the internal 2.048V bandgap reference or acceptan externally applied reference and allows the refer-ence to be shared between the two ADCs. The refer-ence structure allows the full-scale analog input rangeto be adjusted from ±0.35V to ±1.15V. The MAX12558provides a common-mode reference to simplify designand reduce external component count in differentialanalog input circuits.The MAX12558 supports either a single-ended or differ-ential input clock. User-selectable divide-by-two (DIV2)and divide-by-four (DIV4) modes allow for design flexibil-ity and help to reduce the negative effects of clock jitter.Wide variations in the clock duty cycle are compensatedwith the ADC’s internal duty-cycle equalizer (DCE).The MAX12558 features two parallel, 14-bit-wide,CMOS-compatible outputs. The digital output format ispin-selectable to be either two’s complement or Graycode. A separate power-supply input for the digital out-puts accepts a 1.7V to 3.6V voltage for flexible interfac-ing with various logic levels. The MAX12558 is availablein a 10mm x 10mm x 0.8mm, 68-pin thin QFN packagewith exposed paddle (EP), and is specified for theextended (-40°C to +85°C) temperature range.For a 12-bit, pin-compatible version of this ADC, refer tothe MAX12528 data sheet. See the Selector Guide formore selections.
ApplicationsIF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,MMDS, HFC, WLAN
I/Q Receivers
Ultrasound and Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
Features♦ Direct IF Sampling Up to 400MHz♦ Excellent Dynamic Performance
74.4dB/71.7dB SNR at fIN = 70MHz/175MHz84.2dBc/79dBc SFDR at fIN = 70MHz/175MHz
♦ 3.3V Low-Power Operation789mW (Differential Clock Mode)756mW (Single-Ended Clock Mode)
♦ Fully Differential or Single-Ended Analog Input♦ Adjustable Differential Analog Input Voltage ♦ 750MHz Input Bandwidth♦ Adjustable, Internal or External, Shared Reference ♦ Differential or Single-Ended Clock♦ Accepts 25% to 75% Clock Duty Cycle♦ User-Selectable DIV2 and DIV4 Clock Modes♦ Power-Down Mode♦ CMOS Outputs in Two’s Complement or Gray
Code♦ Out-of-Range and Data-Valid Indicators♦ Small, 68-Pin Thin QFN Package
(10mm x 10mm x 0.8mm)♦ 12-Bit, Pin-Compatible Version Available
(MAX12528)♦ Evaluation Kit Available (Order MAX12558EVKIT)
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Dual, 80Msps, 14-Bit, IF/Baseband ADC
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3842; Rev 0; 10/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGEPKG
CODE
MAX12558ETK -40°C to +85°C 68 Thin QFN-EP* T6800-2
MAX12558ETK+ -40°C to +85°C 68 Thin QFN-EP* T6800-2*EP = Exposed paddle.+Denotes lead-free package.
**Future product—contact factory for availability.
PARTSAMPLING RATE
(Msps)RESOLUTION
(Bits)
MAX12559** 95 14
MAX12558 80 14
MAX12557 65 14
MAX12529** 95 12
MAX12528 80 12
MAX12527 65 12
Selector Guide
Pin Configuration appears at end of data sheet.
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2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA =-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND ................................................................-0.3V to +3.6VOVDD to GND............-0.3V to the lower of (VDD + 0.3V) and +3.6VINAP, INAN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6VINBP, INBN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6VCLKP, CLKN to
GND........................-0.3V to the lower of (VDD + 0.3V) and +3.6VREFIN, REFOUT
to GND ..................-0.3V to the lower of (VDD + 0.3V) and +3.6VREFAP, REFAN,
COMA to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6VREFBP, REFBN,
COMB to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V
DIFFCLK/SECLK, G/T, PD, SHREF, DIV2, DIV4 to GND .........-0.3V to the lower of (VDD + 0.3V) and +3.6V
D0A–D13A, D0B–D13B, DAV, DORA, DORB to GND..............................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)68-Pin Thin QFN, 10mm x 10mm x 0.8mm (derate 70mW/°C above +70°C) ....................................4000mW
Operating Temperature Range................................-40°C to +85°CJunction Temperature...........................................................+150°CStorage Temperature Range .................................-65°C to +150°CLead Temperature (soldering 10s).......................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 14 Bits
Integral Nonlinearity INL fIN = 3MHz ±1.4 LSB
Differential Nonlinearity DNLfIN = 3MHz, no missing codes overtemperature (Note 2)
-1.0 ±0.6 +1.2 LSB
Offset Error ±0.1 ±0.7 %FSR
Gain Error External reference, VREFIN = 2.048V ±0.1 ±4.6 %FSR
ANALOG INPUT (INAP, INAN, INBP, INBN)
Differential Input Voltage Range VDIFF Differential or single-ended inputs ±1.024 V
Common-Mode Input Voltage VDD / 2 V
Analog Input Resistance RIN Each input, Figure 3 2.8 kΩ
CPARFixed capacitance to ground,each input, Figure 3
2
Analog Input Capacitance
CSAMPLESwitched capacitance,each input, Figure 3
4.5
pF
CONVERSION RATE
Maximum Clock Frequency fCLK 80 MHz
Minimum Clock Frequency 5 MHz
Data Latency Figure 5 8ClockCycles
DYNAMIC CHARACTERISTICS
Small-Signal Noise Floor SSNF Input at -35dBFS 75.4 76.8 dBFS
fIN = 3MHz 72.7 75.2
fIN = 40MHz 74.7
fIN = 70MHz 74.4Signal-to-Noise Ratio SNR
fIN = 175MHz 69.9 71.7
dB
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ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA =-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fIN = 3MHz 71.1 74.8
fIN = 40MHz 73.5
fIN = 70MHz 73.7Signal-to-Noise Plus Distortion SINAD
fIN = 175MHz 68.6 70.6
dB
fIN = 3MHz 73.8 86.9
fIN = 40MHz 81.9
fIN = 70MHz 84.2Spurious-Free Dynamic Range SFDR
fIN = 175MHz 72.8 79
dBc
fIN = 3MHz -85.3 -72.9
fIN = 40MHz -79.7
fIN = 70MHz -81.7Total Harmonic Distortion THD
fIN = 175MHz -77.1 -71.3
dBc
fIN = 3MHz -87.3
fIN = 40MHz -84.8
fIN = 70MHz -86.7Second Harmonic HD2
fIN = 175MHz -79.9
dBc
fIN = 3MHz -91.4
fIN = 40MHz -81.9
fIN = 70MHz -84.3Third Harmonic HD3
fIN = 175MHz -81.3
dBc
fIN1 = 68.5MHz at -7dBFSfIN2 = 71.5MHz at -7dBFS
-86.53rd-Order IntermodulationDistortion IM3 fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS-87.1
dBc
Full-Power Bandwidth FPBW Input at -0.2dBFS, -3dB rolloff 750 MHz
Aperture Delay tAD Figure 5 1.2 ns
Aperture Jitter tAJ < 0.1 psRMS
Output Noise nOUTINAP = INAN = COMAINBP = INBN = COMB
0.91 LSBRMS
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ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA =-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Overdrive Recovery Time ±10% beyond full scale 1ClockCycle
INTERCHANNEL CHARACTERISTICS
fINA or fINB = 70MHz at -1dBFS 95Crosstalk Rejection
fINA or fINB = 175MHz at -1dBFS 87dB
Gain Matching ±0.01 ±0.1 dB
Offset Matching ±0.01 %FSR
INTERNAL REFERENCE (REFOUT)
REFOUT Output Voltage VREFOUT 2.000 2.048 2.080 V
REFOUT Load Regulation -1mA < IREFOUT < +1mA 35 mV/mA
REFOUT Temperature Coefficient TCREF ±50 ppm/°C
Short to VDD—sinking 0.24REFOUT Short-Circuit Current
Short to GND—sourcing 2.1mA
BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source;VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are generated internally)
REFIN Input Voltage VREFIN 2.048 V
REFIN Input Resistance RREFIN > 50 MΩ
COM_ Output VoltageVCOMAVCOMB
VCOM_ = VDD / 2 1.60 1.65 1.70 V
REF_P Output VoltageVREFAPVREFBP
VREF_P = VDD / 2 + (VREFIN x 3/8) 2.418 V
REF_N Output VoltageVREFANVREFBN
VREF_N = VDD / 2 - (VREFIN x 3/8) 0.882 V
Differential Reference VoltageVREFAVREFB
VREF_ = VREF_P - VREF_N 1.456 1.536 1.595 V
Differential ReferenceTemperature Coefficient
TCREF ±25 ppm/°C
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are appliedexternally, VCOMA = VCOMB = VDD / 2)
REF_P Input VoltageVREFAPVREFBP
VREF_P - VCOM_ +0.768 V
REF_N Input VoltageVREFANVREFBN
VREF_N - VCOM_ -0.768 V
COM_ Input Voltage VCOM_ VCOM_ = VDD / 2 1.65 V
Differential Reference VoltageVREFAVREFB
VREF_ = VREF_P - VREF_N = VREFIN x 3/4 1.536 V
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ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA =-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REF_P Sink CurrentIREFAPIREFBP
VREF_P = 2.418V 1.2 mA
REF_N Source CurrentIREFANIREFBN
VREF_N = 0.882V 0.85 mA
COM_ Sink CurrentICOMAICOMB
VCOM_ = 1.65V 0.85 mA
REF_P, REF_N CapacitanceCREF_P,CREF_N
13 pF
COM_ Capacitance CCOM_ 6 pF
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input HighThreshold
VIH DIFFCLK/SECLK = GND, CLKN = GND0.8 xVDD
V
Single-Ended Input LowThreshold
VIL DIFFCLK/SECLK = GND, CLKN = GND0.2 xVDD
V
Minimum Differential Clock InputVoltage Swing
DIFFCLK/SECLK = OVDD 0.2 VP-P
Differential Input Common-ModeVoltage
DIFFCLK/SECLK = OVDD VDD / 2 V
CLKP, CLKN Input Resistance RCLK Each input, Figure 4 5 kΩCLKP, CLKN Input Capacitance CCLK 2 pF
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4, SHREF)
Input High Threshold VIH0.8 xOVDD
V
Input Low Threshold VIL0.2 xOVDD
V
OVDD applied to input ±5Input Leakage Current
Input connected to ground ±5µA
Digital Input Capacitance CDIN 5 pF
DIGITAL OUTPUTS (D0A–D13A, D0B–D13B, DORA, DORB, DAV)
D0A–D13A, D0B–D13B, DORA, DORB:ISINK = 200µA
0.2Output-Voltage Low VOL
DAV: ISINK = 600µA 0.2
V
D0A–D13A, D0B–D13B, DORA, DORB:ISOURCE = 200µA
OVDD -0.2
Output-Voltage High VOH
DAV: ISOURCE = 600µAOVDD -
0.2
V
OVDD applied to input ±5Tri-State Leakage Current(Note 3)
ILEAKInput connected to ground ±5
µA
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Dual, 80Msps, 14-Bit, IF/Baseband ADC
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ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA =-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
D 0A–D 13A, D O RA,D 0B–D 13B, and D O RB Tr i - S tateO utp ut C ap aci tance ( N ote 3)
COUT 3 pF
DAV Tri-State OutputCapacitance (Note 3)
CDAV 6 pF
POWER REQUIREMENTS
Analog Supply Voltage VDD 3.15 3.30 3.60 V
Digital Output Supply Voltage OVDD 1.70 2.0 VDD V
Normal operating modefIN = 175MHzsingle-ended clock(DIFFCLK/SECLK = GND)
229
Normal operating modefIN = 175MHzdifferential clock(DIFFCLK/SECLK = OVDD)
239 273Analog Supply Current IVDD
Power-down mode (PD = OVDD)clock idle
0.1
mA
Normal operating modefIN = 175MHzsingle-ended clock(DIFFCLK/SECLK = GND)
756
Normal operating modefIN = 175MHzdifferential clock(DIFFCLK/SECLK = OVDD)
789 900Analog Power Dissipation PVDD
Power-down mode (PD = OVDD)clock idle
0.33
mW
Normal operating modefIN = 175MHz, CL ≈ 10pF
22.6
Digital Output Supply Current IOVDDPower-down mode (PD = OVDD)clock idle
0.004
mA
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Dual, 80Msps, 14-Bit, IF/Baseband ADC
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ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA =-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figure 5)
Clock Pulse-Width High tCH 6.2 ns
Clock Pulse-Width Low tCL 6.2 ns
Data-Valid Delay tDAV (Note 4) 5.8 ns
Data Setup Time Before RisingEdge of DAV
tSETUP (Notes 4, 5), OVDD = 1.8V 5.5 ns
Data Hold Time After Rising Edgeof DAV
tHOLD (Notes 4, 5), OVDD = 1.8V 5.5 ns
Wake-Up Time from Power-Down tWAKE VREFIN = 2.048V 10 ms
Note 1: Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization.Note 2: Guaranteed by design and characterization. Device tested for performance during production test.Note 3: During power-down, D0A–D13A, D0B–D13B, DORA, DORB, and DAV are high impedance.Note 4: Data outputs settle to VIH or VIL.Note 5: Guaranteed by design and characterization.
Typical Operating Characteristics(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential),DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
FFT PLOT (32,768-POINT DATA RECORD)
MAX
1255
8 to
c01
ANALOG INPUT FREQUENCY (MHz)
AMPL
ITUD
E (d
BFS)
-100
-80
-60
-40
-20
0
-120
HD3
fCLK = 80MHzfIN = 3.00883MHzAIN = -1.013dBFSSNR = 75.3dBSINAD = 75.1dBTHD = -90.1dBcSFDR = 91.8dBcHD2 = -91.8dBcHD3 = -102dBc
HD2
-10
-30
-50
-70
-90
-110
3525 403015 201050
FFT PLOT (32,768-POINT DATA RECORD)
MAX
1255
8 to
c02
ANALOG INPUT FREQUENCY (MHz)
AMPL
ITUD
E (d
BFS)
-100
-80
-60
-40
-20
0
-120
HD3
fCLK = 80MHzfIN = 39.50928MHzAIN = -1.024dBFSSNR = 74.4dBSINAD = 73.5dBTHD = -80.8dBcSFDR = 83.3dBcHD2 = -85.5dBcHD3 = -82.6dBcHD2
-10
-30
-50
-70
-90
-110
3525 403015 201050
FFT PLOT (32,768-POINT DATA RECORD)
MAX
1255
8 to
c03
ANALOG INPUT FREQUENCY (MHz)
AMPL
ITUD
E (d
BFS)
-100
-80
-60
-40
-20
0
-120
fCLK = 80MHzfIN = 70.09846MHzAIN = -1.03dBFSSNR = 74.2dBSINAD = 73.7dBTHD = -83.3dBcSFDR = 85.8dBcHD2 = -88.7dBcHD3 = -85.8dBc
-10
-30
-50
-70
-90
-110
HD3HD2
3525 403015 201050
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0 4096 61442048 8192 10,240 12,288 14,336 16,384
INTEGRAL NONLINEARITYvs. DIGITAL OUTPUT CODE
MAX
1255
8 to
c07
DIGITAL OUTPUT CODE
INL
(LSB
)
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
-2.0 -1.00
-0.50
-0.75
0
-0.25
0.25
0.50
0.75
1.00
DIFFERENTIAL NONLINEARITYvs. DIGITAL OUTPUT CODE
MAX
1255
8 to
c08
DIGITAL OUTPUT CODE
DNL
(LSB
)
0 4096 61442048 8192 10,240 12,288 14,336 16,38440
50
45
60
55
65
70
75
80
0 100 15050 200 250 300 350 400
SNR, SINAD vs. ANALOG INPUT FREQUENCY(fCLK = 80MHz, AIN = -1dBFS)
MAX
1255
8 to
c09
fIN (MHz)
SNR,
SIN
AD (d
B)SNR
SINAD
50
60
55
75
70
65
90
85
80
95
0 150 20050 100 250 300 350 400
-THD, SFDR vs. ANALOG INPUT FREQUENCY(fCLK = 80MHz, AIN = -1dBFS)
MAX
1255
8 to
c10
fIN (MHz)
-THD
, SFD
R (d
Bc) SFDR
-THD
MAX
1255
8 to
c11
AIN (dBFS)
SNR,
SIN
AD (d
B)
SNR, SINAD vs. ANALOG INPUT AMPLITUDE(fCLK = 80MHz, fIN = 70MHz)
SINAD
SNR
-5-10-15-20-25-30-35-40-45-50-55
20
30
40
50
60
70
80
10-60 0
MAX
1255
8 to
c12
AIN (dBFS)
-THD
, SFD
R (d
Bc)
-THD, SFDR vs. ANALOG INPUT AMPLITUDE(fCLK = 80MHz, fIN = 70MHz)
-THD
SFDR
-5-10-15-20-25-30-35-40-45-50-55-60 0
45
55
65
75
85
95
35
FFT PLOT (32,768-POINT DATA RECORD)
MAX
1255
8 to
c04
ANALOG INPUT FREQUENCY (MHz)
AMPL
ITUD
E (d
BFS)
-100
-80
-60
-40
-20
0
-120
fCLK = 80MHzfIN = 174.97827MHzAIN = -1.093dBFSSNR = 71.8dBSINAD = 70.9dBTHD = -78.2dBcSFDR = 79.4dBcHD2 = -102.3dBcHD3 = -79.4dBc
HD2
-10
-30
-50
-70
-90
-110
HD3
3525 403015 201050
TWO-TONE IMD PLOT(32,768-POINT DATA RECORD)
MAX
1255
8 to
c05
ANALOG INPUT FREQUENCY (MHz)
AMPL
ITUD
E (d
BFS)
fCLK = 80MHzfIN1 = 68.50117MHzfIN2 = 71.49933MHzAIN1 = AIN2 = -7dBFSIM3 = -94.7dBc
fIN2 - fIN1 fIN1 + fIN22fIN2 + fIN1
2fIN1 + fIN2
fIN2fIN1
3525 3015 201050
-100
-80
-60
-40
-20
0
-120
TWO-TONE IMD PLOT(32,768-POINT DATA RECORD)
MAX
1255
8 to
c06
ANALOG INPUT FREQUENCY (MHz)
AMPL
ITUD
E (d
BFS)
3525 3015 201050
fIN2 - fIN1
2fIN1 - fIN22fIN2 - fIN1
fIN1
-100
-80
-60
-40
-20
0
-120
fCLK = 80MHzfIN1 = 172.499299MHzfIN2 = 177.499492MHzAIN1 = AIN2 = -7dBFSIM3 = -87.5dBc
fIN2
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
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MAX
1255
8 to
c13
AIN (dBFS)
SNR,
SIN
AD (d
B)
SNR, SINAD vs. ANALOG INPUT AMPLITUDE(fCLK = 80MHz, fIN = 175MHz)
SINAD
SNR
-5-10-15-20-25-30-35-40-45-50-55-60 0
25
35
45
55
65
75
15 35
55
45
75
65
85
95
-55 -45 -40 -35-50 -30 -25 -20 -15 -10 -5 0
MAX
1255
8 to
c14
AIN (dBFS)
-THD
, SFD
R (d
Bc)
-THD, SFDR vs. ANALOG INPUT AMPLITUDE(fCLK = 80MHz, fIN = 175MHz)
-THD
SFDR
60
64
68
72
76
80
SNR, SINAD vs. CLOCK SPEED(fIN = 70MHz, AIN = -1dBFS)
MAX
1255
8 to
c15
fCLK (MHz)
SNR,
SIN
AD (d
B)
SNR
SINAD
7060504030 80
-THD, SFDR vs. CLOCK SPEED(fIN = 70MHz, AIN = -1dBFS)
MAX
1255
8 to
c16
fCLK (MHz)
-THD
, SFD
R (d
Bc)
SFDR
-THD
70605040
55
60
65
70
75
80
85
90
95
100
5030 80
SNR, SINAD vs. CLOCK SPEED(fIN = 175MHz, AIN = -1dBFS)
MAX
1255
8 to
c17
fCLK (MHz)
SNR,
SIN
AD (d
B)
SNR
SINAD
70605040
55
60
65
70
75
80
5030 80
50
55
60
70
75
80
85
90
30 5040 60 70 80
-THD, SFDR vs. CLOCK SPEED(fIN = 175MHz, AIN = -1dBFS)
MAX
1255
8 to
c18
fCLK (MHz)
-THD
, SFD
R (d
Bc)
-THD
65
SFDR
50
60
55
70
65
75
80
3.0 3.23.1 3.3 3.4 3.5 3.6
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 70MHz)
MAX
1255
8 to
c19
VDD (V)
SNR,
SIN
AD (d
B)
SNR
SINAD
55
60
70
65
80
75
90
85
95
3.0 3.2 3.33.1 3.4 3.5 3.6
MAX
1255
8 to
c20
VDD (V)
-THD
, SFD
R (d
Bc)
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 70MHz)
SFDR
-THD
50
55
65
60
70
75
3.0 3.23.1 3.3 3.4 3.5 3.6
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 175MHz)
MAX
1255
8 to
c21
VDD (V)
SNR,
SIN
AD (d
B)
SNR
SINAD
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
MA
X1
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58
Dual, 80Msps, 14-Bit, IF/Baseband ADC
10 ______________________________________________________________________________________
60
65
75
70
80
85
3.0 3.23.1 3.3 3.4 3.5 3.6
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 175MHz)
MAX
1255
8 to
c22
VDD (V)
-THD
, SFD
R (d
Bc)
SFDR
-THD
50
60
55
70
65
75
80
1.6 2.01.8 2.2 2.4 2.6 2.8 3.0 3.2 3.4
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 70MHz)
MAX
1255
8 to
c23
OVDD (V)
SNR,
SIN
AD (d
B)
SNR
SINAD
3.6
MAX
1255
8 to
c24
OVDD (V)
-THD
, SFD
R (d
Bc)
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 70MHz)
SFDR
-THD
3.43.21.8 2.0 2.2 2.6 2.82.4 3.0
60
65
70
75
80
85
90
95
551.6 3.6
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 175MHz)
MAX
1255
8 to
c25
OVDD (V)
SNR,
SIN
AD (d
B)
SNR
SINAD
3.43.23.02.82.62.42.22.01.8
55
60
65
70
75
80
501.6 3.6
65
69
77
73
81
85
1.6 1.8 2.42.22.0 2.6 2.8 3.0 3.2 3.4
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 175MHz)
MAX
1255
8 to
c26
OVDD (V)
-THD
, SFD
R (d
Bc)
SFDR
-THD
3.6100
300
200
600
500
400
900
800
700
1000
3.0 3.23.1 3.3 3.4 3.5 3.6
PDISS (ANALOG), IVDD vs. ANALOG SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 175MHz)
MAX
1255
8 to
c27
VDD (V)
P DIS
S, I V
DD (m
W, m
A)PDISS (ANALOG)
IVDD
0
20
10
40
30
70
60
50
80
1.6 2.01.8 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
MAX
1255
8 to
c28
OVDD (V)
PDISS (DIGITAL), IOVDDvs. DIGITAL SUPPLY VOLTAGE(fCLK = 80MHz, fIN = 175MHz)
P DIS
S, I O
VDD
(mW
, mA)
PDISS (DIGITAL)
IOVDD
50
55
65
60
70
75
25 4535 55 65 75
SNR, SINAD vs. CLOCK DUTY CYCLE(fIN = 70MHz, AIN = -1dBFS)
MAX
1255
8 to
c29
CLOCK DUTY CYCLE (%)
SNR,
SIN
AD (d
B)
SINGLE-ENDED CLOCK DRIVE
SNRSINAD
60
70
65
80
75
85
90
25 4535 55 65 75
-THD, SFDR vs. CLOCK DUTY CYCLE(fIN = 70MHz, AIN = -1dBFS)
MAX
1255
8 to
c30
CLOCK DUTY CYCLE (%)
-THD
, SFD
R (d
Bc)
SINGLE-ENDED CLOCK DRIVE
SFDR
-THD
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
MA
X1
25
58
Dual, 80Msps, 14-Bit, IF/Baseband ADC
______________________________________________________________________________________ 11
60
69
66
63
72
75
-40 10-15 35 60 85
SNR, SINAD vs. TEMPERATURE(fIN = 175MHz, AIN = -1dBFS)
MAX
1255
8 to
c31
TEMPERATURE (°C)
SNR,
SIN
AD (d
B)
SNR
SINAD
60
80
75
70
65
90
85
95
100
-40 10-15 35 60 85
-THD, SFDR vs. TEMPERATURE(fIN = 175MHz, AIN = -1dBFS)
MAX
1255
8 to
c32
TEMPERATURE (°C)-T
HD, S
FDR
(dBc
) SFDR
-THD
-1.0
-0.6
0.2
-0.2
0.6
1.0
-40 10-15 35 60 85
GAIN ERROR vs. TEMPERATURE(VREFIN = 2.048V)
MAX
1255
8 to
c33
TEMPERATURE (°C)
GAIN
ERR
OR (%
FSR)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
-40 -15 10 35 60 85
OFFSET ERROR vs. TEMPERATURE
MAX
1255
8 to
c34
TEMPERATURE (°C)
OFFS
ET E
RROR
(%FS
R)
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
MA
X1
25
58
Dual, 80Msps, 14-Bit, IF/Baseband ADC
12 ______________________________________________________________________________________
PIN NAME FUNCTION
1, 4, 5, 9,13, 14, 17
GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together.
2 INAP Channel A Positive Analog Input
3 INAN Channel A Negative Analog Input
6 COMA Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.
7 REFAP
Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). BypassREFAP with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFAPand REFAN. Place the 0.1µF REFAP-to-REFAN capacitor as close to the device as possible on thesame side of the PC board.
8 REFAN
Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). BypassREFAN with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFAPand REFAN. Place the 0.1µF REFAP-to-REFAN capacitor as close to the device as possible on thesame side of the PC board.
10 REFBN
Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). BypassREFBN with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFBPand REFBN. Place the 0.1µF REFBP-to-REFBN capacitor as close to the device as possible on thesame side of the PC board.
11 REFBP
Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). BypassREFBP with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFBPand REFBN. Place the 0.1µF REFBP-to-REFBN capacitor as close to the device as possible on thesame side of the PC board.
12 COMB Channel B Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.
15 INBN Channel B Negative Analog Input
16 INBP Channel B Positive Analog Input
18DIFFCLK/SECLK
Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clockinput drives.DIFFCLK/SECLK = GND: Selects single-ended clock input drive.DIFFCLK/SECLK = OVDD: Selects differential clock input drive.
19 CLKNNegative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differentialclock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), applythe clock signal to CLKP and connect CLKN to GND.
20 CLKPPositive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differentialclock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), applythe single-ended clock signal to CLKP and connect CLKN to GND.
21 DIV2 Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.
22 DIV4 Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.
23–26, 61,62, 63
VDDAnalog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallelcapacitor combination of ≥ 10µF and 0.1µF. Connect all VDD pins to the same potential.
27, 43, 60 OVDDOutput-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with aparallel capacitor combination of ≥ 10µF and 0.1µF.
Pin Description
MA
X1
25
58
Dual, 80Msps, 14-Bit, IF/Baseband ADC
______________________________________________________________________________________ 13
PIN NAME FUNCTION
28 D0B Channel B CMOS Digital Output, Bit 0 (LSB)
29 D1B Channel B CMOS Digital Output, Bit 1
30 D2B Channel B CMOS Digital Output, Bit 2
31 D3B Channel B CMOS Digital Output, Bit 3
32 D4B Channel B CMOS Digital Output, Bit 4
33 D5B Channel B CMOS Digital Output, Bit 5
34 D6B Channel B CMOS Digital Output, Bit 6
35 D7B Channel B CMOS Digital Output, Bit 7
36 D8B Channel B CMOS Digital Output, Bit 8
37 D9B Channel B CMOS Digital Output, Bit 9
38 D10B Channel B CMOS Digital Output, Bit 10
39 D11B Channel B CMOS Digital Output, Bit 11
40 D12B Channel B CMOS Digital Output, Bit 12
41 D13B Channel B CMOS Digital Output, Bit 13 (MSB)
42 DORB
Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analoginput voltage is out of range.DORB = 1: Digital outputs exceed full-scale range.DORB = 0: Digital outputs are within full-scale range.
44 DAVData-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs.The MAX12558 evaluation kit utilizes DAV to latch data into any external back-end digital logic.
45 D0A Channel A CMOS Digital Output, Bit 0 (LSB)
46 D1A Channel A CMOS Digital Output, Bit 1
47 D2A Channel A CMOS Digital Output, Bit 2
48 D3A Channel A CMOS Digital Output, Bit 3
49 D4A Channel A CMOS Digital Output, Bit 4
50 D5A Channel A CMOS Digital Output, Bit 5
51 D6A Channel A CMOS Digital Output, Bit 6
52 D7A Channel A CMOS Digital Output, Bit 7
53 D8A Channel A CMOS Digital Output, Bit 8
54 D9A Channel A CMOS Digital Output, Bit 9
55 D10A Channel A CMOS Digital Output, Bit 10
56 D11A Channel A CMOS Digital Output, Bit 11
57 D12A Channel A CMOS Digital Output, Bit 12
58 D13A Channel A CMOS Digital Output, Bit 13 (MSB)
59 DORA
Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analoginput voltage is out of range.DORA = 1: Digital outputs exceed full-scale range.DORA = 0: Digital outputs are within full-scale range.
64 G/TOutput Format Select Digital Input.G/T = GND: Two’s-complement output format selected.G/T = OVDD: Gray-code output format selected.
Pin Description (continued)
MA
X1
25
58
Detailed DescriptionThe MAX12558 uses a 10-stage, fully differential,pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consump-tion. Samples taken at the inputs move progressivelythrough the pipeline stages every half clock cycle.From input to output the total latency is 8 clock cycles.
Each pipeline converter stage converts its input voltageto a digital output code. At every stage, except the last,the error between the input voltage and the digital out-put code is multiplied and passed on to the nextpipeline stage. Digital error correction compensates forADC comparator offsets in each pipeline stage andensures no missing codes. Figure 2 shows theMAX12558 functional diagram.
Dual, 80Msps, 14-Bit, IF/Baseband ADC
14 ______________________________________________________________________________________
PIN NAME FUNCTION
65 PDPower-Down Digital Input.PD = GND: ADCs are fully operational.PD = OVDD: ADCs are powered down.
66 SHREF
Shared Reference Digital Input.SHREF = VDD: Shared reference enabled.SHREF = GND: Shared reference disabled.When sharing the reference, externally connect REFAP and REFBP together to ensure that VREFAP =VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensurethat VREFAN = VREFBN.
67 REFOUT
Inter nal Refer ence V ol tag e O utp ut. The RE FOU T outp ut vol tag e i s 2.048V and RE FO U T can d el i ver 1m A.For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider fromREFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥ 0.1µF capacitor.For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥ 0.1µFcapacitor.
68 REFIN
Single-Ended Reference Analog Input. For i nter nal r efer ence and b uffer ed exter nal r efer ence op er ati on,ap p l y a 0.7V to 2.3V D C r efer ence vol tag e to RE FIN . B y p a s s REF I N t o GN D w it h a 4 . 7 µ F c a p a c i t o r . W i thi n i ts sp eci fi ed op er ati ng vol tag e, RE FIN has a > 50M Ω i np ut i m p ed ance, and the d i ffer enti al r efer ence vol tag e ( V R E F_ P - V R E F_ N ) i s g ener ated fr om RE FIN . For unb uffer ed exter nal r efer enceop er ati on, connect RE FIN to G N D . In thi s m od e, RE F_P , RE F_N , and C O M _ ar e hi g h- i m p ed ance i np utsthat accep t the exter nal r efer ence vol tag es.
— EPExposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve thespecified dynamic performance.
Pin Description (continued)
MAX12558Σ
+
−
DIGITAL ERROR CORRECTION
FLASHADC
x2
DAC
STAGE 2IN_P
IN_NSTAGE 1 STAGE 9
STAGE 10END OF PIPELINE
D0_ THROUGH D13_
Figure 1. Pipeline Architecture—Stage Blocks
MA
X1
25
58
Dual, 80Msps, 14-Bit, IF/Baseband ADC
______________________________________________________________________________________ 15
INBP
14-BITPIPELINE
ADC
DIGITALERROR
CORRECTION
CHANNEL AREFERENCE
SYSTEMCOMAREFAN
REFAP
OVDD
DAV
OUTPUTDRIVERS
DORA
CLOCKDIVIDER
DATAFORMAT
14-BITPIPELINE
ADC
DIGITALERROR
CORRECTION
OUTPUTDRIVERS
DATAFORMAT
DIV2DIV4
INBN
D0B TO D13B
DORB
CHANNEL BREFERENCE
SYSTEMCOMBREFBN
REFBP
INAP
INAN
CLKP
CLKN
DUTY-CYCLEEQUALIZER
CLOCK
CLOCK
POWERCONTROL
ANDBIAS CIRCUITS
PD
VDD
GND
CLOCK
REFININTERNAL
REFERENCEGENERATOR
REFOUT
SHREF
DIFFCLK/SECLK
D0A TO D13A
G/T
MAX12558
T/H
T/H
Figure 2. Functional Diagram
MA
X1
25
58
Analog Inputs and Input Track-and-Hold(T/H) Amplifier
Figure 3 displays a simplified functional diagram of theinput T/H circuit. This input T/H circuit allows for highanalog input frequencies (high IF) of 175MHz andbeyond and supports a VDD / 2 common-mode inputvoltage.
The MAX12558 sampling clock controls the switched-capacitor input T/H architecture (Figure 3) allowing theanalog input signals to be stored as charge on thesampling capacitors. These switches are closed (trackmode) when the sampling clock is high and open (holdmode) when the sampling clock is low (Figure 4). Theanalog input signal source must be able to provide thedynamic currents necessary to charge and dischargethe sampling capacitors. To avoid signal degradation,these capacitors must be charged to one-half LSBaccuracy within one-half of a clock cycle. The analoginput of the MAX12558 supports differential or single-ended input drive. For optimum performance with dif-ferential inputs, balance the input impedance of IN_Pand IN_N and set the common-mode voltage to mid-supply (VDD / 2). The MAX12558 provides the optimumcommon-mode voltage of VDD / 2 through the COMoutput when operating in internal reference mode andbuffered external reference mode. This COM outputvoltage can be used to bias the input network as shownin Figures 9, 10, and 11.
Reference OutputAn internal bandgap reference is the basis for all theinternal voltages and bias currents used in theMAX12558. The power-down logic input (PD) enablesand disables the reference circuit. REFOUT has approxi-mately 17kΩ to GND when the MAX12558 is powereddown. The reference circuit requires 10ms to power upand settle to its final value when power is first applied tothe MAX12558 or when PD (power-down control line)transitions from high to low.
The internal bandgap reference produces a bufferedreference voltage of 2.048V ±1% at the REFOUT pinwith a ±50ppm/°C temperature coefficient. Connect anexternal ≥ 0.1µF bypass capacitor from REFOUT toGND for stability. REFOUT sources up to 1mA andsinks up to 0.1mA for external circuits with a 35mV/mAload regulation. Short-circuit protection limits IREFOUTto a 2.1mA source current when shorted to GND and a0.24mA sink current when shorted to VDD. Similar toREFOUT, REFIN should be bypassed with a 4.7µFcapacitor to GND.
Reference ConfigurationsThe MAX12558 full-scale analog input range is ±2/3 xVREF with a VDD / 2 ±0.5V common-mode input range.VREF is the voltage difference between REFAP (REFBP)and REFAN (REFBN). The MAX12558 provides threemodes of reference operation. Setting the voltage atREFIN (VREFIN) selects the reference operation mode(Table 1).
Dual, 80Msps, 14-Bit, IF/Baseband ADC
16 ______________________________________________________________________________________
VREFIN REFERENCE MODE
35% VREFOUTto 100%VREFOUT
Internal Reference Mode. REFIN is driven byREFOUT either through a direct short or aresistive divider.VCOM_ = VDD / 2VREF_P = VDD / 2 + 3/8 x VREFINVREF_N = VDD / 2 - 3/8 x VREFIN
0.7V to 2.3V
Buffered External Reference Mode. Anexternal 0.7V to 2.3V reference voltage isapplied to REFIN.VCOM_ = VDD / 2VREF_P = VDD / 2 + 3/8 x VREFINVREF_N = VDD / 2 - 3/8 x VREFIN
<0.5V
U nb uffer ed E xter nal Refer ence M od e. RE F_P ,RE F_N , and C O M _ ar e d r i ven b y exter nal r efer ence sour ces. The ful l - scal e anal og i np utr ang e i s ± ( V R E F _P - V R E F _N ) x 2/3.
Table 1. Reference Modes
MAX12558
CPAR2pF
VDDBOND WIREINDUCTANCE
1.5nHIN_P
SAMPLINGCLOCK
*THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS:
*CSAMPLE4.5pF
CPAR2pF
VDDBOND WIREINDUCTANCE
1.5nHIN_N
*CSAMPLE4.5pF
RIN =1
fCLK x CSAMPLE
Figure 3. Internal T/H Circuit
Connect REFOUT to REFIN either with a direct short orthrough a resistive divider for internal reference mode.COM_, REF_P, and REF_N are low-impedance outputswith VCOM_ = VDD / 2, VREFP = VDD / 2 + 3/8 x VREFIN,and VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P,REF_N, and COM_ each with a 0.1µF capacitor to GND.Bypass REF_P to REF_N with a 10µF capacitor. BypassREFIN and REFOUT to GND with a 0.1µF capacitor. TheREFIN input impedance is very large (> 50MΩ). Whendriving REFIN through a resistive divider, use resistances≥ 10kΩ to avoid loading REFOUT.
Buffered external reference mode is virtually identical tothe internal reference mode except that the referencesource is derived from an external reference and not theMAX12558’s internal bandgap reference. In bufferedexternal reference mode, apply a stable reference volt-age source between 0.7V to 2.3V at REFIN. Pins COM_,REF_P, and REF_N are low-impedance outputs withVCOM_ = VDD / 2, VREF_P = VDD / 2 + 3/8 x VREFIN, andVREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P, REF_N,and COM_ each with a 0.1µF capacitor to GND. BypassREF_P to REF_N with a 4.7µF capacitor.
Connect REFIN to GND to enter unbuffered external ref-erence mode. Connecting REFIN to GND deactivatesthe on-chip reference buffers for COM_, REF_P, andREF_N. With their buffers deactivated, COM_, REF_P,and REF_N become high-impedance inputs and mustbe driven with separate, external reference sources.Drive VCOM_ to VDD / 2 ±5%, and drive REF_P andREF_N so VCOM_ = (VREF_P_ + VREF_N_) / 2. The analoginput range is ±(VREF_P_ - VREF_N) x 2/3. BypassREF_P, REF_N, and COM_ each with a 0.1µF capacitorto GND. Bypass REF_P to REF_N with a 4.7µF capacitor.
For all reference modes, bypass REFOUT with a 0.1µFand REFIN with a 4.7µF capacitor to GND.
The MAX12558 also features a shared reference mode,in which the user can achieve better channel-to-chan-nel matching. When sharing the reference (SHREF =VDD), externally connect REFAP and REFBP together toensure that VREFAP = VREFBP. Similarly, when sharingthe reference, externally connect REFAN to REFBNtogether to ensure that VREFAN = VREFBN.
Connect SHREF to GND to disable the shared refer-ence mode of the MAX12558. In this independent refer-ence mode, a better channel-to-channel isolation isachieved.
For detailed circuit suggestions and how to drive theADC in buffered/unbuffered external reference mode,see the Applications Information section.
Clock Duty-Cycle EqualizerThe MAX12558 has an internal clock duty-cycle equaliz-er, which makes the converter insensitive to the dutycycle of the signal applied to CLKP and CLKN. The con-verters allow clock duty-cycle variations from 25% to 75%without negatively impacting the dynamic performance.
The clock duty-cycle equalizer uses a delay-lockedloop (DLL) to create internal timing signals that areduty-cycle independent. Due to this DLL, theMAX12558 requires approximately 100 clock cycles toacquire and lock to new clock frequencies.
Clock Input and Clock Control LinesThe MAX12558 accepts both differential and single-ended clock inputs with a wide 25% to 75% input clockduty cycle. For single-ended clock input operation,connect DIFFCLK/SECLK and CLKN to GND. Apply anexternal single-ended clock signal to CLKP. To reduceclock jitter, the external single-ended clock must havesharp falling edges. For differential clock input opera-tion, connect DIFFCLK/SECLK to OVDD. Apply anexternal differential clock signal to CLKP and CLKN.Consider the clock input as an analog input and route itaway from any other analog inputs and digital signallines. CLKP and CLKN enter high impedance when theMAX12558 is powered down (Figure 4).
Low clock jitter is required for the specified SNR perfor-mance of the MAX12558. The analog inputs are sam-pled on the falling (rising) edge of CLKP (CLKN),requiring this edge to have the lowest possible jitter.Jitter limits the maximum SNR performance of any ADCaccording to the following relationship:
where fIN represents the analog input frequency and tJis the total system clock jitter. Clock jitter is especiallycritical for undersampling applications. For instance,assuming that clock jitter is the only noise source, toobtain the specified 71.7dB of SNR with an input fre-quency of 175MHz the system must have less than0.24ps of clock jitter. However, in reality there are othernoise sources such as thermal noise and quantizationnoise that contribute to the system noise requiring theclock jitter to be less than 0.17ps to obtain the speci-fied 71.7dB of SNR at 175MHz.
Clock-Divider Control Inputs (DIV2, DIV4)The MAX12558 features three different modes of sam-pling/clock operation (see Table 2). Pulling both controllines low, the clock-divider function is disabled and theconverters sample at full clock speed. Pulling DIV4 low
SNRf tIN J
log
= ×× × ×
⎛
⎝⎜⎞
⎠⎟20
12 π
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______________________________________________________________________________________ 17
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and DIV2 high enables the divide-by-two feature, whichsets the sampling speed to one-half the selected clockfrequency. In divide-by-four mode, the converter sam-pling speed is set to one-fourth the clock speed of theMAX12558. Divide-by-four mode is achieved by applyinga high level to DIV4 and a low level to DIV2. The option toselect either one-half or one-fourth of the clock speed forsampling provides design flexibility, relaxes clockrequirements, and can minimize clock jitter.
System Timing RequirementsFigure 5 shows the timing relationship between theclock, analog inputs, DAV indicator, DOR_ indicators,and the resulting output data. The analog input is sam-
pled on the falling (rising) edge of CLKP (CLKN) andthe resulting data appears at the digital outputs 8 clockcycles later.
The DAV indicator is synchronized with the digital out-put and optimized for use in latching data into digitalback-end circuitry. Alternatively, digital back-end cir-cuitry can be latched with the rising edge of the con-version clock (CLKP - CLKN).
Data-Valid OutputDAV is a single-ended version of the input clock that iscompensated to correct for any input clock duty-cyclevariations. The MAX12558 output data changes on thefalling edge of DAV, and DAV rises once the outputdata is valid. The falling edge of DAV is synchronizedto have a 5.4ns delay from the falling edge of the inputclock. Output data at D0A/B–D13A/B and DORA/B arevalid from 7ns before the rising edge of DAV to 7nsafter the rising edge of DAV.
DAV enters high impedance when the MAX12558 ispowered down (PD = OVDD). DAV enters its high-impedance state 10ns after the rising edge of PD andbecomes active again 10ns after PD transitions low.
DAV can sink and source 600µA and has three times thedriving capabilities of D0A/B–D13A/B and DORA/B. DAV
Dual, 80Msps, 14-Bit, IF/Baseband ADC
18 ______________________________________________________________________________________
MAX12558
CLKP
CLKN
VDD
GND
10kΩ
10kΩ
10kΩ
10kΩ
DUTY-CYCLEEQUALIZER
S1H
S2H
S2L
S1L
SWITCHES S1_ AND S2_ ARE OPENDURING POWER-DOWN, MAKINGCLKP AND CLKN HIGH IMPEDANCE.SWITCHES S2_ ARE OPEN INSINGLE-ENDED CLOCK MODE.
Figure 4. Simplified Clock Input Circuit
DIV4 DIV2 FUNCTION
0 0Clock Divider DisabledfSAMPLE = fCLK
0 1Divide-by-Two Clock DividerfSAMPLE = fCLK / 2
1 0Divide-by-Four Clock DividerfSAMPLE = fCLK / 4
1 1 Not Allowed
Table 2. Clock-Divider Control Inputs
DAV
N N + 1 N +2
N + 3
N + 4 N + 5N + 6
N + 7
N + 8
N + 9
tDAV
tSETUP
tAD
N - 1N - 2N - 3
tHOLD
tCL tCH
DIFFERENTIAL ANALOG INPUT (IN_P–IN_N)
CLKN
CLKP
(VREF_P - VREF_N) x 2/3
(VREF_N - VREF_P) x 2/3
N + 4 D0_–D13_
DOR
8.0 CLOCK-CYCLE DATA LATENCY tSETUP tHOLD
N N + 1 N + 2 N + 3 N + 5 N + 6 N + 7N - 1N - 2N - 3 N + 9N + 8
Figure 5. System Timing Diagram
is typically used to latch the MAX12558 output data intoan external digital back-end circuit. Keep the capacitiveload on DAV as low as possible (< 15pF) to avoid largedigital currents feeding back into the analog portion ofthe MAX12558, thereby degrading its dynamic perfor-mance. Buffering DAV externally isolates it from heavycapacitive loads. Refer to the MAX12558 EV kit schemat-ic for recommendations of how to drive the DAV signalthrough an external buffer.
Data Out-of-Range IndicatorThe DORA and DORB digital outputs indicate when theanalog input voltage is out of range. When DOR_ is high,the analog input is out of range. When DOR_ is low, theanalog input is within range. The valid differential inputrange is from (VREF_P - VREF_N) x 2/3 to (VREF_N -VREF_P) x 2/3. Signals outside of this valid differentialrange cause DOR_ to assert high as shown in Table 1.
DOR is synchronized with DAV and transitions alongwith the output data D13–D0. There is an 8 clock-cyclelatency in the DOR function as is with the output data(Figure 5). DOR_ is high impedance when the
MAX12558 is in power-down (PD = high). DOR_ entersa high-impedance state within 10ns after the rising edgeof PD and becomes active 10ns after PD’s falling edge.
Digital Output Data and Output Format SelectionThe MAX12558 provides two 14-bit, parallel, tri-stateoutput buses. D0A/B–D13A/B and DORA/B update onthe falling edge of DAV and are valid on the rising edgeof DAV.
The MAX12558 output data format is either Gray codeor two’s complement depending on the logic input G/T.With G/T high, the output data format is Gray code.With G/T low, the output data format is set to two’s com-plement. See Figure 8 for a binary-to-Gray and Gray-to-binary code conversion example.
The following equations, Table 3, Figure 6, and Figure 7define the relationship between the digital output andthe analog input.
Gray Code (G/T = 1):
VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x (CODE10 - 8192) / 16,384
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______________________________________________________________________________________ 19
GRAY-CODE OUTPUT CODE(G/T = 1)
TWO’S-COMPLEMENT OUTPUT CODE(G/T = 0)
BINARYD13A–D0AD13B–D0B
DOR
H EXA D ECIM A LEQUIVALENT
OFD13A–D0AD13B–D0B
DECIMALEQUIVALENT
OFD13A–D0AD13B–D0B(CODE10)
BINARYD13A–D0AD13B–D0B
DOR
HEXADECIMALEQUIVALENT
OFD13A–D0AD13B–D0B
DECIMALEQUIVALENT
OFD13A–D0AD13B–D0B(CODE10)
VIN_P - VIN_NVREF_P = 2.418VVREF_N = 0.882V
10 0000 0000 0000 1 0x2000 +16,383 01 1111 1111 1111 1 0x1FFF +8191> +1.023875V(DATA OUT OF
RANGE)
10 0000 0000 0000 0 0x2000 +16,383 01 1111 1111 1111 0 0x1FFF +8191 +1.023875V
10 0000 0000 0001 0 0x2001 +16,382 01 1111 1111 1110 0 0x1FFE +8190 +1.023750V
11 0000 0000 0011 0 0x3003 +8194 00 0000 0000 0010 0 0x0002 +2 +0.000250V
11 0000 0000 0001 0 0x3001 +8193 00 0000 0000 0001 0 0x0001 +1 +0.000125V
11 0000 0000 0000 0 0x3000 +8192 00 0000 0000 0000 0 0x0000 0 +0.000000V
01 0000 0000 0000 0 0x1000 +8191 11 1111 1111 1111 0 0x3FFF -1 -0.000125V
01 0000 0000 0001 0 0x1001 +8190 11 1111 1111 1110 0 0x3FFE -2 -0.000250V
00 0000 0000 0001 0 0x0001 +1 10 0000 0000 0001 0 0x2001 -8191 -1.023875V
00 0000 0000 0000 0 0x0000 0 10 0000 0000 0000 0 0x2000 -8192 -1.024000V
00 0000 0000 0000 1 0x0000 0 10 0000 0000 0000 1 0x2000 -8192< -1.024000V
(DATA OUT OFRANGE)
Table 3. Output Codes vs. Input Voltage
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Two’s Complement (G/T = 0):
VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x CODE10 / 16,384
where CODE10 is the decimal equivalent of the digitaloutput code as shown in Table 3.
The digital outputs D0A/B–D13A/B are high impedancewhen the MAX12558 is in power-down (PD = 1) mode.D0A/B–D13A/B enter this state 10ns after the risingedge of PD and become active again 10ns after PDtransitions low.
Keep the capacitive load on the MAX12558 digital out-puts D0A/B–D13A/B as low as possible (< 15pF) toavoid large digital currents feeding back into the ana-log portion of the converter and degrading its dynamicperformance. Adding external digital buffers on the dig-ital outputs helps isolate the MAX12558 from heavycapacitive loads. To improve the dynamic performanceof the MAX12558, add 220Ω resistors in series with thedigital outputs close to the MAX12558. Refer to theMAX12558 EV kit schematic for guidelines of how todrive the digital outputs through 220Ω series resistorsand external digital output buffers.
Power-Down InputThe MAX12558 has two power modes that are con-trolled with a power-down digital input (PD). With PD
low, the converter is in its normal operating mode. WithPD high, the MAX12558 is in power-down mode.
The power-down mode allows the MAX12558 to effi-ciently use power by transitioning to a low-power statewhen conversions are not required. Additionally, theMAX12558 parallel output bus goes high impedance inpower-down mode, allowing other devices on the busto be accessed.
In power-down mode all internal circuits are off, theanalog supply current reduces to less than 50µA, andthe digital supply current reduces to 1µA. The followinglist shows the state of the analog inputs and digital out-puts in power-down mode.
1) INAP/B, INAN/B analog inputs are disconnectedfrom the internal input amplifier (Figure 3).
2) REFOUT has approximately 17kΩ to GND.
3) REFAP/B, COMA/B, REFAN/B enter a high-imped-ance state with respect to VDD and GND, but thereis an internal 4kΩ resistor between REFAP/B andCOMA/B as well as an internal 4kΩ resistorbetween REFAN/B and COMA/B.
4) D0A–D13A, D0B–D13B, DORA, and DORB enter ahigh-impedance state.
5) DAV enters a high-impedance state.
6) CLKP, CLKN clock inputs enter a high-impedancestate (Figure 4).
Dual, 80Msps, 14-Bit, IF/Baseband ADC
20 ______________________________________________________________________________________
DIFFERENTIAL INPUT VOLTAGE (LSB)
TWO'
S-CO
MPL
EMEN
T OU
TPUT
COD
E (L
SB)
-8189 +8191+8189-1 0 +1-8191
0x20000x20010x20020x2003
0x1FFF0x1FFE0x1FFD
0x3FFF0x00000x0001
2/3 x (VREFP - VREFN) 2/3 x (VREFP - VREFN)
1 LSB = 4/3 x (VREFP - VREFN) / 16,384
Figure 6. Two’s-Complement Transfer Function (G/T = 0)
DIFFERENTIAL INPUT VOLTAGE (LSB)
GRAY
OUT
PUT
CODE
(LSB
)-8189 +8191+8189-1 0 +1-8191
0x00000x00010x00030x0002
0x20000x20010x2003
0x10000x30000x3001
2/3 x (VREFP - VREFN) 2/3 x (VREFP - VREFN)
1 LSB = 4/3 x (VREFP - VREFN) / 16,384
Figure 7. Gray-Code Transfer Function (G/T = 1)
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BINARY-TO-GRAY CODE CONVERSION
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAMEAS THE MOST SIGNIFICANT BINARY BIT.
0 1 1 0 0 1 0 0 1 1 0 0 BINARY
GRAY CODE0
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDINGTO THE FOLLOWING EQUATION:
D13 D7 D3 D0
GRAYX = BINARYX + BINARYX + 1
BIT POSITION
0 1 1 0 0 1 0 0 1 1 0 0 BINARY
GRAY CODE0
BIT POSITION
GRAY12 = BINARY12 BINARY13
GRAY12 = 1 0
GRAY12 = 1
1
3) REPEAT STEP 2 UNTIL COMPLETE:
0 1 1 0 0 1 0 0 1 1 0 0 BINARY
GRAY CODE0
BIT POSITION
GRAY11 = BINARY11 BINARY12
GRAY11 = 1 1
GRAY11 = 0
1 0
4) THE FINAL GRAY-CODE CONVERSION IS:
0 1 1 0 0 1 0 0 1 1 0 0 BINARY
GRAY CODE0
BIT POSITION
1 0 1 1 1 01 1 0 1 0
GRAY-TO-BINARY CODE CONVERSION
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THEMOST SIGNIFICANT GRAY-CODE BIT.
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TOTHE FOLLOWING EQUATION:
BINARYX = BINARYX+1
BIT POSITION
BINARY12 = BINARY13 GRAY12
BINARY12 = 0 1
BINARY12 = 1
3) REPEAT STEP 2 UNTIL COMPLETE:
4) THE FINAL BINARY CONVERSION IS:
0 1 0 0 1 1 1 0 1 0 1 0
BINARY
GRAY CODE
BIT POSITION
0 BINARY
GRAY CODE0 1 0 0 1 1 01 1 0 1 0
BINARY11 = BINARY12 GRAY11
BINARY11 = 1 0
BINARY11 = 1
GRAYX
0 1 0 1 1 1 1 0 1 0 1 0
BINARY
GRAY CODE
0
BIT POSITION
1
0 1 0 1 1 1 0 1 0 1 0
BINARY
GRAY CODE
0
BIT POSITION
1 1
0 1 1 1 0 1 0 0 1 1 0 0
A B Y = A B
0 00 11 01 1
0110
EXCLUSIVE OR TRUTH TABLE
WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTHTABLE BELOW) AND X IS THE BIT POSITION:
+ WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTHTABLE BELOW) AND X IS THE BIT POSITION:
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAYCODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUTFORMAT OF THE MAX12558 IS TWO'S-COMPLEMENT BINARY, HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODEMUST BE INVERTED TO REFLECT TRUE OFFSET BINARY FORMAT.
D11
1 1
1 1
1 1
1 1
1 0
1 1
1 0
D13 D7 D3 D0D11
1 1 0
D13 D7 D3 D0D11
1 1
0 1
D13 D7 D3 D0D11
D13 D7 D3 D0D11
D13 D7 D3 D0D11
D13 D7 D3 D0D11
D13 D7 D3 D0D11
Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion
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by the time required to charge the capacitors at REF_P,REF_N, and COM_. In internal reference mode andbuffered external reference mode the wake-up time istypically 10ms. When operating in the unbuffered exter-nal reference mode the wake-up time is dependent onthe external reference drivers.
Applications InformationUsing Transformer Coupling
In general, the MAX12558 provides better SFDR andTHD with fully differential input signals than single-ended input drive, especially for input frequenciesabove 125MHz. In differential input mode, even-orderharmonics are lower as both inputs are balanced, andeach of the ADC inputs only requires half the signalswing compared to single-ended input mode.
An RF transformer (Figure 9) provides an excellentsolution to convert a single-ended input source signalto a fully differential signal, required by the MAX12558for optimum performance. Connecting the center tap ofthe transformer to COM provides a VDD / 2 DC levelshift to the input. Although a 1:1 transformer is shown, astep-up transformer can be selected to reduce thedrive requirements. A reduced signal swing from theinput driver, such as an op amp, can also improve theoverall distortion. The configuration of Figure 9 is goodfor frequencies up to Nyquist (fCLK / 2).
The circuit of Figure 10 converts a single-ended inputsignal to fully differential just as Figure 9. However,Figure 10 utilizes an additional transformer to improvethe common-mode rejection allowing high-frequencysignals beyond the Nyquist frequency. A set of 75Ωand 110Ω termination resistors provide an equivalent50Ω termination to the signal source. The second set oftermination resistors connects to COM_ providing thecorrect input common-mode voltage. Two 0Ω resistorsin series with the analog inputs allow high-IF input fre-quencies. These 0Ω resistors can be replaced with low-value resistors to limit the input bandwidth.
Dual, 80Msps, 14-Bit, IF/Baseband ADC
MAX125581
5
3
6
2
4
N.C. N.C.
VIN
0.1µF
T1
MINI-CIRCUITSADT1-1WT
24.9Ω
24.9Ω49.9Ω0.5%
49.9Ω0.5%
5.6pF
5.6pF
0.1µF
IN_P
COM_
IN_N
Figure 9. Transformer-Coupled Input Drive for Input FrequenciesUp to Nyquist
1
5
3
6
2
4
N.C.
VIN
0.1µF
T1
MINI-CIRCUITSADT1-1WT
CIN
RIN
RIN
CIN
IN_P
COM_
IN_N
*0Ω RESISTORS CAN BE REPLACED WITHLOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.
N.C.
1
5
3
6
2
4
N.C.
T2
MINI-CIRCUITSADT1-1WT
N.C.
75Ω0.5%
75Ω0.5%
110Ω0.5%
110Ω0.5%
0.1µF
0Ω*
0Ω*
MAX12558
Figure 10. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
22 ______________________________________________________________________________________
The input network in Figure 10 can be modified to enhancethe frequency-range-specific AC performance of theMAX12558 by simply replacing the input capacitance witha series network of resistor (RIN) and capacitor (CIN).Table 4 displays a selection of resistors and capacitorsthat are recommended to help improve the alreadyexcellent performance of this ADC for specific applica-tions requiring only a certain range of input frequencies.
Single-Ended AC-Coupled Input SignalFigure 11 shows an AC-coupled, single-ended inputapplication. The MAX4108 provides high speed, highbandwidth, low noise, and low distortion to maintain theinput signal integrity.
Buffered External Reference DrivesMultiple ADCs
The buffered external reference mode allows for morecontrol over the MAX12558 reference voltage andallows multiple converters to use a common reference.The REFIN input impedance is > 50MΩ.
Figure 12 shows the MAX6029 precision 2.048V bandgapreference used as a common reference for multiple con-verters. The 2.048V output of the MAX6029 passesthrough a single-pole 10Hz LP filter to the MAX4230.
The MAX4250 buffers the 2.048V reference and pro-vides additional 10Hz LP filtering before its output isapplied to the REFIN input of the MAX12558.
Unbuffered External Reference DrivesMultiple ADCs
The unbuffered external reference mode allows for pre-cise control over the MAX12558 reference and allowsmultiple converters to use a common reference.Connecting REFIN to GND disables the internal refer-ence, allowing REF_P, REF_N, and COM_ to be drivendirectly by a set of external reference sources.
Figure 13 uses a MAX6029 precision 3.000V bandgapreference as a common reference for multiple convert-ers. A seven-component resistive divider chain followsthe MAX6029 voltage reference. The 0.47µF capacitoralong this chain creates a 10Hz LP fi lter. ThreeMAX4230 amplifiers buffer taps along this resistorchain providing 2.413V, 1.647V, and 0.880V to theMAX12558 REF_P, REF_N, and COM_ reference inputs.The feedback around the MAX4230 op amps providesadditional 10Hz LP filtering. Reference voltages 2.413Vand 0.880V set the full-scale analog input range for theconverter to ±1.022V (±[VREF_P - VREF_N] x 2/3).
Note that one single power supply for all active circuitcomponents removes any concern regarding power-supply sequencing when powering up or down.
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______________________________________________________________________________________ 23
MAX12558
MAX4108
0.1µF
0.1µF
0Ω
5.6pF
IN_P
COM_
IN_N
100Ω
100Ω
VIN
24.9Ω
24.9Ω
5.6pF
Figure 11. Single-Ended, AC-Coupled Input Drive
INPUTFREQUENCY
RANGE
CINCOMPONENT
VALUES
RINCOMPONENT
VALUES
< 10MHz 12pF to 22pF 0Ω10MHz to 125MHz 12pF 50Ω> 125MHz 5.6pF 0Ω
Table 4. Component Selection toEnhance the Frequency-Range-SpecificAC Performance
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24 ______________________________________________________________________________________
MAX4230
0.1µF
1µF
5
2
3
4
1
1
5
2
REFIN
VDD
GND
0.1µF
47Ω
3.3V
2.048V
16.2kΩ
REFOUT0.1µF
REF_P
REF_N
COM_
0.1µF
0.1µF
0.1µF
2.2µF0.1µF
3.3V
1.47kΩ
300µF6V
NOTE: ONE FRONT-END REFERENCE CIRCUITCAN SOURCE UP TO 15mA AND SINK UP TO30mA OF OUTPUT CURRENT.
10µF 0.1µF
REFIN
VDD
GNDREFOUT
0.1µF
REF_P
REF_N
COM_
0.1µF
0.1µF
0.1µF
2.2µF0.1µF
10µF 0.1µF
MAX12558
MAX6029(EUK21)
MAX12558
Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference
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______________________________________________________________________________________ 25
MAX12558
MAX4230
MAX6029(EUK30)
0.1µF 15
2
0.47µF 10µF6V
47Ω
1.47kΩ
2.413V
3V
4
1
3330µF6V
MAX4230
10µF6V
47Ω
1.47kΩ
1.647V
4
1
3330µF6V
MAX4230
10µF6V
47Ω
1.47kΩ
0.880V
4
1
3330µF6V
REF_P
REF_N
COM_
VDD
GNDREFIN
3.3V
3.3V
REFOUT
0.1µF0.1µF
0.1µF
10µF
0.1µF
2.2µF0.1µF
20kΩ1%
20kΩ1%
20kΩ1%
20kΩ1%
20kΩ1%
52.3kΩ1%
52.3kΩ1%
0.1µF
MAX12558
REF_P
REF_N
COM_
VDD
GNDREFIN
REFOUT
0.1µF0.1µF
0.1µF
10µF
0.1µF
2.2µF0.1µF
0.1µF
Figure 13. External Unbuffered Reference Driving Multiple ADCs
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26 ______________________________________________________________________________________
Grounding, Bypassing, and Board Layout
The MAX12558 requires high-speed board layoutdesign techniques. Refer to the MAX12558 EV kit datasheet for a board layout reference. Locate all bypasscapacitors as close to the device as possible, prefer-ably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD toGND with a 220µF ceramic capacitor in parallel with atleast one 10µF, one 4.7µF, and one 0.1µF ceramiccapacitor. Bypass OVDD to GND with a 220µF ceramiccapacitor in parallel with at least one 10µF, one 4.7µF,and one 0.1µF ceramic capacitor. High-frequencybypassing/decoupling capacitors should be located asclose as possible to the converter supply pins.
Multilayer boards with ample ground and power planesproduce the highest level of signal integrity. All groundsand the exposed backside paddle of the MAX12558must be connected to the same ground plane. TheMAX12558 relies on the exposed backside paddle con-nection for a low-inductance ground connection. Isolatethe ground plane from any noisy digital system groundplanes such as a DSP or output buffer ground.
Route high-speed digital signal traces away from thesensitive analog traces. Keep all signal lines short andfree of 90° turns.
Ensure that the differential, analog input network layoutis symmetric and that all parasitic components are bal-anced equally. Refer to the MAX12558 EV kit datasheet for an example of symmetric input layout.
Parameter DefinitionsIntegral Nonlinearity (INL)
INL is the deviation of the values on an actual transferfunction from a straight line. For the MAX12558, thisstraight line is between the endpoints of the transferfunction, once offset and gain errors have been nullified.INL deviations are measured at every step of the transferfunction and the worst-case deviation is reported in theElectrical Characteristics table.
Differential Nonlinearity (DNL)DNL is the difference between an actual step width andthe ideal value of 1 LSB. A DNL error specification ofless than 1 LSB guarantees no missing codes and amonotonic transfer function. For the MAX12558, DNLdeviations are measured at every step of the transferfunction and the worst-case deviation is reported in theElectrical Characteristics table.
Offset ErrorOffset error is a figure of merit that indicates how wellthe actual transfer function matches the ideal transferfunction at a single point. Ideally the midscaleMAX12558 transition occurs at 0.5 LSB above mid-scale. The offset error is the amount of deviationbetween the measured midscale transition point andthe ideal midscale transition point.
Gain ErrorGain error is a figure of merit that indicates how well theslope of the actual transfer function matches the slope ofthe ideal transfer function. The slope of the actual transferfunction is measured between two data points: positivefull scale and negative full scale. Ideally, the positive full-scale MAX12558 transition occurs at 1.5 LSBs below pos-itive full scale, and the negative full-scale transitionoccurs at 0.5 LSB above negative full scale. The gainerror is the difference of the measured transition pointsminus the difference of the ideal transition points.
Small-Signal Noise Floor (SSNF)SSNF is the integrated noise and distortion power in theNyquist band for small-signal inputs. The DC offset isexcluded from this noise calculation. For this converter,a small signal is defined as a single tone with a -35dBFSamplitude. This parameter captures the thermal andquantization noise characteristics of the data converterand can be used to help calculate the overall noise fig-ure of a digital receiver signal path.
Signal-to-Noise Ratio (SNR)For a waveform perfectly reconstructed from digitalsamples, the theoretical maximum SNR is the ratio ofthe full-scale analog input (RMS value) to the RMSquantization error (residual error). The ideal, theoreticalminimum analog-to-digital noise is caused by quantiza-tion error only and results directly from the ADC’s reso-lution (N bits):
SNR[max] = 6.02 × N + 1.76
In reality, there are other noise sources besides quanti-zation noise: thermal noise, reference noise, clock jitter,etc. SNR is computed by taking the ratio of the RMSsignal to the RMS noise. RMS noise includes all spec-tral components to the Nyquist frequency excluding thefundamental, the first six harmonics (HD2 throughHD7), and the DC offset.
SNR = 20 x log (SIGNALRMS / NOISERMS)
Signal-to-Noise Plus Distortion (SINAD)SINAD is computed by taking the ratio of the RMS sig-nal to the RMS noise plus distortion. RMS noise plusdistortion includes all spectral components to theNyquist frequency excluding the fundamental and theDC offset.
Total Harmonic Distortion (THD)THD is the ratio of the RMS sum of the first six harmon-ics of the input signal to the fundamental itself. This isexpressed as:
where V1 is the fundamental amplitude, and V2 throughV7 are the amplitudes of the 2nd- through 7th-orderharmonics (HD2 through HD7).
Spurious-Free Dynamic Range (SFDR)SFDR is the ratio expressed in decibels of the RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next largest spuriouscomponent, excluding DC offset.
3rd-Order Intermodulation (IM3)IM3 is the power of the 3rd-order intermodulation prod-uct relative to the input power of either of the input tonesfIN1 and fIN2. The individual input tone power levels areset to -7dBFS for the MAX12558. The 3rd-order inter-modulation products are 2 x fIN1 - fIN2 and 2 x fIN2 - fIN1.
Aperture JitterFigure 14 shows the aperture jitter (tAJ), which is thesample-to-sample variation in the aperture delay.
Aperture DelayAperture delay (tAD) is the time defined between therising edge of the sampling clock and the instant whenan actual sample is taken (Figure 14).
Full-Power BandwidthA large -0.2dBFS analog input signal is applied to anADC and the input frequency is swept up to the pointwhere the amplitude of the digitized conversion resulthas decreased by -3dB. This point is defined as thefull-power input bandwidth frequency.
Output Noise (nOUT)The output noise (nOUT) parameter is similar to thermalplus quantization noise and is an indication of the con-verter’s overall noise performance.
No fundamental input tone is used to test for nOUT.IN_P, IN_N, and COM_ are connected together and
1024k data points are collected. nOUT is computed bytaking the RMS value of the collected data points afterthe mean is removed.
Overdrive Recovery TimeOverdrive recovery time is the time required for theADC to recover from an input transient that exceeds thefull-scale limits. The MAX12558 specifies overdriverecovery time using an input transient that exceeds thefull-scale limits by ±10%. The MAX12558 requires oneclock cycle to recover from the overdrive condition.
CrosstalkCrosstalk indicates how well each channel is isolatedfrom the other channel. In case of the MAX12558,crosstalk specifies the coupling onto one channelbeing driven by a (-0.5dBFS) signal when the adjacentinterfering channel is driven by a full-scale signal.Measurement includes all spurs resulting from bothdirect coupling and mixing components.
Gain MatchingGain matching is a figure of merit that indicates howwell the gains between the two channels are matchedto each other. The same input signal is applied to bothchannels and the maximum deviation in gain is report-ed (typically in dB) as gain matching.
Offset MatchingLike gain matching, offset matching is a figure of meritthat indicates how well the offsets between the two chan-nels are matched to each other. The same input signal isapplied to both channels and the maximum deviation inoffset is reported (typically in %FSR) as offset matching.
THDV V V V V V
V log
= ×
+ + + + +⎛
⎝
⎜⎜
⎞
⎠
⎟⎟
20 22
32
42
52
62
72
1
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Dual, 80Msps, 14-Bit, IF/Baseband ADC
______________________________________________________________________________________ 27
tAD
tAJ
T/H TRACKHOLD HOLD
CLKN
CLKP
ANALOGINPUT
SAMPLEDDATA
Figure 14. T/H Aperture Timing
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Dual, 80Msps, 14-Bit, IF/Baseband ADC
28 ______________________________________________________________________________________
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4142434445 3738394046
21
22
23
24
25
26
27
28
29
30
THIN QFN
TOP VIEW
3536
D2B
D1B
D0B
OVDD
VDD
VDD
VDD
VDD
DIV4
DIV2
18
19
20 CLKP
CLKN
DIFFCLK/SECLK
EXPOSED PADDLE (GND)
31 D3B
4748495051
65432 109871 1211 151413 1716
32
33 D5B
D4B
34 D6B
D2A
D1A
D0A
DAV
OVDD
DORB
D13B
D12B
D11B
D10B
D9B
D8B
D7B
D3A
D5A
D4A
D6A
62
61
60
59
58
57
56
55
54
53
67
66
65
64
63
52
68
REFB
P
REFB
N
GND
REFA
N
REFA
P
COM
A
INBP
INBNGN
D
GND
COM
B
GND
GND
INAN
INAP
GND
GND
MAX12558
D12A
D13A
DORA
OVDD
VDD
VDD
VDD
G/T
PD
SHREF
REFOUT
REFIN
D11A
D8A
D9A
D10A
D7A
Pin Configuration
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Dual, 80Msps, 14-Bit, IF/Baseband ADC
______________________________________________________________________________________ 29
Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)
68L
QFN
TH
IN.E
PS
PACKAGE OUTLINE
21-0142 21
D
68L THIN QFN, 10x10x0.8mm
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Dual, 80Msps, 14-Bit, IF/Baseband ADC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Heaney
Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)
MA
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PACKAGE OUTLINE
21-0142 22
D
68L THIN QFN, 10x10x0.8mm