13bec093 experiment 8
TRANSCRIPT
8/19/2019 13BEC093 Experiment 8
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Experiment 8Code-
module PIPO (in, cin, out, clk);
input [3:0]in;
input cin;output out, clk;
reg [3:0]out;
clock (cin, clk);
always@(posedge clk)
out<=in;
endmodule
module PISO (in2, out2, s, reset2, clkin2, clk2);
input reset2, clkin2, s;
input [3:0]in2;
reg [3:0]temp2;
output clk2;
output out2;
reg out2;clock(clkin2, clk2);
always@(posedge clk2)
if (reset2==1)
temp2=4'b0000;
else if(s==0)
temp2<=in2;
else if(s==1)
begin
out2=temp2[0];
temp2[0]=temp2[1];
temp2[1]=temp2[2];
temp2[2]=temp2[3];
end
endmodule
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module SIPO (in1, out1, reset1, clkin1, clk1);
input in1, reset1, clkin1;
reg [3:0]temp1;
output clk1;
output out1;
wire [3:0]out1;clock(clkin1, clk1);
always@(posedge clk1)
if (reset1==1)
temp1=4'b0000;
else
begin
temp1[0]<=in1;temp1[1]<=temp1[0];
temp1[2]<=temp1[1];
temp1[3]<=temp1[2];
end
assign out1 = temp1;
endmodule
module SISO(in0, out0, reset0, clkin0, clk0);
input in0, reset0, clkin0;
reg temp[3:0];
output clk0, out0;
reg out0;
clock(clkin0, clk0);
always@(posedge clk0)if(reset0==1)
out0=1'b0;
else
begin
temp[0]<=in0;
temp[1]<=temp[0];
temp[2]<=temp[1];temp[3]<=temp[2];
out0<=temp[3];
8/19/2019 13BEC093 Experiment 8
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end
endmodule
module clock (c, p);
input c;
output p;reg p;
reg [31:0] t=0;
parameter sys=50000000;
parameter req=1;
parameter factor=sys/req;
always@(posedge c)begin
if(t<factor-1)
t<=t+1'b1;
else
t<=0;
end
always@(t)if(t<factor/2)
p=1'b1;
else
p=1'b0;
endmodule
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RTL View –
PIPO
PISO
SIPO
SISO
8/19/2019 13BEC093 Experiment 8
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CLOCK