12 md virtex 6 overview
TRANSCRIPT
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Copyright 2009 XilinxMarch 22, 2009
Virtex-6 FPGA Extended OverviewXilinx Product Marketing
Wednesday, April 22, 2009
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Copyright 2009 Xilinx
Agenda
Xilinx Introduction Virtex-6 Introduction
Extending Leadership from 65nm to 40nm
Power
Lowest ever!
Performance Highlights
Highest FPGA performance in the industry!
Cost Reduction
Reducing device cost and more
Virtex-6 Feature Advancements
Logic, Memory, DSPFamily Table
Wednesday, April 22, 2009
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Copyright 2009 Xilinx
2000+ Patents
Innovation at Xilinx
Xilinx Patent Hall
Pioneer of the fabless model
Inventor of the FPGA
First to 180nm, 150nm, 130nm,90nm and 65nm
Industrys first 65 nm FPGAs
Shipping 98% of high-end 65nmproduction FPGAs in the world
Next-generation 40/45nm FPGAs
Up to 760K logic density
More than 38Mbit of BlockRAM
2,000 DSP slices
Up to 64 GTH transceivers runningat up to 11.2 Gbps
PCI Express-compliant hard blocks
Dedicated DDR3 memory controllers
Wednesday, April 22, 2009
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Product Demands Are Increasing
Differentiate orDie
Fickle MarketDemands
Shorter Life Cycle
AcceleratedTime to Market
SpiralingComplexity
Capped EngineeringBudgets
Xilinx Confidential Internal Unpublished Work Copyright 2009 Xilinx
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Product Demands Are Increasing
ProgrammableImperative!
Differentiate orDie
Fickle MarketDemands
Shorter Life Cycle
AcceleratedTime to Market
SpiralingComplexity
Capped EngineeringBudgets
Xilinx Confidential Internal Unpublished Work Copyright 2009 Xilinx
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What it Means to Designers
Do more with less
Reduce risk profile
Focus on core competencies
Avoid big bets onASIC design starts
Improve engineering productivity
Differentiate or die
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6
Continued Rise of ASIC/ASSP
Development Costs
Source: Xilinx, Venture Capital Insights
Development Costs ($M) Minimum Market Size ($M)
Process Nodes (nm)
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6
Continued Rise of ASIC/ASSP
Development Costs
Source: Xilinx, Venture Capital Insights
Development Costs ($M) Minimum Market Size ($M)
Process Nodes (nm)
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Targeted Design PlatformsEnabling Customers to Do More, Faster
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Targeted Design PlatformsEnabling Customers to Do More, Faster
Virtex SpartanBase IP, ISE program, base boardsBase Platform
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Targeted Design PlatformsEnabling Customers to Do More, Faster
Virtex SpartanBase IP, ISE program, base boards
Embedded DSP ConnectivityDomain IP, Domain tools,
FMC daughter cards
Base Platform
Domain-Specific
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Targeted Design PlatformsEnabling Customers to Do More, Faster
Virtex SpartanBase IP, ISE program, base boards
Embedded DSP ConnectivityDomain IP, Domain tools,
FMC daughter cards
Communication Video AVBMarket specific IP, custom tools, custom boards
Base Platform
Domain-Specific
Market-Specific
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Targeted Design PlatformsEnabling Customers to Do More, Faster
Focus on Differentiation
Virtex SpartanBase IP, ISE program, base boards
Embedded DSP ConnectivityDomain IP, Domain tools,
FMC daughter cards
Communication Video AVBMarket specific IP, custom tools, custom boards
Base Platform
Domain-Specific
Market-Specific
Customer
Design
Wednesday, April 22, 2009
Xili S Wid R
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Copyright 2009 Xilinx
Xilinx Serves a Wide Range
of Markets
Wednesday, April 22, 2009
Xili S Wid R
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Copyright 2009 Xilinx
Xilinx Serves a Wide Range
of Markets
Surveillance
SpaceAerospaceand Defense
Infrastructure Wireless
Communications
Infotainment
InstrumentationAutomotive
Displays
HandheldsConsumer
Surveillance
Test and MeasurementIndustrial Scientific
and Medical
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Digital Convergence Drives Demand
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Digital Convergence Drives Demand
In-the-Hand (CoolRunner-II) Cost & size are premium Power is key Shortest time-in-market
The Core Infrastructure (Virtex) Performance & capability
are premium Power & cost constrained Longer time-in-market
The Expanding Edge (Spartan) Cost & flexibility are key Moderate Performance Shorter time-in-market
Voice
Data
Video
Wednesday, April 22, 2009
Introducing
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D879http://images.google.com/imgres?imgurl=http://www.wishlist.com.au/images/Products/MK01/Product_L.jpg&imgrefurl=http://www.wishlist.com.au/Product/ProductDetail.asp%253FSKUID%253D113249%2526CHID%253D2436%2526PCHID%253D&h=250&w=220&sz=10&tbnid=FVr15ePQ2cIJ:&tbnh=106&tbnw=93&hl=en&start=136&prev=/images%253Fq%253Dset-top%252Bbox%2526start%253D120%2526svnum%253D10%2526hl%253Den%2526lr%253D%2526sa%253DN%2526biw%253D879http://images.google.com/imgres?imgurl=http://www.wishlist.com.au/images/Products/MK01/Product_L.jpg&imgrefurl=http://www.wishlist.com.au/Product/ProductDetail.asp%253FSKUID%253D113249%2526CHID%253D2436%2526PCHID%253D&h=250&w=220&sz=10&tbnid=FVr15ePQ2cIJ:&tbnh=106&tbnw=93&hl=en&start=136&prev=/images%253Fq%253Dset-top%252Bbox%2526start%253D120%2526svnum%253D10%2526hl%253Den%2526lr%253D%2526sa%253DN%2526biw%253D879http://images.google.com/imgres?imgurl=http://images.tigerdirect.com/itemDetails/G126-1048/G126-1048-out4-hl.jpg&imgrefurl=http://www.tigerdirect.com/applications/SearchTools/item-details.asp%253FEdpNo%253D1209329%2526CatId%253D0&h=313&w=400&sz=132&hl=en&start=38&tbnid=5zddo2ZKKjP17M:&tbnh=97&tbnw=124&prev=/images%253Fq%253Dsecurity%252BMonitor%2526start%253D20%2526ndsp%253D20%2526svnum%253D10%2526hl%253Den%2526lr%253D%2526sa%253DNhttp://images.google.com/imgres?imgurl=http://images.tigerdirect.com/itemDetails/G126-1048/G126-1048-out4-hl.jpg&imgrefurl=http://www.tigerdirect.com/applications/SearchTools/item-details.asp%253FEdpNo%253D1209329%2526CatId%253D0&h=313&w=400&sz=132&hl=en&start=38&tbnid=5zddo2ZKKjP17M:&tbnh=97&tbnw=124&prev=/images%253Fq%253Dsecurity%252BMonitor%2526start%253D20%2526ndsp%253D20%2526svnum%253D10%2526hl%253Den%2526lr%253D%2526sa%253DN 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Introducing
Virtex-6 and Spartan-6 FPGA Families
Breakthrough performance, lower power, and lower costpush programmability beyond the tipping point
Up to 60% lower system cost
Up to 65%power reduction
Up to 50% development time reduction
Over1Tbps IO bandwidth
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Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
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Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
BlockRAM
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Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
DSP Slices
BlockRAM
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Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
DSP Slices
BlockRAM
High-performance Clocking
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Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
DSP Slices
BlockRAM
Parallel I/O
High-performance Clocking
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Copyright 2009 Xilinx
Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
DSP Slices
BlockRAM
HSS Transceivers*
Parallel I/O
High-performance Clocking
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Copyright 2009 Xilinx
Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
DSP Slices
BlockRAM
HSS Transceivers*
Parallel I/O
PCIe Interface
High-performance Clocking
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Copyright 2009 Xilinx
Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
DSP Slices
BlockRAM
HSS Transceivers*
Parallel I/OFIFO Logic
PCIe Interface
High-performance Clocking
Wednesday, April 22, 2009
A hit t Ali t
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Copyright 2009 Xilinx
Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
DSP Slices
BlockRAM
HSS Transceivers*
Parallel I/OFIFO Logic
Tri-mode EMAC
PCIe Interface
High-performance Clocking
Wednesday, April 22, 2009
A hit t Ali t
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Copyright 2009 Xilinx
Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
LUT-6 CLB
DSP Slices
BlockRAM
HSS Transceivers*
Parallel I/OFIFO Logic
System Monitor
Tri-mode EMAC
PCIe Interface
High-performance Clocking
Wednesday, April 22, 2009
A hit t Ali t
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Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
Hardened Memory Controllers
LUT-6 CLB
DSP Slices
BlockRAM
HSS Transceivers*
Parallel I/OFIFO Logic
System Monitor
Tri-mode EMAC
PCIe Interface
High-performance Clocking
Wednesday, April 22, 2009
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Architecture Alignment
Virtex-6 FPGAs Spartan-6 FPGAs
150KLogic Cell
Device
760KLogic Cell
Device
Common Resources
*Optimized for target application in each family
3.3 Volt compatible I/O
Hardened Memory Controllers
LUT-6 CLB
DSP Slices
BlockRAM
HSS Transceivers*
Parallel I/OFIFO Logic
System Monitor
Tri-mode EMAC
PCIe Interface
High-performance Clocking
Wednesday, April 22, 2009
Addressing the Broad Range of
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g g
Technical Requirements
MarketS
ize
Application Market Segments + 100s More
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Addressing the Broad Range of
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Technical Requirements
MarketS
ize
Application Market Segments + 100s More
Spartan-6 LX
Lowest costlogic + DSP
Lowest logic +high-speed serial
Spartan-6 LXT
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Addressing the Broad Range of
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Technical Requirements
MarketS
ize
Application Market Segments + 100s More
Spartan-6 LX
Lowest costlogic + DSP
Lowest logic +high-speed serial
Spartan-6 LXT
High logic density +serial connectivity
Virtex-6 LXT
DSP + logic +serial connectivity
Virtex-6 SXT
Ultra high-speed serialconnectivity + logic
Virtex-6 HXT
Wednesday, April 22, 2009
Addressing the Broad Range of
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Technical Requirements
MarketS
ize
Application Market Segments + 100s More
Spartan-6 LX
Lowest costlogic + DSP
Lowest logic +high-speed serial
Spartan-6 LXT
High logic density +serial connectivity
Virtex-6 LXT
DSP + logic +serial connectivity
Virtex-6 SXT
Ultra high-speed serialconnectivity + logic
Virtex-6 HXT
Wednesday, April 22, 2009
Agenda
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Agenda
Xilinx Introduction
Virtex-6 Introduction
Extending Leadership from 65nm to 40nm
Power
Lowest ever!
Performance Highlights
Highest FPGA performance in the industry!
Cost Reduction
Reducing device cost and more
Virtex-6 Feature Advancements
Logic, Memory, DSPFamily Table
Wednesday, April 22, 2009
What Designers Asked For
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What Designers Asked For
Higher System Performance More design margin to simplify designs
Higher integrated functionality
Lower System Cost
Reduce BOM
Implement my design in a smaller device & lower speed-grade Lower Power
Help me meet my power budgets
Eliminate heat sinks & fans
Prevent thermal runaway
Shorter Design Cycle
Faster timing closure
Reduce my design teams learning curve
Help me cut down my verification times
Wednesday, April 22, 2009
What is Virtex-6?
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High Performance, Low Power on 40nm Process
Improved transistor mobility forswitching speed increase SiGe implant
Strained Si
Third generation triple-oxidetechnology reduces overall power
Immersion lithography improvesprinting resolution at minimumgeometry
Wednesday, April 22, 2009
VirtexProduct & Process Evolution
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Copyright 2009 XilinxVirtex-6 Base Platform 16
Virtex Product & Process Evolution
Delivering Balanced Performance, Power, and Cost
Virtex
Virtex-E
Virtex-II
Virtex-II Pro
Virtex-4
Virtex-5
220-nm
180-nm
150-nm
40-nm
65-nm
90-nm
130-nm
Virtex-6
Wednesday, April 22, 2009
Agenda
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Agenda
Xilinx Introduction Virtex-6 Introduction
Extending Leadership from 65nm to 40nm
Power
Lowest ever!
Performance Highlights
Highest FPGA performance in the industry!
Cost Reduction
Reducing device cost and more
Virtex-6 Feature Advancements
Logic, Memory, DSPFamily Table
Wednesday, April 22, 2009
Strong Focus on Power Reduction
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Static Power Reduction Higher distribution of low leakage transistors
Dynamic Power Reduction
Reduced capacitance through device shrink
Reduced Core Voltage Devices Lower Overall Power VCCINT = 0.9V option allows power / performance tradeoff
I/O Power Improvements
Dynamic termination
System Monitor Allows sophisticated monitoring of temperature and voltage
Wednesday, April 22, 2009
Advanced Design and Process
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Power consumption is becoming a top concern for FPGA designers
Virtex FPGAs provide pre-engineered power reductions without the
need for complex external circuitry
Virtex-6 Base Platform 19 Xilinx Confidential
Wednesday, April 22, 2009
Power Focus: Architecture
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More direct routing Less capacitance
LUT6 architecture Less power than LUT4
More clock gating Reduces dynamic power
Hardened IP can save 90% of power
Gigabit Transceivers, PCI Express, EMAC DSP, BRAM / FIFO
Automatic power savings for most applications
Wednesday, April 22, 2009
Reducing Static Power
with Optimized Performance
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Copyright 2009 Xilinx
with Optimized Performance
More transistor options in the Virtex-6 40nm process
Virtex-6 blocks use fewer high-leakage transistors
Still achieves much higher performance
Highest Leakage (Min channel Low VT)
Longer channel Low VTMin channel Regular VTLowest Leakage (Longer channel Regular VT)
Virtex-5 65nm block
(transistor distribution) Virtex-6 40nm block(transistor distribution)Highest Leakage (65 nm Low VT )
Lower Leakage (65 nm Regular VT)
Wednesday, April 22, 2009
Up to 50% Reduction in Core Power
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Total Power(Watts)
~50%lower
65 nm Core Static Power
65 nm Core Dynamic Power
40 nm Core Static Power
40 nm Core Dynamic Power
85
C / Typical Design
Xilinx Confidential
-30%
-35%
-20%
-24%
Virtex-6 Base Platform 22
Wednesday, April 22, 2009
- 1L Low Power Option
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-1L devices give FPGA designers the option to achieveadditional power savings
0.9V core voltage in -1L vs 1.0V core voltage for -1 devices
Minimal performance impact
26% Additional Static Power Reduction Static power varies as (VCCINT)
3
-1L VCCINT max of 0.95 vs. -1 VCCINT max of 1.05
(0.95)3 / (1.05)3 = .74 static power scale factor
20% Additional Dynamic Power Reduction Dynamic power varies as (VCCINT
2)
(0.95)2 / (1.05)2 = .80 dynamic scale factor
Wednesday, April 22, 2009
Leakage and Dynamic
Power Reduction
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Power Reduction
Each Xilinx 40nm block has targeted leakage & dynamicpower reduction
Blocks in 40nm consume significantly less power than same block in Virtex-5
56% 58% 65%75%
90%
TotalPower
Wednesday, April 22, 2009
Up to 44% Dynamic Power Reduction
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Virtex-6 TransistorVirtex-6 Interconnect
Shorter interconnect traces
Low-K Dielectricinsulating material
Small transistor = lower gate capacitance
Via
Metal PlaneL
W
source drain
polyParasitic
Capacitances
1 30% Reduction in Node Capacitance and Interconnect Length and Lower-K
Wednesday, April 22, 2009
Virtex-6 Lower SelectIO Power
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Virtex-5 & 40nm Input Power Comparison
0
5
10
15
20
25
30
35
Power(mW)
DDR21.8V
DDR31.5V
T_DCI(50%R/W
)
LowerPowerIDELAY
IDELAY High Performance Mode
Input Referenced Receiver
DCI at 1.8V
DCI at 1.5V
IDELAY Low Power Mode (65 and 40nm)
Programmable Low Power Referenced Receiver (40nm)
FPGA Input Pin (SSTL/HSTL)
DCIReferenced
Input ReceiverIDELAYBlock
FromMemoryDevice
LowPowerReference
Receiver
PotentialIOpowerreduction
40nm Power Reductions
Wednesday, April 22, 2009
Power Estimation Tools &
Power-Aware Place-and-Route
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Power-Aware Place-and-Route
Estimate power consumption in
advance
More accurate power estimator spreadsheet
Always provides power numbers for
typical & worst-case conditions
Further reduce power as needed
Option for place-and-route tools to prioritize
low power (10-15% average power savings)
Clock Gating: Selectively turn off clock nets
0/2
0/2
1/2 1/2
5/6
1/3
5/3
1/4
1/5
2/3
1/10
source pin
target pin10/5
Lowest Power Path
Predicting and saving power during the design process
Wednesday, April 22, 2009
Agenda
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Xilinx Introduction Virtex-6 Introduction
Extending Leadership from 65nm to 40nm
Power
Lowest ever!
Performance Highlights
Highest FPGA performance in the industry!
Cost Reduction
Reducing device cost and more
Virtex-6 Feature Advancements
Logic, Memory, DSPFamily Table
Wednesday, April 22, 2009
Highest Performance in the Industry
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Fabric: 15% faster than any competing FPGA
Advanced process, improved routing, faster pipelining
Serial Transceivers: >200% higher bandwidth*
Up to 36, 6.5Gpbs in LXT and SXT platforms
SelectIO Technology: 37% higher bandwidth* Enabling advanced memory interfaces, including 1066+ Mbps DDR3
Clocking: 10% faster*
Lower skew, improved jitter, faster clock trees
DSP: >200% more bandwidth vs other FPGAs
Over 2,000 enhanced DSP slices
Wednesday, April 22, 2009
Higher Performance
Benefits Everyone
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Benefits Everyone
To gain a competitive edge
To upgrade a design
To achieve greater margin
To reduce design time and effort
Wednesday, April 22, 2009
A Peak Under The Hood:Virtex-6 Performance Improvements
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p
40nm IC Technology Faster transistors with lower capacitance
Smaller transistors allowing tighter spacing
Design Innovation
Advanced logic fabric and interconnect
High-performance embedded blocks
Ethernet MAC, PCI Express, Gigabit Transceivers, BRAM, FIFO,
DSP, Clock Management
Advanced I/O and packaging
Design Tools Advanced synthesis and implementation tools
Wednesday, April 22, 2009
Virtex-6 Performance Comparison
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BlockVirtex-5
(-1, slow)
Virtex-
6
Virtex-6
(-1,
Virtex-6
(-2, mid)
Virtex-6
(-3, fast)
Virtex-5
(-3, fast)
Fabric 1 1.10-1.1 1.15 1.30 1.45 1.30
Block RAM/
FIFO
450 MHz TBD 450 MHz 500 MHz 600 MHz
SDP /
550 MHz
DSP 48E 450 MHz TBD 450 MHz 500 MHz 600 MHz 550 MHz
Global Clock 450 MHz TBD 500 MHz 550 MHz 600 MHz 550 MHz
Regional Clock 250 MHz TBD 300 MHz 450 MHz 500 MHz 300 MHz
IO: DDR3 650 Mbps TBD 800 Mbps 800Mbps 1066+Mbps 800 Mbps
IO: LVDS DDR 1.0 Gbps 1.0 1.0 Gbps 1.25 1.4 Gbps 1.25
GTX 4.25 Gbps 5 Gbps 5 Gbps 6.5 Gbps 6.5 Gbps6.5Gbps(V-5 FXT)
PCIe Gen1 Gen2 Gen2 Gen2 Gen2 Gen1
Low Power Option (0.9V)
Wednesday, April 22, 2009
Agenda
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Xilinx Introduction Virtex-6 Introduction
Extending Leadership from 65nm to 40nm
Power
Lowest ever! Performance Highlights
Highest FPGA performance in the industry!
Cost Reduction
Reducing device cost and more
Virtex-6 Feature Advancements
Logic, Memory, DSPFamily Table
Wednesday, April 22, 2009
Virtex-6 Cost Reduction in Many Areas*
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More functionality within a device More integration (MGTs, hard blocks)
Rich register mix
Reduce cost of the system or board
Reduce number of components
Lower cost components
Cost reduction from increase in
performance
Potentially fit design into slower,
less expensive speed grade device
Wednesday, April 22, 2009
Preserving Your Design InvestmentAcross Generations
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Xilinx Confidential
Save Resources & Cost Through Design Re-use
Virtex-6 supports designs based on previous-generation silicon capabilities
Programmable Programmable logic Programmable logic Programmable logic
Block RAM Block RAM Block RAM Block RAM
SelectIO pins SelectIO pins SelectIO pins SelectIO pins
Clocking Clocking Clocking Clocking
Multipliers DSP slices DSP slices DSP slices
Serial transceivers Serial transceivers Serial transceivers Serial transceivers
Ethernet MAC blocks Ethernet MAC blocks Ethernet MAC blocks
System Monitor blocks System Monitor
PCIe endpoint blocks PCIe blocks
Wednesday, April 22, 2009
EasyPath For Cost Reduction
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Further system cost reduction
30 to 75% cost reduction from standard FPGA Identical to FPGA resource and capability
Tested to the users specific design
Conversion-free
No additional engineering required (unlike ASICs or structuredASICs)
Flexible and low risk No re-qualification required
Guaranteed timing and functionality
Move easily between FPGA and EasyPath during production
Fast time to market 12 weeks to volume shipment from design handoff
Wednesday, April 22, 2009
Virtex-6 EasyPath Availability
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EasyPath Availability Guideline
ProductEasyPath
Conversion
Shipping
(-1,-2 C & I)
Shipping
(-1L C)
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T1
Q410 Q111 Q211
XC6VLX7601 Q111 Q211 Q211
XC6VSX315T Q410 Q111 Q211
XC6VSX475T1 Q111 Q211 Q211
Note 1: -2I speed grade is not offered on EP nor FPGA on V6 LX550T, LX760 & SX475T
Wednesday, April 22, 2009
Agenda
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Xilinx Introduction
Virtex-6 Introduction
Extending Leadership from 65nm to 40nm
Power
Lowest ever! Performance Highlights
Highest FPGA performance in the industry!
Cost Reduction
Reducing device cost and more
Virtex-6 Feature Advancements
Logic, Memory, DSPFamily Table
Wednesday, April 22, 2009
Virtex-6 Feature Advancements
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Highest Logic Capacity
Unprecedented Flip-Flop Offering
Fast Homogenous IOs1.4Gbps LVDS / 1066+Mbps DDR3
Enhanced DSP ProcessingPre-adder & up to 2k DSP Blocks
High Throughput / Low PowerSerial IO Capability
Large Set of Hard Embedded BlocksEthernet, PCIe Gen2, System Monitor
Highest Embedded MemoryUp to 38Mb
Abundant Low Jitter ClockingNew Clocking Buffers
Wednesday, April 22, 2009
FPGA Fabric
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Highest Logic CapacityUnprecedented Flip-Flop Offering
Fast Homogenous IOs1.4Gbps LVDS / 1066+Mbps DDR3
Enhanced DSP ProcessingPre-adder & up to 2k DSP Blocks
High Throughput / Low PowerSerial IO Capability
Large Set of Hard Embedded BlocksEthernet, PCIe Gen2, System Monitor
Highest Embedded MemoryUp to 38Mb
Abundant Low Jitter ClockingNew Clocking Buffers
Wednesday, April 22, 2009
3rd Generation ASMBLArchitecture
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Optimized FPGA feature mix forvarious applications
LXT: General Logic + Serial
SXT: Rich DSP & BRAM +Serial
HXT: Highest Bandwidth Serial
Ultimate flexibility
Change FPGA feature mix at any timeduring your design / product lifecycle
Opens new possibilities Which capabilities do you want to
emphasize in your product?
Wednesday, April 22, 2009
Optimized for Diverse Applications
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Logic
On-chip RAM
DSP CapabilitiesParallel I/Os
2009 2009
LXT SXT Future (HXT)
2010
Serial I/Os
Wednesday, April 22, 2009
Virtex-6 Logic Cell
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Ever increasing capabilities
in the Virtex logic cell
Improve performance
Improve power consumption
Reduce silicon area
Power Consumption Benefits Performance Benefits Cost Benefits
Connection to FF for second output stayswithin the LUT no external net (with driver)
Higher performance due to fastconnection to FF for second output
Tools use packing options more leading tolower number of used 6LUTs and smaller devices
Wednesday, April 22, 2009
Virtex-6 Logic Fabric
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Virtex-6 Configurable Logic Block (CLB)
Each CLB contains two slices
Each slice contains four 6-input Lookup Tables (6LUT)
Slices implement logic functions (slice_l)
Slices for memories and shift registers (slice_m)
LUT6 implements
All functions of up to 6 variables
Two functions of up to 5 or less variables each
Shift registers up to 32 stages long
Memories of 64 bits
Multiple configurations within a slice
Power Consumption Benefits Performance Benefits Cost Benefits
Shift register mode greatly reduces powerconsumption over FF implementation
Increased ratio of slice_m memoriesavailable closer to the source or target logic
Can pack logic and memory functionsmore efficiently
Wednesday, April 22, 2009
Virtex-6 Logic Capacity
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More than 2x the logic density of 65nm Even more counting the hard block functions!
More than 2x the BRAM capacity of 65nm
Nearly 2x the DSP capacity of 65nm
More than 3x the Register capacity of 65nm
>100% Increase in MGT count and
bandwidth (with HXT platform)
Power Consumption Benefits Performance Benefits Cost Benefits
Reduced number of components
Reduced number of external interfaces
More integration = faster systems Reduced number of components
Lower BOM
Smaller board area
Virte
x-6
Vir
tex
-IIP
ro
Vir
tex
-4
Vir
tex
-5
Vir
tex
-II
Wednesday, April 22, 2009
Embedded Memory
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Highest Logic CapacityUnprecedented Flip-Flop Offering
Fast Homogenous IOs1.4Gbps LVDS / 1066+Mbps DDR3
Enhanced DSP ProcessingPre-adder & up to 2k DSP Blocks
High Throughput / Low PowerSerial IO Capability
Large Set of Hard Embedded BlocksEthernet, PCIe Gen2, System Monitor
Highest Embedded MemoryUp to 38Mb
Abundant Low Jitter ClockingNew Clocking Buffers
Wednesday, April 22, 2009
BRAM/FIFO Features
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Independent read and write port widths
Multiple configurations True dual-port, single-port
Simple dual-port with
Asymmetric Read & Write Ports
Integrated cascade logic
Creates 64k x 1 from two 32k x 1 BRAMs
Byte-write enable
Enhances processor memory interfacing
Integrated optional 64-bit error correction
Integrated optional logic for fast efficient FIFOs
FIFO
Dual-Port
BRAM
Power Consumption Benefits Performance Benefits Cost Benefits
Designed for Low Static Power 9k internal split for Lower Dynamic Power
600MHz operation BRAM 600MHz operation FIFO
More BRAM for smaller component choice
Wednesday, April 22, 2009
Most On-Chip Memory
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Logic Cells
BRAM(Mbits)
Virtex-6 SXTHighest Memory Capacity Virtex-6 LXTStrong Increase inMemory-to-Logic
Wednesday, April 22, 2009
Distributed Memory
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Distributed LUT memory
64-bit blocks throughout the FPGA
Single-port, dual-port, multi-port
Can be used as 32-bit shift register
Very fast (sub-nanosecond)
Tightly coupled to logic Ideal for coefficient storage, small buffers, small
state machines
More capability than Virtex-5
32x2 per LUT with registered outputs
SRL 16x2 with registered outputs
RAM
RAM
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic RAM
Shift Register
RAM
Logic
Power Consumption Benefits Performance Benefits Cost Benefits
Short routing between LUTRAM and logicreduces power
High performance since located close to theLogic
Great efficiency: 64bit = 1.6 Logic Cells
Wednesday, April 22, 2009
More LUTRAM
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Virtex-6 Base Platform 50 Xilinx Confidential
Logic Cells
Max
DistributedRAM (Mbits)
Similar LUTRAM ratio as Virtex-5 SXTbelow 470K LCs for both LXT & SXT
Up to 8 Mbits
additionalon-chip RAM
Wednesday, April 22, 2009
External Memory IF
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Improved Performance
Higher data rates Faster logic (40 nm)
Enhanced I/O (50 ps/-3 IODELAY)
Dedicated clocking paths
Real time calibration with MMCM (PLL)
Higher effective bandwidth
Reordering controller (DDR3/DDR2)
Improved Functionality
DDR3 DIMM write levelingMemory Interface Speed
DDR2 SDRAM 800 Mbps*
DDR3 SDRAM 1066+ Mbps*
QDR II+ 400 MHz*
RLDRAM II 500 MHz*
*All frequencies quoted for Virtex-6 are for fastest speed grades. Mid- and slow-speed grade performance is TBD
Wednesday, April 22, 2009
Advanced Clocking
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Highest Logic CapacityUnprecedented Flip-Flop Offering
Fast Homogenous IOs1.4Gbps LVDS / 1066+Mbps DDR3
Enhanced DSP ProcessingPre-adder & up to 2k DSP Blocks
High Throughput / Low PowerSerial IO Capability
Large Set of Hard Embedded BlocksEthernet, PCIe Gen2, System Monitor
Highest Embedded MemoryUp to 38Mb
Abundant Low Jitter ClockingNew Clocking Buffers
Wednesday, April 22, 2009
Introducing MMCM
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MMCM = Mixed Mode Clock Managers
PLL-based architecture
Lowest jitter clocking
Support all popular modes from Virtex-5 DCM
Fine grain phase shifting
Clock de-skew
CMT = Clock Management Tile
2 MMCM per CMT
Dedicated interconnections between MMCMs
MMCM
MMCM
CMT
Power Consumption Benefits Performance Benefits Cost Benefits
Low Static Power Architecture Lower Jitter Clocking than Virtex-5 PLL Does not require separate power supplies
Wednesday, April 22, 2009
Most Advanced Clocking
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New Performance Paths
Directly connect to I/O & regionalclocks
Lower skew for non-GCLK sources
Differential regional clocks
New Mid-Point GCLK Buffering
Lower skew between columns Leveraged by SW tools
600MHz differential global clocks
Up to 18 Mixed-Mode
Clock Managers (MMCMs)
Power Consumption Benefits Performance Benefits Cost Benefits
Lowest Power clock generation and Network 600MHz Global Clock 500MHz regional
Remove the need for external components& simpler board designs for fast Interfaces
Wednesday, April 22, 2009
Select IO
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Highest Logic CapacityUnprecedented Flip-Flop Offering
Fast Homogenous IOs1.4Gbps LVDS / 1066+Mbps DDR3
Enhanced DSP ProcessingPre-adder & up to 2k DSP Blocks
High Throughput / Low PowerSerial IO Capability
Large Set of Hard Embedded BlocksEthernet, PCIe Gen2, System Monitor
Highest Embedded MemoryUp to 38Mb
Abundant Low Jitter ClockingNew Clocking Buffers
Wednesday, April 22, 2009
Virtex-6 I/Os
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Extended performance
1.4 Gbps LVDS for DDR Supports 1066+ Mbps DDR3
Powerful parallel I/O capabilities 1.0 to 2.5 V operation
ChipSync technology Programmable I/O Delay
XCITE DCI termination
Support for many standards SFI-4, HSTL, SSTL, differential
HSTL/SSTL, LVCMOS
Power Consumption Benefits Performance Benefits Cost Benefits
DCI @ 1.5V IDELAY in low power mode Low power referenced receiver
Homogenous I/Os: high performanceinterfaces on all pins
Improved signal integrity
Easier and less expensive board designdue to homogenous I/Os and improvedsignal integrity
Wednesday, April 22, 2009
Signal Processing
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Highest Logic CapacityUnprecedented Flip-Flop Offering
Fast Homogenous IOs1.4Gbps LVDS / 1066+Mbps DDR3
Enhanced DSP ProcessingPre-adder & up to 2k DSP Blocks
High Throughput / Low PowerSerial IO Capability
Large Set of Hard Embedded BlocksEthernet, PCIe Gen2, System Monitor
Highest Embedded MemoryUp to 38Mb
Abundant Low Jitter ClockingNew Clocking Buffers
Wednesday, April 22, 2009
Higher DSP Performance
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Most advanced DSP architecture
New optional pre-adder for symmetric filters
25x18 multiplier
High resolution filters
Efficient floating point support
ALU-like second stage enables mapping of
advanced operations Programmable op-code
SIMD support
Addition / Subtraction / Logic functions
Pattern detector
Lowest power consumption
Highest DSP slice capacity
Up to 2K DSP Slices
Wednesday, April 22, 2009
Virtex-6 DSP Slice Details
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=
X
+/-A
D
B
C
P
Power Consumption Benefits Performance Benefits Cost Benefits
Lowest power operation of any FPGA solution
1.23mW/100Mz at 38% toggle rate 600MHz operations for any DSP operation(including large filters)
~1.2 TeraMACC in a single device
Hardened pre-adder and adder cascade savessignificant logic resources Logic functions can be mapped into DSP blocks
25bit Pre-adder
25x18 Multiplier ALU-likeSecond Stage
Pattern Detector
Wednesday, April 22, 2009
The Ultimate DSP FPGA Family
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Virtex-6 LXT
Virte
x-6S
XT
Virtex
-5SX
T
Virtex-5LXT
Virtex-6 LXT Virtex-6 SXT
Right feature mix for most DSP applications:
Wireless Radio/Baseband, Video Processing, Medical Imaging
Ideal for the most advanced DSP applications:
Medical imaging, Video processing, Radar, Cryptography
Wednesday, April 22, 2009
High Speed Serial IO
Hi h t L i C it
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Highest Logic CapacityUnprecedented Flip-Flop Offering
Fast Homogenous IOs1.4Gbps LVDS / 1066+Mbps DDR3
Enhanced DSP ProcessingPre-adder & up to 2k DSP Blocks
High Throughput / Low Power
Serial IO Capability
Large Set of Hard Embedded BlocksEthernet, PCIe Gen2, System Monitor
Highest Embedded MemoryUp to 38Mb
Abundant Low Jitter ClockingNew Clocking Buffers
Wednesday, April 22, 2009
Fifth Generation of Multi-Gigabit Transceivers
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GTP Transceivers - Up to 3.2 Gbps
Making serial connectivity ubiquitous Low cost, easy to use
Featured in Spartan-6 FPGAs
GTX Transceivers - Up to 6.5 Gbps High bandwidth for connected systems
PCIe Gen2, Interlaken, CPRI, HD-SDI
Low power dissipation
Featured in Virtex-6 FPGAs
GTH Transceivers - Up to 11.2 Gbps
Supporting roll-out of 100G networks Highest performance low-power transceiver
Featured in Virtex-6 HXT* FPGAs
Providing the right multi-gigabit transceiver for the job
Wednesday, April 22, 2009
Next-Generation Serial Connectivity
Need for higher serial
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Need for higher serial
bandwidth 6.5 Gb/s in LXT & SXT
devices
HXT devices for even
higher performance
transceivers
Highly flexible clocking
Independent PLLs for TX
and RX
Power Consumption Benefits Performance Benefits Cost Benefits
Power optimized GTX
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Incr
easedInterfacePerformance
HSTL
Class I, II, IIISSTL
Class I, II, III
*Hardened endpoint core
Select IO High-Speed Serial
SingleEnded
LVTTLLVCMOS
I2CLPC
PCI33
DifferentialInterfaces
LVDSRSDS
Mini LVDS
Emerging
Interfaces
TMDSPPDS
Diff HSTLDiff SSTL
GTPSerial
Transceivers(3.2Gbps)
PCIe Gen1*1G Ethernet
XAUIDisplay Port
EPONGPON
SATA Gen1 & 2
CPRIOBSAISRIO
Aurora
PCIe* Gen 1 & 2
CEI-6Interlaken
XAUI2x XAUIGigabit
EthernetCPRI
OBSAISRIO
HD-SDIFiber Channel
GPONSATASAS
Aurora
GTXSerial
Transceivers(6.5Gbps)
SimpleInterfaces
MemoryInterfaces
10 Gigabit EOTU-4CEI-11
GTHSerial
Transceivers(11.2Gbps)
Wednesday, April 22, 2009
World-Class Support forHigh-Speed Serial Design
S
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RapidIOXAUI1 GbEAS1/2/4G FC
PCI Express
Support andServices
Protocol Packs withCharacterization &Compliance Data
Industry-wideInteroperabilityCertifications
DevelopmentBoards & kits
Pre-verified IP forAll Major Standards
Silicon for HighestPerformance &
Lowest Cost
First worldwidenetwork ofdesign labs
EasyPath forCost Reduction
SignalIntegrity
Tools
17 RocketLab Locations Worldwide
PCIe Development Kit for Virtex-5
Wednesday, April 22, 2009
Hardened Embedded Blocks
Highest Logic Capacity
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Highest Logic CapacityUnprecedented Flip-Flop Offering
Fast Homogenous IOs1.4Gbps LVDS / 1066+Mbps DDR3
Enhanced DSP ProcessingPre-adder & up to 2k DSP Blocks
High Throughput / Low Power
Serial IO Capability
Large Set of Hard Embedded BlocksEthernet, PCIe Gen2, System Monitor
Highest Embedded MemoryUp to 38Mb
Abundant Low Jitter ClockingNew Clocking Buffers
Wednesday, April 22, 2009
Hardened Protocol Support
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Built-in PCI Express
Gen1 up to 8 lanes
Gen2 up to 4 lanes
OOB signaling
Endpoint support
Root Complex (via soft IP wrapper)
Built-in Ethernet MAC
10/100/1000 TEMAC
Supports 2.5Gbps (oversampling)
Power Consumption Benefits Performance Benefits Cost Benefits
10-20x lower power than LUT basedsolution
Support PCIe Gen2 Higher performance EMAC
Saves 1000s of LUTs smaller devices
Wednesday, April 22, 2009
Virtex-6 System Monitor
Monitors external and internal analog voltages
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Monitors external and internal analog voltages
Configurable thresholds and warning levels
Results stored in configurable registers
Easy interfaces to logic fabric, or microprocessors
Provides high flexibility at runtime
Through DRP ports & microprocessor
Easy to implement and useADC
Power Consumption Benefits Performance Benefits Cost Benefits
Tightly controlled voltage regulationreduce power consumption
TUE of 1LSB: better than most systemmanagement ASSPs
No external components Cheaper power supply
Wednesday, April 22, 2009
Leverage FPGA Hard IP for Must HaveFunctionality
Clocking Flexibility
-
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Optimized Serial IOPower & Performance150Mbps to 6.5Gbps GTX
Integrated ReliabilitySystem Monitor
TL DL PHY
Enhanced Support for PCI
Express technologyIntegrated x1, x4, x8
g yPLL (precision synthesis + low jitter)
PLL
DCMPLL
Wednesday, April 22, 2009
25 Years of XilinxA Strong Partner in Tough Times
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Execution & Operational Excellence
Excellent Financial Scorecard
50%Market
Share
Cash &Investments
$1.8B
OperatingCash Flow:
$581MFinancialStability
Products & Solutions Leadership
Wednesday, April 22, 2009
Up to 750K Logic Cells with close to 1 Million fabric flip-flops
Virtex-6 LXT / SXT FPGA Highlights
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p g p p
Largest FPGA ever Up to 38 Mbits Block RAM
Memory-rich architecture
Up to 2,000 DSP slices
Unparalleled DSP performance
Up to 1,200 SelectIO pins Low-latency parallel and memory interfacing
Up to 36 6.5 Gbps serial transceivers
225 Gbps aggregate serial bandwidth in a single device
Hardened, full-featured PCI-Express technology and 10/100/1000
Mbps Ethernet MACs
Easy, high-performance protocol support that saves programmable logic
Wednesday, April 22, 2009
Virtex-6 LXT / SXT FPGAs
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Wednesday, April 22, 2009
Xilinx Engineering Services
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Enhance your competitive advantage
Allows you to focus on your unique solution
Decreases your time to market further
Reduces your engineering costs
Portfolio of services, tailored to your needs From hands-on training to full design delivery
QuickStart!: Up-front customized support
Titanium: Dedicated on-site FPGA expertise
XDS: Turn-key custom development
Successful engagements with more than 450 customers
http://www.xilinx.com/services
Wednesday, April 22, 2009
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Thank You
Wednesday, April 22, 2009