1199 james knight

7/27/2019 1199 James Knight

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CADENCE AND KNIGHTS TECHNOLOGY CONFIDENTIAL

Knigh ts Techno logy

Shrinking the Design for Manufacturing Gap-A Semiconductor Yield Management Perspective

Jim Kramer


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FEI Serves a Broad Range of Markets

4%

42%

Semiconductor

Data Storage

Research & Ind

($ Millions)

2004 Revenue

$465.7 Mill ion

2003 Revenue

$360.1 Mill ion

A proven business model:

Growth in the upturns, buoyancy in the downturns

49%

9%

42%

45%51%

jc6


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Slide 3

jc6 need pie chart for 6 months of 2003jchiafery, 8/1/2003


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The Leader in Tools for Nanotechnology

Focused Ion Beams (FIB), Scanning Electron Microscopes (SEM), Transmission ElectronMicroscopes (TEM), Laboratory, In-Fab DualBeams, Merlin , YieldManager


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FEI Tools Improve Customer Yields

Defect Analysis inDefect Analysis inlaboratories and inlaboratories and in fabsfabs

InIn--fab metrologyfab metrology


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Knights History

1987: Knights Technology founded

Excalibur (Microprobe station with CAD Navigation)

Merlin CAD Navigation and MegaLab

1994: New Products

YieldManager (in cooperation with Sematech)

1997: Knights Technology bought by Electroglas

New Products: YM-LCD, YM-Mask, LogicMap, Bondtool,

Interactive Schematic

July 16, 2003: Knights/EGsoft division acquired by FEI

New division Knights Technology


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Leader in Design-For-Manufacturing Solutions

As technology nodes shrink(130nm->90nm->65nm->45nm)

System defectswill have a larger affect thanrandom defects

Examples of system defects: Process variation Signal integrity issues Design integrity issues

This is driving the Design, Mfg and FA closer together Key design constraints fed-forward into

manufacturing and test processes Feed system defect issues back to design

Yield learning

FABFAB EDAEDA

LABLAB


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Knights Market Position/Overview

CAD - Navigation

Merlins Framework

MegaLab

LogicMap

Product Engineering WB

Failure Analysis Tools

YieldManager

SPAR

DataMining

APC

Predictive Yield

Chip Traceability

Factory

Host

IC Design

Schematic &Netlist

Layout &Verification

ATPG &Simulation

IC Manufacturing

ProcessData

Defect Data &Wafer Maps

Test &Assembly

FIB SEM DB TEM EMMI

FAB Analysis Tools

Metrology. Test, Inspection


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What is Yield Management?

Yield Management within the semiconductor industry is the

practice of collecting, managing, and analyzing all relevantprocess, equipment, metrology, defect, final test, parametric, and

bitmap data at batch, lot, wafer, die, and subdie levels to find the

source(s) contributing to a random and/or systematic relatedproblems.

Random Yield Loss- Die loss associated with particles andsurface level defects. Usually unpredictable and random in nature.

Systematic Yield Loss- Die loss associated with process and designIndused problems such as over etched, partially filled vias, exposed

contacts, etc. Usually predictable in nature (once detected).

YE = 1- ( YS + YR )


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Implementing YMS solutions to shift the Yield Curve- different strategies for dif ferent phases

Time

Yield

Phase 1Pilot

Phase 2Ramp

Phase 3Maturity

YE Product A

Product B

YE = 1- ( YS + YR )

Incremental Yield

YI

Shif t ing the Yield Curve

YS Focus YRFocus


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Why is YMS Important?

Improves Yield Ramp time

Improves Profitability

Reduces Time to Market

Improves Design for Manufacturability

Provides a metric to measure fab to fab performance

A true YMS Initiative Forces a fab to work as a Cohesive Unitand improve efficiencies


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Cummulative Revenue Gained by Increasing

Learning Rates from Current LR (0%)

0

2040

60

80

100

120

140

160

180

1 2 3 4 5 6 7 8 9 10 11 12 13

Months

Revenue($Millions

)

3% LR

5% LR

($60/die, 200 die/wafer, 20K wafers/month)

Logic

Learning Rate LR= 1 (Dn / D0) x (1/n)

YMS ROI Model- Logic


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Cummulative Revenue Gained by Increasing Learning

Rates from Current LR (0%)

0

20

40

60

80

100

120

140

160

1 2 3 4 5 6 7 8 9 10 11 12 13

Months

Revenue($Million

s)

1% LR

3% LR

($30/die, 300 die/wafer, 40,000 wafers/month)

Memory

Learning Rate LR= 1 (Dn / D0) x (1/n)

YMS ROI Model- Memory


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Equipment and Application Interfaces

SPC Process MonitoringSupervisory Control

Cell Control APC YMS

Manuf Execution Systems

Enterprise

CIM Triangle- Semiconductor

Jim Kramer, 12/28/01

Grapheq Stationworks FAbuilder Autoshell FactoryLink

Data Acquisition HSMS SECS GEM Other

SAS Cornerstone

RS1

Interlution FactoryLink

Wonderware

Cellworks

Triant

Adventa

KLA

YieldDynamics

Applied Materials PRI Brooks

Cellworks KLA

IDS HPL

Yield Dynamics

FactoryLink

Honeywell

SEMY

LabView

Knights

Data Collaboration (Running a Business)

MES (Running a Fab)

Running a Tool/Process

Monitoring

Data


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On Line SPCIdentify and Select

FABWorks/

MBX Bus

Defect Density

(Yield Manager,

Knights)Identify and Select

Off Line SPC

SystemIdentify and Select

Optional Review

StationIdentify and Select

Defect Data

EDA DatabaseIdentify and Select

APC Run 2 RunIdentify and Select

Defec

tData

Stationworks/

Kernel/EI/Tools

ToolData/MetrologyData

ToolandRecipe

ParameterChanges

APC Fault Detection(Regensburg Fault

Detection System,FDC, Oracle)

Identify and Select

Tool&MetrologyData

FaultEventMessages

FDCD

atafor

Stora

geand

Future

analy

sis

Resultsofcalulations

DefectData

ToolandM

etrologyD

ata

LotEquipmentand

MetrologyData

Outofcontrole

ventdata

FaultD

etectio

nandDefectD

ata

Fault

Dete

ctionN

otifi

catio

nandClassifi

catio

n

HistoricalToolandMetrologyDataforanalysis

APCDataforStorageandFutureanalysis

ToolandMetrologyData(maybethroughEDA

DB)

Wafer MapIdentify and Select

Param

etric

,Bin

,an

dlim

it

data

Metrology ToolsDefect

Data

New Vision APCfor Lithography

Controldata

LithoData

Fab Wide YMS Complex Data Flow Diagram


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Typical Defect Data Flow Diagram

3-

Orobot

1-

KLA

2125

KNIGHTSDB

HP 2000

Oracle

1-VIPER

4- Leica

Review

1-

Hitachi

SEM

1-

JEOL

SEM

Data

Warehouse

Oracle-HP

MES System

Test

Archive

Viewer

VMS

TAS DB

VMS

Advantest

Testers

Image DB

Oracle

SEIKO

SEM

1-Inspec8510

Klarity

Seiko Format

KLARF

Format

TCPIP

Extracts

Notes:

Orbot to KLARF conversion ScriptSeiko to KLARF conversion Script

Temp script to copy data to PAM DB

Tester file loads XY coordinate data . Knights to

normalize data during load time

Images on File Server

40 Concurrent User license-Knights

Unlimited users for images

Plan to implement Leica offline ADC

DMS System

Lot and Wafer Level

and Equipment data

TCPIP

KLARF

KLARF

KLARF

KLARF


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Automated,Intelligent,Open-Architecture,Yield Management software

System.

Enables Fab Engineers to Collect, Correlate and Analyze

Defect, Images, Review, Bitmap, and Binsort Data

YieldManager


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Wafer Map

A wafer map gives the stacked view of wafer(s) across inspectionstep(s) for defect analysis.

Features

Legend Settings

Select By Box/Die

Zoom

Chart Correlation

Image Correlation

Export To KLA / Export ForReview

Reclassify defect(s)

Repartition

Sampling Defects

Grid for Multiple Products

Defect Density Map


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Die Map

Allows the user to view the defects on wafer(s) stacked on single die / vertical / horizontal.Enables Chip zone analysis

Features

Legend

Chip Zone AnalysisCustomized DieMap

Zoom In/Out

Image Correlation


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Image Zoom In / Out

Zoom In on a Image


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Bin Map

This type of mapping offers a way of looking at a spatial distribution of

wafer sort data by bin across wafer(s) and can be used to get a graphicalview of the weight of defectivity occurrences at different wafer location.

Features

Legend Settings

Summary

Defect Overlay

Show Counts OnStacked Map

Zoom

Color Settings

Stacked Bin

Map

Single Bin Map


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- Next Generation in CAD Navigation Software Solutions.

Camelot


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The Industry Standard in CAD

Navigation

Netlist

CircuitSchematic

Layout

MicroscopeImage

Failure Analysis, DesignVerification, Low YieldAnalysis

Central Databaselinks chipdesign & FA

Layout, netlist, schematic Images with thelayout

Equipment-independentsolutions

Interfaces to variousEDA

systems (incl. Cadence,Mentor, Synopsis, Avant!)


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Multiple Traces and Crossmap

Every trace gets added as a Trace Layerin the legend window

Each trace can be assigned individualcolors & patterns

Trace property dialog displays layername with clipboard support for easycopy/paste between applications

Polygons present tab lists polygons for

the trace sorted by layer name

Trace can be filtered by layer visibility &other filter criteria set in options

Signal Name displayed as a tool tip inlegend & also the status bar when signalis traced

Option to display trace in Birds view for

quick navigation

Trace/Crossmap in context menus forquick access without changingapplication mode


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Multiple Image Overlay

Supports popular image

formats (tiff, bmp, gif,jpg,)

Overlay of multipleimages simultaneously.

Per image 3 point

alignment.

Possibility to show/hide

images

Layout transformations

(Rotate/Mirror) apply toImages also.

Replace Image retaining

alignment of previousimage.


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Interactive Schematic & Netview


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LogicMap Software Solut ion

-First Commercial ly avai lable defect correlat ion too lfor Logic Devices


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LogicMap integrates in-line defect inspection data

with a set of suspected signals and gates generated

by the scan diagnostics flow.

It is similar to memorybitmapping, but forlogicdevices.

Electrical failures are localized into a relatively small

physical trace on the die.

What is Logic Map?


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Identifies the precise circuit trace on failing chips

Overlays failing trace with in-line defect inspection data

Facilitates FA without the need for packaging or probing

Quickly determines systematic fail modes

Provides real time and statistically meaningful yield

fallout and design sensitivity data

LogicMap Features


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KLA

ESDA

1

Testers generate datalogs

for each die tested. Some

fraction of these die arefunctional enough for scan test.

Tester Generated Files Prior to simulating the failure of the dielevel datalogs in question, the datalogs

are be translated into FastScan or TetraMaxformat.

Knights

DesignDatabase

Oracle system loading

defect data and LogicMapdata for physical overlay.

LogicMap

UNIX DB

WinNT PCKnightsDefect

Overlay

2

4

3

LogicMap File Translation Process

FastScan UNIX Server

Knights

Merlin

The Knights Merlin LogicMap translatorwill convert incoming FastScan data intostandard defect data format. This is

a logical to physical translation. (Net toPoly, Poly to Klarf)

If desired custom file

exports are availablefrom each client PC.

Knights YieldManager client visualization

include wafermaps, charts, layout.

5 Data Sharing

Design Netlist

And Layout (GDS2)

Inpection

Tool

Klarf

Klarf


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Defects with product correlated hits can then be exportedback to the Merlin software for FIB navigation and de-processing.


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Legend represents# of failed die

in grid

Hot spots or areasof high fail intensity

are located.These can then besent to Merlin for

analysis

Intensity Map

LogicMap Facilitates FA


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Why we are working together?Synergy of technolog ies measurably increases

value To improve both the efficiency and accuracy of the FA flow

Utilize each companys unique strengths; Cadence diagnostic

technology in conjunction with Knights can effectively drive SEM orFIB equipment

Shorten the time to identify yield limiters

Utilize each companys unique strengths; take inline data from

Knights Yield Manager to seed the diagnostic engine to improvefault modeling accuracy and lessen runtime

Better determine sources of yield loss

Utilize each companys unique strengths; Correlate volumediagnostic data to bin-sort yield loss contributors


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Significant synergy existsHigh value in in tegrated f lows

Merlin

Defect

RevBin SortImage

BitmapParametricMES

ReviewTool

ATPGScan Vectors

Netlist

FIB , SemEquipment

Other Synergistic

Applications

Failed Nets

Encounter Diagnostics Volume

Encounter Diagnostics Precision

Diagnostics

Database

X Y

locations

Yield

Manager

FIB , SemEquipment

CadenceKnights TechnologyFEIOther companiesSynergistic opportunities

Key ToolsEquipment

ATPGScan Vectors

LogicMap

ATEData

Netlist Layout


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Potential Application #1Improv e ef f ic iency & accu racy of the FA f low

Encounter Diagnostics -PrecisionCallout of failing nets

LogicMap

Conversion to X-Y

Silicon Wafer

Merlin

Database

Equipment control

Sem & FIB

Callouts typically 80% accurate so FAprocess will be more efficient


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Potential Application #2Improve ident i f icat ion & resolut ion of y ield

l imiters

LogicMap

Failed Nets

Encounter Diagnostics - Volume

YieldManager

KLARF

Diagnostics

Database

Defect

Matches

Silicon Wafer

Sem & FIB

Low correlated X Y

Merlin

1

Pass inline data to diagnosticsengine

Inline data improvesefficiency of diagnosticsengine by limiting faultsimulationInline data can help buildmore accurate fault models(opens, bridges)

Utilize inline and

diagnostic dataCallout and inline can beanalyzed to eliminate FA incase of high correlation2


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Potential Application #3In tensi ty map high l ights d efects to d r ive FA

Failed Nets

Encounter Diagnostics

Diagnostics

Database

Silicon Wafer

Sem & FIB

Correlated X Y

LogicMapIntensity map

Merlin

Legend represents# of failed die in grid

Callouts map can guide FA processwill be more accurate


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DetailsDiagno st ic c allout l ink age

BLK T1ET

Callouts ultimately mappedto net to FA image

Callouts ultimately mappedto net to inline image


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Potential Application #4Determine top yield l imiters

Top Yield loss ComponentsCellNetInstance

Encounter Diagnostics - Volume YieldManager

Diagnostics

Database

Bin Sort data

What components are themajor source of yield loss


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Summary of Benefits

An integrated Design to Fab to FA Yield Management

initiative provides for:

Improves Design for Manufacturability thus:

Improving Yield Ramp time Reduces Time to Market

Improves Profitability

Provides a metric to measure Fab to Fab performance

A true integrated YMS Initiative Forces a Fab to work withDesign and FA as a Cohesive Unit thus improving efficiencies

1199 james knight

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