11/16/2006 wsn mote- mcu & sensor hardware 1 ecet 581 wireless sensor networks mote – mcu...

11/16/200611/16/2006 WSN Mote- MCU & Sensor HardwareWSN Mote- MCU & Sensor Hardware 11

ECET 581ECET 581

Wireless Sensor NetworksWireless Sensor Networks

Mote – MCU & Sensor HardwareMote – MCU & Sensor Hardware2 of 32 of 3

Fall 2006Fall 2006

http://www.etcs.ipfw.edu/~linhttp://www.etcs.ipfw.edu/~lin


WSN Mote & Sensor HardwareWSN Mote & Sensor Hardware

TimerTimer DMA – Direct Memory AccessDMA – Direct Memory Access JTAGJTAG USART/USCIUSART/USCI SPI – Serial Peripheral InterfaceSPI – Serial Peripheral Interface I2CI2C RF TransceiverRF Transceiver


Timers on the MSP430Timers on the MSP430

Timer_A3Timer_A3• 16-bit timer/counter with 3 16-bit timer/counter with 3

capture/compare registerscapture/compare registers• PWM outputPWM output• Interval timingInterval timing• InterruptsInterrupts

Timer_B3Timer_B3 Watch Dog TimerWatch Dog Timer


DMADMA

DMA – Direct Memory AccessDMA – Direct Memory Access Move a block of data in memory from Move a block of data in memory from

system RAM to/from a buffer without using system RAM to/from a buffer without using the CPUthe CPU

CPU bus access turned over to DMA CPU bus access turned over to DMA controllercontroller

ApplicationsApplications• Network packet routingNetwork packet routing• Audio playbackAudio playback• Streaming videoStreaming video


DMADMA

3-independent channels for DMA transfer3-independent channels for DMA transfer DMACTL0- (DMA Control Register 0) - DMAxTSELx bits: DMACTL0- (DMA Control Register 0) - DMAxTSELx bits:

triggering & data transfertriggering & data transfer DMACTL1 (DMA Control Register 1)DMACTL1 (DMA Control Register 1)

• Handle conflicts for simultaneous triggersHandle conflicts for simultaneous triggers• PrioritiesPriorities

DMAxCTL - DMA Channel Control Register DMAxCTL - DMA Channel Control Register • Single TransferSingle Transfer• Block Transfer – entire data blockBlock Transfer – entire data block• Burst-Block Transfer – allow interleave CPU and DMABurst-Block Transfer – allow interleave CPU and DMA• Repeated Single TransferRepeated Single Transfer• Repeated Block TransferRepeated Block Transfer• Repeated Burst-Block Transfer Repeated Burst-Block Transfer


MSP430 - JTAGMSP430 - JTAG JTAG (Joint Test Action Group) Flexible Printed JTAG (Joint Test Action Group) Flexible Printed

Circuit Interface Circuit Interface IEEE 1149.1 Standard Test Access Port and IEEE 1149.1 Standard Test Access Port and

Boundary-Scan Architecture - 1990 Boundary-Scan Architecture - 1990 MSP430 on-chip JTAG interfaceMSP430 on-chip JTAG interface

• 2-wire JTAG (Spy-Bi-Wire or SBW)2-wire JTAG (Spy-Bi-Wire or SBW)• 4-wire JTAG (standard)4-wire JTAG (standard)

TMS – In, signal to control the JTAG state machineTMS – In, signal to control the JTAG state machine TCK – In, JTAG clock inputTCK – In, JTAG clock input TDI – In, JTAG data input/TCLK inputTDI – In, JTAG data input/TCLK input TDO – Out, JTAG data outputTDO – Out, JTAG data output

JTAG In Circuit Debugger & ProgrammerJTAG In Circuit Debugger & Programmer• TI MSP-FET430UIF connected to a USB portTI MSP-FET430UIF connected to a USB port• TI MSP-FETP430 JTAG interface connected to the PC’s TI MSP-FETP430 JTAG interface connected to the PC’s

parallel portparallel port


MSP430 - JTAGMSP430 - JTAG

Programming Flash-based MSP430 using the JTAG interfaceProgramming Flash-based MSP430 using the JTAG interface High-level MacrosHigh-level Macros

• IR_SHIFT (8-bit instruction)IR_SHIFT (8-bit instruction) Shifts an 8-bit JTAG instruction into the JTAG instruction registerShifts an 8-bit JTAG instruction into the JTAG instruction register

• DR_SHIFT16 (16-bit data)DR_SHIFT16 (16-bit data) Shifts a 16-bit data into the JTAG data registerShifts a 16-bit data into the JTAG data register

• DR_SHIFT20 (20-bit address)DR_SHIFT20 (20-bit address) Shifts a 20-bit address into the JTAG memory address bus registerShifts a 20-bit address into the JTAG memory address bus register

• MsDelay (time) – wait a specified msMsDelay (time) – wait a specified ms• SetTCLK – set TCLK to 1SetTCLK – set TCLK to 1• clrTCLK – set TCLK to 0clrTCLK – set TCLK to 0• TDOvalue – variable containing the last value shifted out on TDOvalue – variable containing the last value shifted out on

TDOTDO


USART/USCIUSART/USCI

USART – Universal Synchronous/Asynchronous USART – Universal Synchronous/Asynchronous Receive Transmit using double-buffered Receive Transmit using double-buffered transmit/receive channelstransmit/receive channels• A clock – shared by sender and receiverA clock – shared by sender and receiver• Asynchronous – full duplexAsynchronous – full duplex• Synchronous – master, half duplexSynchronous – master, half duplex• Synchronous – Slave, half duplexSynchronous – Slave, half duplex

USART supportsUSART supports• synchronous SPI (3 or 4 pin)synchronous SPI (3 or 4 pin)• Asynchronous UARTAsynchronous UART• I2C (standard mode 100kbps, fast mode 400 kbps)I2C (standard mode 100kbps, fast mode 400 kbps)


SPI – Serial Peripheral InterfaceSPI – Serial Peripheral Interface

Synchronous serial communication of host Synchronous serial communication of host processor and peripheralsprocessor and peripherals

SPI InterfaceSPI Interface• Based on a 8-bit shift registerBased on a 8-bit shift register• SCK (serial shift clock) provided by the master device.SCK (serial shift clock) provided by the master device.• SCK a gated clockSCK a gated clock• Only generated during shiftingOnly generated during shifting• SCK stays idle between transfer SCK stays idle between transfer

3-wire3-wire• Serial clock (SCK)Serial clock (SCK)• SDI – Data InSDI – Data In• SDO – Data OutSDO – Data Out


I2C BusI2C Bus

A serial computer bus, Inter-Integrated Circuit (I2C), A serial computer bus, Inter-Integrated Circuit (I2C), invented by Philips for low-speed peripherals invented by Philips for low-speed peripherals communicationscommunications

2-wire bi-directional serial bus2-wire bi-directional serial bus• SCL - Clock LineSCL - Clock Line• SDA – Data LineSDA – Data Line

Introduced by Philips 20 years agoIntroduced by Philips 20 years ago Three data transfer speedsThree data transfer speeds

• Standard mode - 100 kbpsStandard mode - 100 kbps• Fast mode - 400 kbpsFast mode - 400 kbps• High speed mode - up to 3.4 Mbps High speed mode - up to 3.4 Mbps

Master and SlaveMaster and Slave


CC2420 RF TransceiverCC2420 RF Transceiver

2.4 GHz IEEE 802.15.4/ZigBee-ready RF 2.4 GHz IEEE 802.15.4/ZigBee-ready RF TransceiverTransceiver

2400-2483.5 MHz RF2400-2483.5 MHz RF Low-power and low-voltage wireless applicationsLow-power and low-voltage wireless applications DSSS (Digital direct sequence spread spectrum) DSSS (Digital direct sequence spread spectrum)

based modembased modem Spreading gain of 9dBSpreading gain of 9dB Effective data rate of 250 kbpsEffective data rate of 250 kbps Separate transmit and receive FIFOs: 128 byte Separate transmit and receive FIFOs: 128 byte

eacheach 4-wire SPI interface, serial clock up to 10 MHz4-wire SPI interface, serial clock up to 10 MHz


CC2420 RF TransceiverCC2420 RF Transceiver Testing CC2420Testing CC2420


CC2420 RF TransceiverCC2420 RF Transceiver CC2400EBCC2400EB

11/16/2006 wsn mote- mcu & sensor hardware 1 ecet 581 wireless sensor networks mote – mcu...

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