11. cad & design flow - upb...11 institute of microelectronic 11: cad & design flow systems...

Institute ofMicroelectronicSystems

11. CAD & Design Flow

2

Institute ofMicroelectronicSystems11: CAD & Design Flow

Motivation: Microelectronics Design Efficiency

Achieving required productivity by system-level design methodologies

1970 1980 1990 2000 2010

Layout Editor

Moore‘sLaw

Schematic Entry

Logic and Architectural Synthesis

???

Eff

icie

ncy

Platform-based Design

3


Example for Complex Systems: Embedded SoC

Properties

• Potentially consisting of a large number of components

• Specialised to an application domain• reactive• Real-time capability

Design Tasks

• Definition of communication architecture which is adequate to the application‘s structure

• Mapping of the system specification on available implementation components

Constraints

• Costs• Power consumption• Latency• Required flexibility

Embedded „System-on-Chip“

Micro-con-

troller

DSP

Memory

I/O-Module

ASIC

Actuators

Sensors

RFTransc.

4


Platform-Based System Design: Platform Life-Cycle

Platform

DSP core

CPU core

busMemory

DSP core

CPU core

busMemory

Specificblocks

OSAPI

Applications

OSAPI

Easy Implementation:

multiple devices with similar basic functions

ExperiencesNew Requirements

Feedback for future platform generations

Drivers

GenericPlatform

+Application-

SpecificAdditions

Lifecycle

5


Project Management: System Design: V Model

Analysis ofSystem Requirements

Design ofSystem Architecture

Analysis of HW/SW Component Requirements

HW/SW Co-Design

HW and SW ComponentImplementation

HW/SWIntegration

System Integration

System Delivery

System Properties and Constraints

Cost Analysis

Abstract Interfaces

Implemented HW/SW Modules

Prototype Generation and/orManufacturing

Product

Customer Application

Quality Assurance

Quality Assurance

Quality Assurance

Validation

Validation

Validation

SystemLevel

HW/SWComponentLevel

HW/SWIP Databaseand ImplementationLevel

ProductLevel

6


Hardware/Software Co-Design

Co-Simulation

HW/SW-Partitioning

Specification

HW-Specification SW-Specification

Synthesis Compilation

Heterogeneous HW-/SW-System

Communication Synth.

Placement/Routing Real-Time OS

O.k., let‘s gobottom-up now

7


Classes of CAD Tools

• Design Entry:– Graphical Editor (drawing schematic diagrams, physical layout, stick

layout diagrams, ...)– Language based circuit capture tools (for hardware description

languages like VHDL, Verilog, EDIF)

• Design Validation:– Physical design verification tools (design rule checker, extractor,

LVS, schematic and electrical rule checker)– Design Simulation:

• analog simulation: circuit level; behavioural level• digital simulations: circuit level, switch level, logic level, register transfer

level, architectural level, behavioural level; • thermal simulation: displaying heat dissipation on chip

– Formal Verification Methods

8


Classes of CAD Tools

• Design Implementation:– Layout Compilers (stick2layout, macrocell generators, datapath

compilers)– Layout Structuring & Optimization:

• Layout Compaction• Placement and Routing

– Logic Synthesis– Finite State Machine (FSM) Synthesis– Architectural Synthesis

• Management of Design Projects:– Design Databases:

• keep different versions (current, backup 1, ..., backup n) and views of a design object (schematic, simulation netlist, stick diagram, physicallayout, ...) in database

9


Full Custom Design: Design EntryFull Custom Design

With Full Custom Design techniques, the designer is able to individually specify the geometrical layout of the integrated circuit(transistor size[channel length, channel width, shape, ...], transistor placement, wire width, ...). The designer has the option to manually optimizethe layout

the most dense/area efficient layouts can be generated using the full custom design styles.

www.tanner.comLayout Editor

and Design Rule CheckHand-Crafted Layout:• The layout is drawn in form of rectangles and polygons on different layers using a graphics

editor.• The designer has to know a large set of process dependent design rules.• The mask layout is generated as drawn on the screen: direct influence to component

placement, to important parameters as W and L of transistors, wire widths, ...

10


Full Custom Design: Design Entry

Tool internal Design Representation: Geometrical Specification Language

• The layout is specified in textual form giving either the position and layer of rectangles(similar to hand crafted layout) or lines (as in stick diagrams).

• Since programming language constructs like – parameterized macros (to be used for layout segments as cells, ...), – loops (while, repeat, for, ...), and – conditional statements (if, case, ...) may be available, – parameterized layouts (e.g. generic transistor with W and L as parameters, cells for

different bit widths, sss) can be described using geometrical specification languages.

• Used in a large number of macrocell compilers.

11



B x y dx dy Box with length dx, width dy, an lower left hand corner placed at (x,y)L n Layout level (layer) for the box definiitions that followM n Start of macro definition nE End of macro definitionC n x y m Call for macro number n with translation x,y and orientation m.Q End of layout file

Example for a simplified geometrical specification language:

MOS Layer definitions:

Layer CMOS NMOS

1 n-diffusion n-diffusion2 p-diffusion ion implant3 polysilicon polysilicon4 metal metal5 contact contact8 n-well --9 overglass overglass

12



Cell Orientations:

Orien-tation Description

1 no rotation2 rotate 90° counterclockwise3 rotate 180° counterclockwise4 rotate 270° counterclockwise5 mirror about y-axis6 rotate 90° counterclockwise and mirror about y-axis7 rotate 180° counterclockwise and mirror about y-axis8 rotate 270° counterclockwise and mirror about y-axis

13



Full custom layout (hand crafted or generated out of a stick

diagram resp. a layout description)

Corresponding geometrical specification file and schematic diagram

14



Stick Diagram:• The layout is drawn in form of lines and polygons on differentlayers using a

graphics editor. • A stick--to--layout converter together with a compactor and a description of the

process design rules is then used to generate the rectanglebased layout.

• The designer can draw almost process and design rule independent symbolic layouts. Process adaption is done by the converter/compactor.

• Converter constraints (cell dimensions, channel widths / lengths of transistors, ...) can be specified.

• Stick Diagram Conventions:– Diffusion Areas: green (b/w: dotted line)– Polysilicon Lines: red (b/w: dashed line)– Metal Lines: blue (b/w: solid line)– Contacts: black

Example: Stick Diagram of a Transistor:

15


Full Custom Design: Stick Diagrams

Memory cell schematic and corresponding stick diagram

16


Fabrication Test Pattern

Block Layout

FloorplanningPlacement & Routing

Full Custom Design: Design Flow

Stick DiagramEditor

stick2layoutConverter

and Compactor

Layout Editor

Cells

Symbol Generation

Schematic Entry

Mask Layout Data

Fabrication

Simulation NetlistExtraction and Simulation (SPICE)

Design AnalysisDRC, ERC

Circuit ExtractionLVS

Circuit Simulation (SPICE)Timing Analysis

Test Pattern Generation

17


Cell Based Design

Cell based Design approaches rely on layout components predefined and provided by a silicon foundry. Several implemenation styles can be distinguished:

• Standard Cells:– layout blocks predefined by silicon foundry– full process sequence (amount of mask layers) for chip fabrication required

• Gate Arrays:– Linear Gate Arrays:

• pre-fabricated diffusion and poly layers (regular structures, e.g. transistors)• customized interconnect structures (wires in metal 1 and metal 2)• fixed size interconnect areas (channels)

– Sea of Gate Array• pre-fabricated diffusion and poly layers (regular structures e.g. transistors)• customized interconnect structures (wires in metal 1 and metal 2)• variable size interconnect areas (channels) over unused transistors

discussed later in this lecture

18


Cell based Full Custom Design: Design FlowMacrocell

Specification/Compilation

Fabrication

Simulation Netlist Extraction

Design AnalysisDRC, ERC

Circuit ExtractionLVS

Fabrication Test Pattern

CellLibrary

Symbol Generation

Schematic EntryGraphical

Data

Logic SimulationFault SimulationTiming Analysis

Test Pattern Generation

Simulation Models

Placement:Standard Cells

Macro CellsI/O Cells

LayoutData

Routing:Channel Generation

Global RoutingDetailed Routing

Mask Layout Data

Place &RouteOptimization

ParasiticWire Capacitances /Delay Backannotation

19


Standard Cell Full Custom Design

20


Physical Design Rule Check:

Physical design rule checks (DRCs) are performed to guarantee the conformity of a layout design to thesilicon vendor's set of design rules. Design rules are defined between objects on the same layer (minimum width, minimum spacing) as well as for objects on different layers (minimum spacing, overlapping, extension).

• Minimum width• Minimum spacing• Overlapping• Extension

Design rule violations are usually reported in the physical layout using a graphics editor. Sometimes, also a tabular form indicating the location and type of design rule violation can be generated.

Design Verification

21


Design Verification

Extraction:

• Circuit Level Extraction can be used to create a netlist for circuit level simulations(e.g. SPICE, ...). The netlist consists of MOS transistors (including geometrical parameters as W / L, parasitic capacitances), resistors, capacitances, diodes, ...

• Switch Level Extraction: can be used to create a netlist which can be processed by a switch level simulator. The resulting netlist consists of MOS transistors and parasitic capacitances (to model storage effects in MOS circuits).

• Parasitics Extraction: is used in conjunction with cell based design techniques. Since wire delay is dependent on the parasitic capacitance of a wire, parasitic capacitances of nets and input capacitances of other gates connected to an output can be used to estimate the extrinsic delays (Note: intrinsic delays [i.e. the delay of unloaded gates] are fetched from the cell library's simulation model data).

• Schematic Extraction: is executed to generate the connectivity data out of a graphical representation (schematic diagram) of a circuit module. The connectivity data is forwarded to a netlister which provides the information required e.g. by simulation tools(the simulators cannot operate on graphical data, they require netlists in a textual format). This kind of extraction is usually required in pre-layout design specification phases.

22


Design Verification

LVS:

The layout-versus-schematic (LVS) comparison tool checks the equivalence of the layout and its schematic.The tool can be used to find wrong connections or parameter mismatch (as W/L of transistors, ...) between a schematic and its physical layout representation.

Schematic / Electrical Rule Check (SRC / ERC):

To verify schematics used e.g. in cell based designs, a schematic rulechecker can find schematic rule violations (like the following examples):

• Warnings:• unconnected (floating) wire segments• open outputs• exceeded fanout

• Errors:• open inputs (undefined input value!)• number of bits differ for 2 buses connected together• number of input/output pins in a schematic differs from its symbol representation ( --> pins are

not accessible / not present at higher levels of schematic hierarchy)• more than one active driver connected to a net at the same time

23


Simulation

Goal of Simulation:

• Validation of the system, logic timing, and electricial behaviour• Verify testability aspects• Software development based on hardware simulation models

Simulator Classification:

Level Primitives observable TimingValues Model

RT registers, user coded bit strings, discreteprimitives, busses, etc. vectors time set

Gate gates bits continuousor discrete

Switch transistors, capacitators bits continuousor discrete

Electricial capacitators, resistors, real values continuous inductors, diodes etc. time set

24


Simulation: Models

Signal Modelling:

• values which exist in real circuits (0, 1, high impedance, oscillation, ...)• values which exist only in the simulator (unknown, transition, ...)• boolean logic set not sufficient

3-valued Logic:

logic zero = 0logic one = 1unknown = U

Example: AND 0 1 U0 0 0 01 0 1 UU 0 U U

Problems:

• Pessimism of U value (for example: circuit initialisation, spikes)• Logic values are often not sufficient (value strength needed)

25


Simulation: Models

Circuit and Delay Modelling:

• Circuit is built up by simulator primitives• Modelling of the timing/delay behaviour:

∆ : basic time unitτ(n) = n * ∆: delay of the gatet1, t2, t3, ...: clock time of a synchronous circuit(tν+1-tν): ∆t = m*∆

Timing Models:

• Zero Delay: ∆ = 0• Unit Delay: τ(n) = constant• Nominal delay: τ(n) = user-specified

26


Simulation: ModelsAdvanced Logic Simulators:

• Introduction of signal strength additional to logic values for driver and bus modelling

A : active, e.g. low impedance driverP : passive, e.g. high impedance driver (depletion load)S : storing, e.g. capacitive stored stateX : active indeterminate (e.g. active or storing)Y : passive indeterminate (e.g. passive or storing)Z : high impedance

• Instead of simple logical values, signals are used for simulation. A signal consists of a logical value and a strength.

• Logical Values = {0,1,X}• 16 states A0 A1 AX P0 P1 PX S0 S1 SX X0 X1 XX Y0 Y1 YX ZZ

A0 A0 AX AX A0 A0 A0 A0 A0 A0 A0 AX AX A0 A0 A0 A0A1 A1 A1 A1 A1 A1 A1 A1 A1 AX A1 AX A1 A1 A1 A1AX AX AX AX AX AX AX AX AX AX AX AX AX AX AXP0 P0 PX PX P0 P0 P0 X0 XX XX P0 PX PX P0P1 P1 PX P1 P1 P1 XX X1 XX PX P1 PX P1PX PX PX PX PX XX XX XX PX PX PX PXS0 S0 SX SX X0 XX XX Y0 YX YX S0S1 S1 SX XX X1 XX YX Y1 YX S1SX SX XX XX XX YX YX YX SXX0 X0 XX XX X0 X0 XX X0X1 X1 XX X1 XX XX X1XX XX XX XX XX XXY0 Y0 YX YX Y0Y1 Y1 YX Y1YX YX YXZZ ZZ

Overviewon

SignalCombinations

27


Simulation: Models

Example: Driver Modelling:

Competing Drivers at a Bus

28


Simulation

www.modelsim.com

29


Simulation: Techniques

Simulation Techniques:

• Compiler-driven technique:– Problems:

• Feedbacks• Sorting of gate netlist• Zero delay model• Entire circuit is simulated

• Event-driven simulation ...

Switch-Level Simulation:

• well-suited so simulate digital MOS circuits

• no fixed direction of signal flow• transistor modeled as a switch

with three states: open, closed, unknown

• algebraic or RC models

30


Simulation: MOS Transistor Model

Ideal Switch Transistor Model:

Linear Switch Transistor Model:

Gate

Drain

Source

Gate

Drain

Source

REFF

Logic n-Channel p-Channel(Gate) Enhancement Enhancement Depletion

1 Closed Open Weak0 Open Closed WeakX Unknown Unknown Weak

Remarks:• Switch transition time is

assumed to be zero or some nominal value

• Unknown states can cause problems

Logic n-Channel p-Channel(Gate) Enhancement Enhancement Depletion

1 REFF infinity REFF

0 infinity REFF REFF

X [REFF, infinity] [REFF, infinity] REFF

Remarks:• In the linear model,

node capacitance and devices resistance are used to compute output logic levels and transition time

• Ratio errors can be detected

31


Executable Specifications: VHDL

architecture structural of first_tap is

signal x_q,red : std_logic_vector(bitwidth-1 downto 0);signal mult : std_logic_vector(2*bitwidth-1 downto 0);

begin

delay_register:process(reset,clk)begin

if reset='1' thenx_q <= (others => '0');

elsif (clk'event and clk='1') thenx_q <= x_in;

end if;end process;

mult <= signed(coef)*signed(x_q);

Different types of modeling:

• Data Flow• Behaviour• Structure

VHDL is used for:

• Modelling• Simulation• Hardware Synthesis

VHDL: Very high speed integrated Circuits Hardware Description Language

32


Design Flow: IC Design with High-Level-Entryarchitecture structural of first_tap is

signal x_q,red : std_logic_vector(bitwidth-1 downto 0);signal mult : std_logic_vector(2*bitwidth-1 downto 0);

begin

delay_register:process(reset,clk)begin

if reset='1' thenx_q <= (others => '0');

elsif (clk'event and clk='1') thenx_q <= x_in;

end if;end process;

mult <= signed(coef)*signed(x_q);

VHDL-Description

RTL-Synthesis(Synopsys)

Gate-LevelNetlist

Layout

Placement &Routing

(Cadence/Mentor)Production

ASIC

33


Future Outlook: Networks-on-Chip

Generic Interface

Router

High-SpeedInterconnect

µP

FPGA MEM

ASIC

– Regular platform integrating independent subsystems

• combine structures of today‘s SoC complexity

– Separation between Communication and Computation

34


NoC-based design flow: Hardware/Software Co-DesignClassical Flow

Co-Simulation

HW/SW-Partitioning

Specification

HW-Specification SW-Specification

Synthesis Compilation

Heterogeneous HW-/SW-System

Communication Synth.

Placement/Routing Real-Time OS

Dynamic Allocation/Re-Mapping duringOperation

HW Library

Implementation

Specification

SW Library

NoC Mapping

NoC-based Flow

NoC Placement

35


Application Scenario: Mobile Video Terminal

Single Chip Mobile TerminalMobileServiceBase

Station(s)RF Centr.

CTRL

DISPLAY

Displ.CTRL

Different Configurations for:• High Quality (Resolution) Downstreaming• Low-Power Mode (Quality Reduction)• Image Compression and Upstreaming• Multi-Stream Modes

11. cad & design flow - upb...11 institute of microelectronic 11: cad & design flow systems...

Documents