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EE471REPORT LAB 1

INTRODUCTING TOTHE LAB

ENVIRONMENTGroup 10 10ECE

NG TRN CHTON

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Designing and Building Verilog HDL

Applications:

Given Module:

1. A four state ripple counter, it! active lo reset, using gate level "odel and Dflip#flop "odel$our!" !o#"$

%

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%i"ulations

%. A four stage &4 'it( s)nc!ronous don counter, it! active lo reset, using adataflo level "odel and t!e D flip#flop$

*rueta'le:

RRENT TATE NE&T TATE INPUT NEEDED'(C

'(B

'(A

'(D

'(C

'(B

'(A

D(D

D(C

D(B

0 0 0 0 0 0 1 0 0 00 0 1 0 0 1 0 0 0 10 1 0 0 0 1 1 0 0 10 1 1 0 1 0 0 0 1 0

1 0 0 0 1 0 1 0 1 01 0 1 0 1 1 0 0 1 11 1 0 0 1 1 1 0 1 11 1 1 1 0 0 0 1 0 00 0 0 1 0 0 1 1 0 00 0 1 1 0 1 0 1 0 10 1 0 1 0 1 1 1 0 10 1 1 1 1 0 0 1 1 01 0 0 1 1 0 1 1 1 01 0 1 1 1 1 0 1 1 1

1 1 0 1 1 1 1 1 1 11 1 1 0 0 0 0 0 0 0

)ro* +," -" M/pp23 4" ,/5"$Q

(AQBQC)QDDD=

+e) Mapping

D(D

BA00

01

11 10

DC

00 0 0 0 001 0 0 1 011 1 1 0 110 1 1 1 1

CBA

00

01

11 10

DC

00 0 0 1 00

1 1 1 0 111 1 1 0 110 0 0 1 0

B BA

6

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Q

(AQB)QCDC=

DB=QAQB

DA=QA

00

01

11 10

DC

00 0 1 0 101 0 1 0 110 0 1 0 1

11 0 1 0 1

ABA

00

01

11 10

DC

00 1 0 0 101 1 0 0 11

1 1 0 0 110 1 0 0 1

%ource code:

%i"ulation:

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%i"ulation:

9

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Learning t!e *ools . *!e %ignal *ap // Logic

Anal)0er:

ipple don counter ') gate level "odel:

o!nson %)nc!ronous counter ') 'e!avioral level "odel:

%)nc!ronous don counter ') data flo level "odel

%)nc!ronous don counter ') sc!e"atic:

2o"pare:T," r";u

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Learning t!e 2 Language . *!e 3irst %teps:

%ource code:

@

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*esting t!e calculator:

*est t!e converter:

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