10 ae fet-ii - didatticaweb

Analogue Electronics Paolo Colantonio

A.A. 2015-16

Università degli Studi di Roma Tor Vergata Dipartimento di Ingegneria Elettronica

P. Colantonio – Analogue Electronics 2|27 A.A. 2015/16

FETamplifiers•  SimpleamplifierscanbeformedusinganykindofFET•  Considerthegenericfollowingcircuit,thatcoulduseanyFET

•  Increasingtheinputvoltagevi•  thecurrentidonthedrainportincreases•  thevoltagedropacrossRincreases•  theoutputvoltagevodecreases Inver1ngamplifier


FETamplifiers


FETamplifiers:Transfercharacteris1c

Transfercharacteris1c


FETBiasingconsidera1on•  ThebiasingarrangementdeterminestheoperaAonofthecircuit,i.e.itsquiescentstate•  ThequiescentoutputvoltageVOisgivenby

•  SincetheFETisnotlinear,determiningthequiescentcondiAonsisnotstraighForward•  Moreover,whenselecAnganoperaAngpointweneedtoavoidcertainforbidden

regionsintheFET’scharacterisAcs

O DD D DV V I R= − ⋅


Biasingcircuits•  ItispossibletoadoptseveralconfiguraAonofbiasingcircuits.•  Themostsimpleisthefollowingone,basedontwoDCsupplyrails(VGGandVDD)

VDD

RD

RL

C2

C1

vout

+

-vin+

-

iL

VGG

RG

IDIG

VDSVGS

•  RGhighvalue(MΩ)inordertorepresentanopencircuitforACsignals

•  VGGnegaAveforJFET•  VGGposiAveornegaAveforMOS

DS DD D DV V I R= − ⋅

GS GG G G GGV V I R V= − ⋅ ≈


Biasingcircuits•  AdifferentsoluAoncouldbeadoptedavoidingtheuseoftwobaPeries,byusingthe

self-biasingschemes(accounAngforIG=0)VDD

RD

RL

C2

C1

vout

+

-

vin

+

-

iL

RGRS C3IG

VGS

VDS

VDD

RD

RL

C2

C1

vout

+

-

vin

+

-

iL

R2RS C3

VGS

VDS

R1

VDD

RD

RL

C2

C1

vout

+

-

vin

+

-

iL

R

RS C3IG

VGS

VDS

•  Theveninequivalence

•  OnlyfornegaAveVGG(JFET)

GS D SV I R= − ⋅

2

1 2GG DD

RV VR R

= ⋅+

1 2

1 2

R RRR R⋅

=+

GS GG D SV V I R= − ⋅


Devicevariability•  FETs,likeallacAvedevices,sufferfromvariability•  AssumingforexampleJFETwhichshowsthefollowingspreadofcharacterisAcs

•  TheeffectsofdevicevariabilityonthequiescentcondiAonsofacircuitcanbetackledusingfeedback•  forexample,theuseof‘automa0c’bias


DevicevariabilityVDD

RD

RL

C2

C1

vout

+

-

vin

+

-

iL

RGRS C3IG

VGS

VDS

VDD

RD

RL

C2

C1

vout

+

-

vin

+

-

iL

R2RS C3

VGS

VDS

R1

VGS

IDIDSS (MAX)

IDSS (min)

VP (min)VP (MAX)

IAIB

VGS=-I RD S

VGS

IDIDSS (MAX)

IDSS (min)

VP (min)VP (MAX)

IAIB

VGS=V -I RGG D S

VGG


BiasingcircuitsforEnhancementMOSVDD

RD

RL

C2

C1

vout

+

-

vin

+

-

iL

VGS

VDS

Rf

RD

RL

C2

C1

vout

+

-

vin

+

-

iL

R2VGS

VDS

Rf

VDD

•  ItistonotethatRfreducestheinputresistance(Miller’seffect)

GS DSV V=2

fGS DS

f

RV V

R R= ⋅

+

1f

inV

RR

A=

−Rin = R2 / /

Rf1− AV

"

#$$

%

&''


EquivalentcircuitofaFETamplifier

rd gmvgs

G

S S

D

Cds

Csd

Cgs

id

•  ThiscircuitcanrepresentanyoftheFETamplifiersabove•  Thisisasmallsignal-equivalentcircuit

•  Inthemediumfrequencyrangetheintrinsiccapacitancesareassumedtobeopencircuit(impedanceis1/ωC→∞)

•  ThedraincurrentisafuncAonofthegateanddrainvoltages

( ),D D GS DSi i v v=1

d m gs dsd

i g v vr

= ⋅ + ⋅

0ds DS

D Dm

GS GSv V

i igv v

=

∂ ∂= =∂ ∂ 0

1

gs GS

D D

d DS DSv V

i ir v v

=

∂ ∂= =∂ ∂



rd gmvgs

G

S S

D

Cds

Csd

Cgs

id

•  Assumingid=0itfollows

•  µ FETamplifyingfactor

•  gm transconductance

•  rd drain(oroutput)resistance

0d

dsm d

gs i

vg r

vµ

=

= = −

1d m gs ds

d

i g v vr

= ⋅ + ⋅



rd gmvgs

G

S S

D

Cds

Csd

Cgs

id

•  gm 0.1–0.5Ω-1•  rd 1–50kΩ•  Cgs,Cgd 1–10pF•  Cds 0.1–1pF

V [V]DS

ID [mA]

VGS

gm

V [V]DS

ID [mA]

VGS

atan(1/r )d

•  Increasingthetemperature,IDdecreasesandthusgm,duetothereducedchargemobility

•  NoThermalDriZ

0ds DS

D Dm

GS GSv V

i igv v

=

∂ ∂= =∂ ∂

0

1

gs GS

D D

d DS DSv V

i ir v v

=

∂ ∂= =∂ ∂

0d

dsm d

gs i

vg r

vµ

=

= = −


FETamplifiers

•  TheamplifierconfiguraAonarenameddependingonthedeviceterminalthatiscommontobothinputandoutputcircuits

voutvin

G

D

Svoutvin G

DS

vou tvin

G

S

D

CommonSource(CS) CommonGate(CG) CommonDrain(CD)


CommonSource

•  TheanalysisoftheamplifierperformancecanbeperformedbyreplacingtheFETwithitsequivalentsmallsignalmodel

•  Notethat•  RGrepresentstheequivalentresistanceduetothebiasingnetwork•  RDgoestoground,sincethesupplyvoltageVDDisavirtualearthpointforsmall

signals

VDD

RD

vout

vin+

-

RG vou trdgmvgs RDvgsvin

Thebiasingnetworkisnotrepresented(forsimplicity)

( )/ /outV m d D

in

vA g r R

v= = − ⋅ in GR R= / /out d DR r R=


CommonGate

RDvin+

-

Svout

vout

rdgmvgs

RDid

vin

S

( )1D m doutV

in d D

R g rvA

v r R⋅ +

= =+

gs inv v= −

out d Dv i R= − ⋅

out ind m gs

d

v vi g v

r−

= +

out inout D m in

d

v vv R g v

r⎡ ⎤−

= − ⋅ − +⎢ ⎥⎣ ⎦

11 Dout in D m

d d

Rv v R gr r

⎛ ⎞ ⎛ ⎞+ = ⋅ ⋅ +⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠


CommonGate•  FortheevaluaAonoftheinputandoutputresistancesitisrequiredtorefertothe

followingschemesInputresistance

rdgmvgs

RD

v

SI

I

Outputresistance

V

rd

RD

S

I

inVRI

=

( )1

1

m gs Dd

Dm

d d

I g v V R Ir

R I V gr r

= − + − ⋅ =

⎛ ⎞= ⋅ + ⋅ −⎜ ⎟

⎝ ⎠1 1 D

md d

RV g Ir r

⎛ ⎞ ⎛ ⎞⋅ + = ⋅ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

1d D

inm d

r RR

g r+

=+ / /out d DR r R=


Commondrain(orsourcefollower)

RG

vou t

rdgmvgs

RS

vgsvin

VDD

RS

voutvin+

-

VGS

•  DividingbothsidesforrdRS

Source follower

outout S m gs

d

vv R g v

r⎡ ⎤

= ⋅ −⎢ ⎥⎣ ⎦

gs in outv v v= − ( ) outout S m in out

d

vv R g v v

r⎡ ⎤

= ⋅ − −⎢ ⎥⎣ ⎦

1 Sout S m in S m

d

Rv R g v R g

r⎛ ⎞⋅ + + = ⋅⎜ ⎟⎝ ⎠

1 1out m in m

S d

v g v gR r

⎛ ⎞⋅ + + = ⋅⎜ ⎟⎝ ⎠

11 1

out mV

inm

d S

v gA

v gr R

= = ≈+ +


Commondrain•  FortheevaluaAonoftheinputandoutputresistancesitisrequiredtorefertothe

followingschemes

Inputresistance Outputresistance

RG

rdgmvgs

RS

vgsV

I

rdgmvgsvg s

VI

11

dout

m d m

rVRI g r g

= = ≈+

in GVR RI

= =

( )d m gsV r I g v= ⋅ +

gsv V= −

( )1 m d dV g r r I+ = ⋅


FETamplifiers:summary

CommonSource(CS) CommonGate(CG) CommonDrain(CD)

voutvin

G

D

Svoutvin G

DS

vou tvin

G

S

D

( )/ /outV m d D m D

in

vA g r R g R

v= = − ⋅ ≈ −

in GR R=

/ /out d D DR r R R= ≈

( )1D m doutV

in d D

R g rvA

v r R⋅ +

= =+

11d D

inm d m

r RR

g r g+

= ≈+

/ /out d D DR r R R= ≈

11 1

out mV

inm

d S

v gA

v gr R

= = ≈+ +

11

dout

m d m

rVRI g r g

= = ≈+

in GVR RI

= =


Anega1vefeedbackamplifier•  FeedbackcanbeusednotonlytostabilizethebiasingcondiAonsofacircuit,butalsoits

voltagegain

VDD

RD

RL

C2

C1

vout

+

-

vin

+

-

iL

R2RS C3

VGS

VDS

R1

VGS

IDIDSS (MAX)

IDSS (min)

VP (min)VP (MAX)

IAIB

VGS=V -I RGG D S

VGG

out DR R≈

/ /out D LV

in S

v R RAv R

= ≈ −

R1//R2vout

rdgmvgs

RD

vgsvin

RS

RL

i

vx

1 2/ /inR R R≈

characteris0cssetbystablepassivecomponents


Anega1vefeedbackamplifier•  Analysis

( )/ /out D Lv i R R= − ⋅

R1//R2vout

rdgmvgs

RD

vgsvin

RS

RL

i

vx

( )

/ / / /

out m gs d S

out outm gs d S

D L D L

v i g v r i R

v vg v r R

R R R R

= − ⋅ + ⋅ =

⎛ ⎞= − − ⋅ − ⋅⎜ ⎟⎝ ⎠

/ /out

gs in S in SD L

vv v R i v R

R R= − ⋅ = + ⋅

/ / / / / /out out out

out m in S d SD L D L D L

v v vv g v R r R

R R R R R R⎡ ⎤⎛ ⎞

= − − + ⋅ ⋅ − ⋅⎢ ⎥⎜ ⎟⎢ ⎥⎝ ⎠⎣ ⎦

1/ / / / / /d m d S S

out m d inD L D L D L

r g r R Rv g r v

R R R R R R⎛ ⎞⋅+ + + = −⎜ ⎟

⎝ ⎠

/ / / // /

out m d D L D LV

in D L d S m d S S

v g r R R R RAv R R r R g r R R

⋅= = − ≈ −

+ + + ⋅


Anega1vefeedbackamplifier•  Analysis

( )m gs d Sv i g v r i R= − ⋅ + ⋅

R1//R2vout

rdgmvgs

RD

vgsvin

RS

RL

i

vx

' / /out out D DR R R R= ≈

1 2/ /inR R R=

V

rdgmvgsvgs

RS

I

vx

gs Sv i R= − ⋅

( )d m d S S m d Sv i r g r R R i g r R= ⋅ + + ≈ ⋅'out m d S

vR g r Ri

= ≈


Useofadecouplingcapacitor•  ThefeedbackamplifierhasarelaAvelylowgain•  Useofadecouplingcapacitorcanincreasethegainbyremovingsmall-signalfeedback•  Gainissimilartothatofthecommonsourceamplifier•  RequireslargeCSatlowfrequencies

VDD

RD

RL

C2

C1

vout

+

-

vin

+

-

iL

R2RS CS

VGS

VDS

R1


Splitloadedamplifier

ReplacingtheFETequivalentmodel

VDD

RD C2

C1

vo1vin

R2 RS

R1

C3

vo2vo2

rdgmvgs

RD

vin

RS

id

Svo1

vGS

GD

•  ApplyingtheTheveninequivalencebetweendrainandsourcenodes

,ds Thevenin m gs d gsv g v r vµ= − ⋅ = − ⋅

,ds Thevenin dr r=



1

2

o d D

o d S

v i Rv i R

= − ⋅

= ⋅

[ ] ( )d D d S in d Si R r R v i Rµ⋅ + + = ⋅ − ⋅

vo2

rd/ (+1)µ

vinµ/(µ+1)

RS

id

D

-

+

S

RD/ (+1)µ

rd

µvin

RDid

vo1

D

-

+

S

( RSµ+1)

Equivalentmodelforvo1

Dividing all elements for µ+1

Equivalent model for vo2

vo2

rd

µ(vin-v )o2

RD

RS

id

vo1

D

-

+

S



( )1

1 1o D

Vin D d S

v RAv R r R

µµ⋅

= = −+ + + ⋅

( )1 1o d SR r Rµ= + + ⋅

( )2

21

11

So S

VD din D d S

S

Rv R

AR rv R r RR

µµµ

µµ

⋅⋅+

= = =+ + + ⋅ +++

2 1d D

or R

Rµ+

=+

•  IfRS=RD=R ( )2 1 2V Vd

RA Ar R

µµ⋅

= − =+ ⋅ +

rd

µvin

RDid

vo1

D

-

+

S

( RSµ+1) vo2

rd/ (+1)µ

vinµ/(µ+1)

RS

id

D

-

+

S

RD/ (+1)µ

( )

( )1

1

1

d D d S in

oD d S in

D

i R r R v

vR r R v

R

µ µ

µ µ

⎡ ⎤⋅ + + + = ⋅⎣ ⎦

⎡ ⎤− ⋅ + + + = ⋅⎣ ⎦ 2

1 1

1 1

D dd S in

o D dS in

S

R ri R v

v R rR v

R

µµ µ

µµ µ

⎡ ⎤+⋅ + = ⋅⎢ ⎥+ +⎣ ⎦

⎡ ⎤+⋅ + = ⋅⎢ ⎥+ +⎣ ⎦

HIGH LOW

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