1 verilog digital system design z. navabi, 2006 rt level design rt level design: taking a high...

1Verilog Digital System Design Z. Navabi, 2006

RT Level DesignRT Level Design RT level design:RT level design:

Taking a high level description of a designTaking a high level description of a design Partitioning Partitioning Coming up with an architectureComing up with an architecture Designing the bussing structureDesigning the bussing structure Describing and implementing various components Describing and implementing various components

of the architectureof the architecture Steps in RT level design:Steps in RT level design:

Control/Data PartitioningControl/Data Partitioning Data Part DesignData Part Design Control Part DesignControl Part Design


RT Level DesignRT Level DesignRT LevelRT Level DesignDesign

Control/data Control/data PartitioningPartitioning

Data PartData Part Control PartControl Part


Control/Data PartitioningControl/Data PartitioningRT LevelRT Level DesignDesign


Data PartData Part Control PartControl Part

Control/data Partitioning


Control/Data PartitioningControl/Data Partitioning

RT Level Design

Flags & status

Opcode

Data flowControl signals

ControlDataPath

Reg

Control

Outputs

Control

Inputs

Data Inputs

Data Outputs


Data PartData PartRT LevelRT Level DesignDesign


Data PartData Part Control PartControl PartData Part


Data PartData Part

Flags & status

Opcode


DataPath

Reg

Data Inputs

Data Outputs


Data PartData Partmodulemodule DataPath DataPath

(DataInput, DataOutput, Flags, Opcodes, (DataInput, DataOutput, Flags, Opcodes, ControlSignals);ControlSignals);

inputinput [15:0] DataInputs; [15:0] DataInputs;output output [15:0] DataOutputs;[15:0] DataOutputs;outputoutput Flags, ...; Flags, ...;outputoutput Opcodes, ...; Opcodes, ...;inputinput ControlSignals, ...; ControlSignals, ...;// instantiation of data components // instantiation of data components // ...// ...// interconnection of data components// interconnection of data components// bussing specification// bussing specification

endmoduleendmodule

DataPath ModuleDataPath Module

Control Control Signals:Signals:

Inputs to data Inputs to data part, sent to part, sent to

the data the data components components and bussesand busses

Output Signals: Output Signals: Going to the Going to the control part, control part, provide flags provide flags and status of and status of

the datathe data


Data PartData Part

modulemodule DataComponent DataComponent (DataIn, DataOut, ControlSignals);(DataIn, DataOut, ControlSignals);

inputinput [7:0] DataIn; [7:0] DataIn;outputoutput [7:0] DataOut; [7:0] DataOut;inputinput ControlSignals; ControlSignals;// Depending on ControlSignals // Depending on ControlSignals // Operate on DataIn and// Operate on DataIn and// Produce DataOut// Produce DataOut

endmoduleendmodule

Partial Verilog Code of a Data ComponentPartial Verilog Code of a Data Component

Data Data ComponentComponent::

Shows how the Shows how the component component

uses its input uses its input control signals control signals

to perform to perform various various

operations on operations on its data inputsits data inputs


Control PartControl PartRT LevelRT Level DesignDesign


Data PartData Part Control PartControl PartControl Part


Control PartControl Part

Flags & status

Opcode


Control

Control

Outputs

Control

Inputs

Consists of one Consists of one or more state or more state

machines machines to keep the to keep the state of the state of the

circuit.circuit.

Makes Makes decisions as to decisions as to when and what when and what control signals control signals

to issue to issue depending on depending on

its state.its state.


Control PartControl Part

modulemodule ControlUnit ControlUnit (Flags, Opcodes, ExternalControls, ControlSignals);(Flags, Opcodes, ExternalControls, ControlSignals);

inputinput Flags, ...; Flags, ...;inputinput Opcodes, ...; Opcodes, ...;inputinput ExternalControls, ...; ExternalControls, ...;outputoutput ControlSignals; ControlSignals;// Based on inputs decide :// Based on inputs decide :// What control signals to issue,// What control signals to issue,// and what next state to take// and what next state to take

endmoduleendmodule

Outline of a ControllerOutline of a Controller

Takes Takes control control

inputs from inputs from thethe

Data PartData Part


Sequential MultiplierSequential Multiplier

Multiplier Block DiagramMultiplier Block Diagram

start

Clklsb-out

done

msb-out

datapath

Multiplier

An add-and-An add-and-shiftshift

SequentialSequentialMultiplierMultiplier

An 8-bit bidirectional An 8-bit bidirectional I/OI/O

for inputing it’s 8-bit for inputing it’s 8-bit operands and outputing operands and outputing

its 16-bit output one its 16-bit output one byte at a time.byte at a time.

MultiplicatiMultiplication begins on begins with the with the

startstart pulse. pulse.

For the most-For the most-significant bytesignificant byte

When both When both bytes are bytes are outputed.outputed.


Sequential MultiplierSequential Multiplier

SequentialSequential

MultiplierMultiplier

Shift-and-addShift-and-add

MultiplicationMultiplication

ProcessProcess



DesignDesign

Multiplier Multiplier

TestingTesting


Shift-and-add Shift-and-add Multiplication ProcessMultiplication Process





ProcessProcess



DesignDesign


TestingTesting

Shift-and-addShift-and-addMultiplicationMultiplication

ProcessProcess



Manual Binary MultiplicationManual Binary Multiplication

1 0 1 1 0 1 1 0

1 0 0 1 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0

1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0

1 1 0 1 0 0 1 0 0 1 1 1 0 0 0

B:A:

Depending on bit Depending on bit i i ofof

operand operand AA, either , either operandoperand

B B is added to the is added to the collectedcollected

partial result and partial result and thenthen

shifted to the rightshifted to the right

(when bit (when bit i i is 1) is 1)

Or (when bit Or (when bit i i is is 0) the0) the

collected partial collected partial resultresult

is shifted one is shifted one place toplace to

the right without the right without beingbeing

added to added to BB..


0 0 00P: 0 0 11A:

1 0 11B:

t = 0

1 1 00 1 0 01

1 0 11

t = 1 0 0 0 0 + 1 1 0 1 0 1 1 0 1

0 1 10 1 1 00

1 0 11

t = 2 0 1 1 0 + 0 0 0 0 0 0 1 1 0

0 0 10 0 1 11

1 0 11

t = 3 0 0 1 1 + 0 0 0 0 0 0 0 1 1

1 1 10 1 0 10

1 0 11

t = 4 0 0 0 1 + 1 1 0 1 0 1 1 1 0

A and B

Result


Hardware Oriented Multiplication ProcessHardware Oriented Multiplication Process



Hardware Oriented Multiplication Process (Continued)Hardware Oriented Multiplication Process (Continued)

0 0 00P: 0 0 11A:

1 0 11B:

t = 0

A and B

Because Because A[0] A[0] is 1, is 1, the partialthe partial

sum of sum of B B + + P P is is calculated.calculated.




1 1 00 1 0 01

1 0 11

t = 1 0 0 0 0 + 1 1 0 1 0 1 1 0 1

0 1 10 1 1 00

1 0 11

t = 2 0 1 1 0 + 0 0 0 0 0 0 1 1 0

The right most The right most bit ofbit of

which is shifted which is shifted into into AA,,

and the rest and the rest replace replace PP

Because Because A[0] A[0] is 0, is 0,

0000 + 0000 + P P is is calculatedcalculated




0 0 10 0 1 11

1 0 11

t = 3 0 0 1 1 + 0 0 0 0 0 0 0 1 1

1 1 10 1 0 10

1 0 11

t = 4 0 0 0 1 + 1 1 0 1 0 1 1 1 0

ResultThe least significant 4 The least significant 4

bits ofbits of

the multiplication the multiplication resultresult

become available in become available in A A and theand the

most-significant bits most-significant bits in in PP..


Sequential Multiplier Sequential Multiplier DesignDesignSequentialSequential




ProcessProcess



DesignDesign


TestingTesting

SequentialSequentialMultiplierMultiplier

DesignDesign


Sequential Multiplier Sequential Multiplier DesignDesignSequentialSequential

MultiplierMultiplier Design Design

Top-Level CodeTop-Level Code

of the Multiplierof the Multiplier

Control DataControl Data

PartitioningPartitioningMultiplier Multiplier

DatapathDatapath

DatapathDatapath

DescriptionDescriptionMultiplierMultiplier

ControllerController


Control Data PartitioningControl Data PartitioningSequentialSequential

Multiplier DesignMultiplier Design





DatapathDatapath

DatapathDatapath



Control DataControl DataPartitioningPartitioning


Control Data PartitioningControl Data Partitioning

Datapath and ControllerDatapath and Controller

Datapathdatabus

8

clr_P

load_P

load_Bmsb_out

lsb_outsel_sum

load_Ashift_A

start

lsb_out

msb_out

done

A0

Data part consists ofData part consists of

registers, logic units, registers, logic units, andand

their interconnecting their interconnecting buses.buses.

On the rising edge of On the rising edge of thethe

system clock, the system clock, the controllercontroller

goes into a new goes into a new state. state.


Multiplier DatapathMultiplier DatapathSequentialSequential






DatapathDatapath

DatapathDatapath



MultiplierMultiplierDatapathDatapath


Multiplier DatapathMultiplier Datapath

Multiplier Block DiagramMultiplier Block Diagram

sel_sumco

sumBdata

load_B

clk

clr_P

load_P

A0

AP

load_A

msb_out

lsb_out

shift_A

ShiftAdd[0]

Sh

iftAd

d

8-bit 8-bit RegistersRegisters

8-bit Shift 8-bit Shift RegisterRegister

Tri-state Tri-state BuffersBuffers

AdderAdder

MultipleMultiplexerxer

Selects carry-out Selects carry-out fromfrom

the adder or 0 the adder or 0 dependingdepending

on the value of on the value of sel_sumsel_sum


Datapath DescriptionDatapath DescriptionSequentialSequential






DatapathDatapath

DatapathDatapath


ControllerControllerDatapathDatapath

DescriptionDescription


modulemodule datapath ( datapath ( inputinput clk, clr_P, load_P, clk, clr_P, load_P,

load_B, msb_out, lsb_out, load_B, msb_out, lsb_out,

sel_sum, load_A, shift_A, sel_sum, load_A, shift_A,

inoutinout [7:0] data, [7:0] data, outputoutput A0 ); A0 );

wirewire [7:0] sum, ShiftAdd; [7:0] sum, ShiftAdd;

regreg [7:0] A, B, P; [7:0] A, B, P;

wirewire co; co;

..............................................................

............................... ...............................

Datapath DescriptionDatapath Description

Datapath Verilog CodeDatapath Verilog Code


always always @( @( posedge posedge clk ) clk ) ifif (load_B) B <= data; (load_B) B <= data;

alwaysalways @( @( posedgeposedge clk ) clk )

ifif (load_P) P <= {co&sel_sum, ShiftAdd[7:1]}; (load_P) P <= {co&sel_sum, ShiftAdd[7:1]};

assign assign { co, sum } = P + B;{ co, sum } = P + B;

alwaysalways @( @( posedge posedge clk )clk )

case case ( { load_A, shift_A } )( { load_A, shift_A } )

2'b01 : A <= { ShiftAdd[0], A[7:1] };2'b01 : A <= { ShiftAdd[0], A[7:1] };

2'b10 : A <= data;2'b10 : A <= data;

default default : A <= A;: A <= A;

endcaseendcase


Datapath Verilog Code (Continued)Datapath Verilog Code (Continued)

RepresenRepresents ts

register register BB

Represents Represents register register PP

for the partial for the partial resultresult

Represents Represents

the 8-bit the 8-bit adderadder

Implements Implements the the

8-bit shift-8-bit shift-register for register for operand operand AA

Loads Loads AA with with datadata

ShiftsShifts A A contentscontents


............................... ...............................

assignassign A0 = A[0]; A0 = A[0];

assignassign ShiftAdd = clr_P ? 8'h0 : ShiftAdd = clr_P ? 8'h0 :

( ~sel_sum ? P : sum );( ~sel_sum ? P : sum );

assignassign data = lsb_out ? A : 8'hzz; data = lsb_out ? A : 8'hzz;

assignassign data = msb_out ? P : 8'hzz; data = msb_out ? P : 8'hzz;

endmoduleendmodule


Datapath Verilog Code (Continued)Datapath Verilog Code (Continued)

Multiplexer for Multiplexer for

selection of selection of sumsum or or PP

2 sets of tri-state 2 sets of tri-state buffersbuffers

driving the driving the bidirectionalbidirectional

datadata bus of the bus of the datapathdatapath


Multiplier ControllerMultiplier ControllerSequentialSequential






DatapathDatapath

DatapathDatapath


ControllerControllerMultiplierMultiplierControllerController


`define`define idle 4'b0000 idle 4'b0000

`define`define init 4'b0001 init 4'b0001

`define`define m1 4'b0010 m1 4'b0010








`define`define rslt1 4'b1010 rslt1 4'b1010

`define`define rslt2 4'b1011 rslt2 4'b1011


Multiplier Control StatesMultiplier Control States

The multiplier The multiplier controllercontroller

is a finite state is a finite state machinemachine

that has 2 starting that has 2 starting states,states,

8 multiplication 8 multiplication states, states,

and 2 ending states.and 2 ending states.

States and States and

their binary their binary assignmentsassignments

The multiplier The multiplier performsperforms

add-and-shift of add-and-shift of P+BP+B, or, or

P+0P+0, depending on , depending on A0A0

The multiplier The multiplier waits forwaits for

start start while loading while loading AAMultiplier loads Multiplier loads BB

The 2 halves of the The 2 halves of the resultresult

are put on are put on databus.databus.


modulemodule controller ( controller ( inputinput clk, start, A0, clk, start, A0,

output regoutput reg clr_P, load_P, load_B, clr_P, load_P, load_B, msb_out, msb_out, lsb_out, sel_sum, lsb_out, sel_sum,

output regoutput reg load_A, Shift_A, done); load_A, Shift_A, done);

regreg [3:0] current; [3:0] current;

always always @ ( @ ( negedgenegedge clk ) clk ) beginbegin

clr_P = 0; load_P = 0; load_B = 0; msb_out = 0; clr_P = 0; load_P = 0; load_B = 0; msb_out = 0; lsb_out = 0; lsb_out = 0;

sel_sum = 0; load_A = 0; Shift_A = 0; done = 0;sel_sum = 0; load_A = 0; Shift_A = 0; done = 0;

....................................................................

Multiplier ControllerMultiplier Controller

Verilog Code of ControllerVerilog Code of Controller

Declares signals Declares signals thatthat

connect to connect to datapathdatapath portsports

always always block to block to issueissue

control signals and control signals and makemake

state transitionsstate transitions

All control signal All control signal outputsoutputs

are set to their are set to their inactive values.inactive values.

Eliminating Eliminating unwantedunwanted

latches that may belatches that may be

generated by a generated by a synthesissynthesis

tool for these tool for these outputs.outputs.


casecase ( current ) ( current )

ìdle : ìdle :

ifif (~start) (~start) beginbegin

current <= ìdle;current <= ìdle;

done = 1;done = 1;

end else beginend else begin

current <= ìnit; current <= ìnit;

load_A = 1; clr_P = 1; load_P = 1;load_A = 1; clr_P = 1; load_P = 1;

endend

ìnit : ìnit : beginbegin

current <= `m1; current <= `m1;

load_B = 1; load_B = 1; endend


Verilog Code of Controller (Continued)Verilog Code of Controller (Continued)

The currently The currently active stateactive state

of the machineof the machine

To Load To Load AA

To clear theTo clear the P P registerregister


............................... ...............................

`m1, `m2, `m3, `m4, `m5, `m6, `m6, `m7, `m1, `m2, `m3, `m4, `m5, `m6, `m6, `m7, `m8: `m8: begin begin

current <= current + 1; current <= current + 1;

Shift_A = 1; load_P = 1; Shift_A = 1; load_P = 1;

ifif (A0) sel_sum = 1; (A0) sel_sum = 1;

end end

............................... ...............................



Shifting Shifting A A

LoadingLoading PP

Asserting Asserting ssel_sum el_sum


`rslt1 : `rslt1 : beginbegin

current <= `rslt2; current <= `rslt2;

lsb_out = 1;lsb_out = 1;

endend

`rslt2 : `rslt2 : beginbegin

current <= ìdle; current <= ìdle;

msb_out = 1; msb_out = 1;

endend

defaultdefault : current <= ìdle; : current <= ìdle;

endcaseendcase

endend

endmoduleendmodule



In the result In the result states,states,

lsb_out lsb_out and and msb_outmsb_out

are asserted in are asserted in twotwo

consecutive consecutive clocks inclocks in

order to put order to put A A and and PP

on the data buson the data bus

respectively.respectively.


Top-Level Code of the Top-Level Code of the MultiplierMultiplierSequentialSequential Multiplier DesignMultiplier Design





DatapathDatapath

DatapathDatapath



Top-Level CodeTop-Level Codeof the Multiplierof the Multiplier


modulemodule Multiplier ( Multiplier ( inputinput clk, start, clk, start,

inoutinout [7:0] databus, [7:0] databus,

outputoutput lsb_out, msb_out, done ); lsb_out, msb_out, done );

wirewire clr_P, load_P, load_B, msb_out, lsb_out, clr_P, load_P, load_B, msb_out, lsb_out, sel_sum, load_A, Shift_A;sel_sum, load_A, Shift_A;

datapath dpu( clk, clr_P, load_P, load_B,datapath dpu( clk, clr_P, load_P, load_B,

msb_out, lsb_out, sel_sum, load_A, msb_out, lsb_out, sel_sum, load_A, Shift_A, databus, A0 ); Shift_A, databus, A0 );

controller cu( clk, start, A0, clr_P, load_P, controller cu( clk, start, A0, clr_P, load_P, load_B, msb_out, lsb_out, sel_sum, load_B, msb_out, lsb_out, sel_sum,

load_A, Shift_A, done );load_A, Shift_A, done );

endmoduleendmodule

Top-Level Code of the Top-Level Code of the MultiplierMultiplier

Top-Level Multiplier CodeTop-Level Multiplier CodeDatapath and Datapath and

controllercontroller

modules are modules are instantiated.instantiated.


Multiplier TestingMultiplier Testing





ProcessProcess



DesignDesign


TestingTestingMultiplierMultiplier

TestingTesting


timescaletimescale 1ns/100ps 1ns/100ps

modulemodule test_multiplier; test_multiplier;

regreg clk, start, error; clk, start, error;

wirewire [7:0] databus; [7:0] databus;

wirewire lsb_out, msb_out, done; lsb_out, msb_out, done;

regreg [7:0] mem1[0:2], mem2[0:2]; [7:0] mem1[0:2], mem2[0:2];

reg reg [7:0] im_data, opnd1, opnd2; [7:0] im_data, opnd1, opnd2;

regreg [15:0] expected_result, multiplier_result; [15:0] expected_result, multiplier_result;

integerinteger indx; indx;

............................... ...............................

............................... ...............................

What is What is calculated calculated

in the in the testbenchtestbench


Multiplier Testbench OutlineMultiplier Testbench Outline

An auto-check An auto-check

interactive interactive testbench fortestbench for

the sequential the sequential multipliermultiplier

Inputs and Inputs and outputs outputs of the of the

multipliermultiplier

A bidirectional bus,A bidirectional bus,

declared as declared as wire wire for for readingreading

Declared for writing Declared for writing to theto the

bidirectionalbidirectional databus databus

The result The result read read

from the from the multipliermultiplier


............................... ...............................

Multiplier uut ( clk, start, databus, lsb_out, Multiplier uut ( clk, start, databus, lsb_out, msb_out, done ); msb_out, done );

initial begininitial begin: Apply_data ... : Apply_data ... endend //Figure 8.11 //Figure 8.11

initial begininitial begin: Apply_Start ... : Apply_Start ... endend //Figure 8.12 //Figure 8.12

initial begininitial begin: Expected_Result... : Expected_Result... end end //Figure8.13//Figure8.13

alwaysalways @( @(posedgeposedge clk) clk) beginbegin: Actual_Result ... : Actual_Result ... endend // Figure 8.14 // Figure 8.14

alwaysalways @( @(posedgeposedge clk) clk) beginbegin: Compare_Results...: Compare_Results...end end // Figure 8.15// Figure 8.15

alwaysalways #50 clk = ~clk; #50 clk = ~clk;

assignassign databus=im_data; databus=im_data;

endmoduleendmodule


Multiplier Testbench OutlineMultiplier Testbench Outline

Applies three rounds Applies three rounds of testof test

to the to the Multiplier Multiplier module. module.

In each round, data is In each round, data is appliedapplied

to the module under to the module under test andtest and

results are read and results are read and comparedcompared

with the expected with the expected results.results.

Read data files Read data files data1.dat data1.dat

and and data2.dat data2.dat and and apply data to apply data to

databusdatabus

Apply Apply start start to to start start

multiplicationmultiplicationCalculate the Calculate the

expected expected resultresult

Wait for Wait for multiplication to multiplication to

complete, and complete, and collect the collect the

calculated resultcalculated result

Compare expected Compare expected andand

calculated results calculated results and issueand issue

error if they do not error if they do not matchmatch

Above tasks are timedAbove tasks are timed

independently, at the independently, at the same time,same time,

an always block an always block generates agenerates a

periodic signal on periodic signal on clk clk that that

clocks the multiplier.clocks the multiplier.


Multiplier TestingMultiplier TestingMultiplierMultiplier

TestingTesting

ComparingComparing

ResultsResults

ReadingReading

Data FilesData FilesApplyingApplying

StartStart

CalculatingCalculating

Expected ResultExpected ResultReadingReading

Multiplier OutputMultiplier Output

1 verilog digital system design z. navabi, 2006 rt level design rt level design: taking a high...

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