1 serial decoder & multiplexer ryan bruno gly cruz frank gurtovoy christopher plowman advisor:...

1

Serial Decoder& Multiplexer

Ryan BrunoGly Cruz

Frank GurtovoyChristopher Plowman

Advisor: Dr. David ParentMay 11 (or 16), 2005

2

Agenda

• Abstract• Introduction

– Why a Serial Decoder/Multiplexer?– Potential Applications– Theory of Operation

• Calculations• Cadence Details• Summary of Results• Cost Analysis• Conclusions

3

Abstract• Target spec

– Simple DFF-Stabilized Decoder and Mux– 200Mhz clock frequency– Within 400μm x 400μm area– Power density spec of 23W/cm2

• Actual– Simple DFF-Stabilized Decoder and Mux– 200MHz clock frequency– Area of 316μm x 274μm– 12.9 mW of Power for 14.9 W/cm2

4

Introduction

• Serial Decoder/Multiplexer– Allows a “Master” to communicate with multiple “Slaves”

using fewer pins than dedicating a Port

• Applications– Microcontroller-based systems– Consumer Products

• Theory– Address and Data share signal at different times.– Decoder selects the receiving slave– Mux chooses the transmitting slave

5

Master Packet Scheme

A0 A1 A2 1WAKE UP

D0 D1 D2 D3 Dn...DC DC

RESET RESET

CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK

RESET LOW RESET LOW RESET LOW

6

Sample Packet

0 1 1 1WAKE UP

0 1 1 0 01 1

RESET RESET

CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK

RESET LOW RESET LOW RESET LOW

0 1 0

1WAKE UP

0 1 1 0 01 0Slave Six Sees:

000IGNORED IGNORED

0WAKE UP

0 0 0 0 00 0

Other Slaves See:

000IGNORED IGNOREDIGNORED IGNORED IGNORED IGNORED IGNORED IGNORED IGNORED IGNORED IGNORED

IGNORED

A1

A1

A2

A2

7

Longest Path Calculations

CELLWN Load

WP Load

Cg or Cin of load phl plh A

NSN

NSP

Cdn

Cdp R WN WP

(cm) (cm) F s s cm cm

BUFF21.50E-

041.50E-

041.0000E-

123.75E-

103.75E-

101.09E+

04 1 1 1 11.736

1.89E-03 3.28E-03 Output Buffer

BUFF11.89E-

033.28E-

038.6659E-

143.75E-

103.75E-

101.09E+

04 1 1 1 11.736

1.76E-04 3.06E-04 Output Buffer

Tenacious INV1.76E-

043.06E-

048.0832E-

153.21E-

103.21E-

101.12E+

04 1 1 1 11.750

1.50E-04 2.62E-04

Input Stabilization

DEC_NAND1.50E-

042.62E-

046.9217E-

153.75E-

103.75E-

101.09E+

04 4 1 1 40.434

3.46E-04 1.50E-04 Decoder

DFF_DATA_NORS

3.46E-04

1.50E-04

6.7178E-14

3.21E-10

3.21E-10

2.67E+04 1 2 2 1

3.499

6.12E-04 2.14E-03 Address Hold

DFF_DATA_MXS

6.12E-04

2.14E-03

3.4880E-13

7.50E-10

7.50E-10

2.16E+04 2 2 1 1

1.643


DFF_DATA_NORM

1.41E-03

2.32E-03

6.2528E-14

4.50E-10

4.50E-10

2.52E+04 1 2 2 1

3.435


DFF_DATA_MXM

3.20E-04

1.10E-03

2.3800E-14

4.50E-10

4.50E-10

2.52E+04 2 2 1 1

1.718


MISO_NOR 22.80E-

044.81E-

047.5308E-

143.00E-

103.00E-

101.13E+

04 1 2 2 33.510

3.22E-04 1.13E-03

Master In Multiplexer

8

Mux Path CalculationsCELL

WN Load

WP Load


NSN

NSP

Cdn

Cdp R WN WP


BUFF21.50E-

041.50E-

04 1.0000E-123.75E-

103.75E-

101.09E+

04 1 1 1 11.73

61.89E-

03 3.28E-03 Output Buffer

BUFF11.89E-

033.28E-

03 8.6659E-143.75E-

103.75E-

101.09E+

04 1 1 1 11.73

61.76E-

04 3.06E-04 Output Buffer

MISO_NOR 22.86E-

044.91E-

04 7.5578E-143.00E-

103.00E-

101.13E+

04 1 2 2 33.51

03.23E-

04 1.13E-03Master In Multiplexer

MUX_NOR 23.23E-

041.13E-

03 1.0000E-135.63E-

105.63E-

109.99E+

03 1 2 2 23.37

91.34E-


MUX_NAND-4*21.34E-

044.54E-

04 3.9477E-145.63E-

105.63E-

109.99E+

03 4 1 4 40.42

23.55E-


MUX_NAND-4*83.55E-

041.50E-

04 8.4777E-155.63E-

105.63E-

109.99E+

03 4 1 1 40.42

23.55E-


9

Clock Block Calculations

CELLWN Load

WP Load


NSN

NSP

Cdn

Cdp R WN WP


MISO_NOR2.80E-

044.81E-

047.5308E-

143.00E-

103.00E-

101.13E+

04 1 2 2 33.510

3.22E-04 1.13E-03

Address Capture Logic

DFF_CB_NORS3.22E-

041.13E-

034.8788E-

143.75E-

103.75E-

102.61E+

04 1 2 2 13.473

3.51E-04 1.22E-03 Clock Block

DFF_CB_MXS3.51E-

041.22E-

037.5108E-

143.75E-

103.75E-

102.61E+

04 2 2 1 11.736


DFF_CB_NORM1.01E-

031.75E-

034.6366E-

143.75E-

103.75E-

102.61E+

04 1 2 2 13.473


DFF_CB_MXM3.36E-

041.17E-

032.5206E-

143.75E-

103.75E-

102.61E+

04 2 2 1 11.736


CB_NAND23.98E-

046.91E-

041.8289E-

141.47E-

101.47E-

101.21E+

04 2 1 3 20.897


10

Schematic

Address Capture Logic

Output Buffer

BUFFER2BUFFER1

DEC_NANDBEST CASE

DecoderAddress DFF

x8

x8

x3

00 01 11

Q

QSET

CLR

DD0

Q

QSET

CLR

DD1

Clock Block (State Machine)

CB_NAND

CB_NAND

/Xmit_EN

Master In Multiplexer

MUX_NAND4_2WORST CASE

MUX_NAND4

Ma

ster In

/ Sla

ve O

ut

Master Out / Slave In

DATA

CLK

RESET

Q

QSET

CLR

DDATA_DFF

ADDR

/ADDR

SLAVE0 OUT

SLAVE1 OUT

SLAVE2 OUT

SLAVE3 OUT

SLAVE4 OUT

SLAVE5 OUT

SLAVE6 OUT

SLAVE7 OUT

MUX_NOR8WORST CASE

MISO_NOR

MISO_NOR

MISO Control

BUFFER2

BUFFER1

MISO_NORWORST Cload

DFF_CB

DFF_CB

BUFFER0/Xmit_EN

Q

QSET

CLR

D

11

Schematic

12

Layout

13

Verification

14

Verification

15

MOSI Simulation

16

MISO Simulation

17

Cost Analysis

• Time spent on each phase of project– Verifying Logic: 4 weeks– Verifying timing: 1 long

night– Layout: 2 long nights– Post-Extracted Timing: 2 long

nights– LVS Success on First Run

with No Errors: Priceless

18

Lessons Learned

• Flip-Flops require special attention• Start Early• Work Together• Start Early• Routing is good fun

19

Summary

• Our circuit is within spec.– Clock > 200MHz– 316 x 274 μm– 12.9mW @ 14.9 W/cm2

• Potential Improvements:– Stabilization D-Flip-Flops– Parity Check– Tri-state Buffer output

20

Improvements

ENB

ENB

ENB

ENB

ENB

ENB

ENB

ENB

b1

b2

b3

b4

5678

DE

CO

DE

R

a1

1

a2

23a

3

4a

4

b1

b2

b3

b4

5678

EN

B

EN

B

EN

B

EN

B

EN

B

EN

B

EN

B

EN

B

MASTER DATA IN

MA

ST

ER

DA

TA

OU

T

SLAVE DATA IN

SLAVE DATA OUT

21

Acknowledgements• Thanks to Cadence Design Systems.• Thanks to Professor David Parent for his

support.• Thanks to Morris Jones, for his State Machine

intervention.• Thanks to Dr. T’s MIST Lab.• Thanks to the janitorial staff of SJSU.• Thanks to Coca-Cola and Gordon Biersch.• Thanks to Nick’s Pizza and the ghetto pizza

place across from the Subway we used to go to before the oneopened in the Student Union.

• Thanks to Microsoft, Bungie, and Halo 2.

22

Tenacious EE

Strikes Again

1 serial decoder & multiplexer ryan bruno gly cruz frank gurtovoy christopher plowman advisor:...

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