1 scalable high-throughput sram-based architecture for ip-lookup using fpga author: hoang le;...
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![Page 1: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/1.jpg)
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Scalable high-throughput SRAM-based architecture for
IP-lookup using FPGA
Author: Hoang Le; Weirong Jiang; Prasanna, V.K.;Publisher: FPL 2008. Field Programmable Logic and Applications, 2008. Presenter: Yu-Ping ChiangDate: 2008/12/03
![Page 2: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/2.jpg)
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Outline
Binary-tree-based IP LookupMappingSearching
ArchitectureCache based
PerformanceThroughputComparison
![Page 3: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/3.jpg)
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Binary-tree-based IP Lookup Base on Binary Search Tree Property
Each node has a value. Left sub-trie nodes contain only smaller values. Right sub-trie nodes contain only greater values. Element can found in (1+logN) operations.
Pre-compute Pad prefixes to 32 bits with 1s. Padded bits. Sort with
concatenation of prefix and padded bits.
![Page 4: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/4.jpg)
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Binary-tree-based IP Lookup Build Binary Search Tree
Full binary tree without last level. Left-aligned .
=>complete tree
12-N
levellast in nodes of #
1log
(height) levels of # n
Nodes of # N
1-n
2
N
2
2 1
n
2
2 1
n
![Page 5: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/5.jpg)
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Binary-tree-based IP Lookup
.
12 2 n
△12 2 n
12 2n
12-N
levellast in nodes of #
1log
(height) levels of # n
Nodes of # N
1-n
2
N
2
2 1
n
△
![Page 6: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/6.jpg)
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Binary-tree-based IP Lookup .
12 2 n
12 2 n
12 2n
12 1 n
12 1 n
12-N
levellast in nodes of #
1log
(height) levels of # n
Nodes of # N
1-n
2
N
2
2 1
n
△
![Page 7: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/7.jpg)
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Binary-tree-based IP Lookup Recursive find root
12 2 n
12 2 n
12 2n
12 1 n
12 1 n
12-N
levellast in nodes of #
1log
(height) levels of # n
Nodes of # N
1-n
2
N
![Page 8: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/8.jpg)
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Binary-tree-based IP Lookup
422
1)12(8
418log
8
14
14
2
n
NStep 1:
x = 4-1+1 =4
4
01111111/011 (Prefix length)
![Page 9: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/9.jpg)
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Binary-tree-based IP Lookup
222
1)12(4
314log
4
13
13
2
n
NStep 2:
x = 2-1+1 =2
01011111/1014
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![Page 10: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/10.jpg)
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Binary-tree-based IP Lookup
4
6
7
8
2
5 3 1
![Page 11: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/11.jpg)
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Binary-tree-based IP Lookup Search
4
6
7
8
2
5 3 1
01111111/011Step 1: IP=01001010
≦ >Not MATCH!!
![Page 12: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/12.jpg)
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Binary-tree-based IP Lookup Search
4
6
7
8
2
5 3 1
01011111/101
Step 2: IP=01001010
>≦Not MATCH!!
![Page 13: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/13.jpg)
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Binary-tree-based IP Lookup Search
4
6
7
8
2
5 3 1
01001111/101
Step 3: IP=01001010
≦Match!!Continue search for longer matching.
![Page 14: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/14.jpg)
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Binary-tree-based IP Lookup Search
4
6
7
8
2
5 3 100011111/011
Step 4: IP=01001010
≦Match!!
Not MATCH!!
![Page 15: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/15.jpg)
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Binary-tree-based IP Lookup Search:
4
6
7
8
2
5 3 1
Match!!
Property:
ex: 1011* and 101*→10111111 and 10111111 (=)
1010* and 101*→10101111 and 10111111 (<)Left brench
![Page 16: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/16.jpg)
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Outline
Binary-tree-based IP LookupMappingSearching
ArchitectureCache based
PerformanceThroughputComparison
![Page 17: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/17.jpg)
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Architecture Pipelining
Memory of each stage contains one Binary Search Tree level nodes.
Dual read/write port Content of each entry:
Padded prefix Prefix length
Data forward to next stage: IP address Memory address Previously longest matched prefix information.
![Page 18: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/18.jpg)
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Architecture Pipelining
Memory of each stage contains one Binary Search Tree level nodes.
Dual read/write port Content of each entry:
Padded prefix Prefix length
Data forward to next stage: IP address Memory address Previously longest matched prefix information.
![Page 19: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/19.jpg)
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Architecture Cache based
Most recently searched packets. Update when:
Route update related to cached entry. Cache miss.
![Page 20: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/20.jpg)
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Outline
Binary-tree-based IP LookupMappingSearching
ArchitectureCache based
PerformanceThroughputComparison
![Page 21: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/21.jpg)
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Performance Throughput
Without caching 324 MLPS, 100 Gbps 162 MHz Minimum packet size of 40 bytes.
With 1% routing entries cached 4 packets processed per clock
=> 4*324=1.3GLPS, 416 Gbps
![Page 22: 1 Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA Author: Hoang Le; Weirong Jiang; Prasanna, V.K.; Publisher: FPL 2008. Field](https://reader035.vdocuments.mx/reader035/viewer/2022062714/56649d425503460f94a1d5c7/html5/thumbnails/22.jpg)
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Performance Comparison
Architecture # slices BRAM # prefix Throughput
Ring architecture 1405(2.3%) 530 80K 125 MLPS
State of art on FPGA 14274(22.7%) 254 80K 263 MLPS
Non-cache-based 2009(3.2%) 539 228K 324 MLPS
Cache-based 7982(12.7%) 539 228K 1.3 GLPS
Non-cache-based with SRAM 1813(2.9%) 311 2M 324 MLPS
Cache-based with SRAM 7713(12.3%) 311 2M 1.3 GLPS