1 programmable modules specification of … · pla state register clk x z y y k p n p present state...

1PROGRAMMABLE MODULES

• SPECIFICATION OF PROGRAMMABLE COMBINATIONALAND SEQUENTIAL MODULES

1. psa

2. rom

3. fpga

• THE WAY THE MODULES ARE PROGRAMMED

• NETWORKS OF PROGRAMMABLE MODULES

• EXAMPLES OF USES

Introduction to Digital Systems 12 – Programmable Modules

2

PROGRAMMABLE SEQUENTIAL ARRAYS (psa)

PLA

State register

clk

zx

Yy

k

p

n

p

next statepresent state

inputs outputs

PSA

Figure 12.1: PROGRAMMABLE SEQUENTIAL ARRAY (psa).


3Example 12.1: IMPLEMENTATION OF SEQUENTIAL SYSTEMS USING psas

• SEQUENCE GENERATOR

INPUTS: x ∈ {0, 1}OUTPUTS: z ∈ {0, 1, 3, 6, 7, 10, 14}

FUNCTION: The transition and output functions

x = 0 : z = 0 → 10 → 14 → 7 → 0 · · ·

x = 1 : z = 1 → 10 → 3 → 6 → 1 · · ·

x = 0 : z = 0000 → 1010 → 1110 → 0111 → 0000 · · ·

x = 1 : z = 0001 → 1010 → 0011 → 0110 → 0001 · · ·


4

CLK

z3z2z1z0

0

0

0

0

1

0

1

0

1

1

1

0

0

1

1

1

State

CLK

z3z2z1z0

State

0

0

0

1

1

0

1

0

0

0

1

1

0

1

1

0

(a) Case x = 0

(b) Case x = 1

0 10 14 70 10 14 7

1 10 3 6 1 10 3 6

Figure 12.2: TIMING SEQUENCES IN Example 12.1.


5

Example 12.1 (cont.)

y k = 0 k = 10 10 − k

1 − 10 k

3 − 6 x

6 0 1 k

7 0 1 k

10 14 3 k

14 7 − x

Y K

y ∈ {2, 4, 5, 8, 9, 11, 12, 13, 15} – don’t care states

K = xy3y2 xy′3y′2y1 ky′1 ky′3y2 ky3y

′2

Y3 = y′1 y′2k′

Y2 = y′3y′2y1 y3k

′

Y1 = y′2 y3

Y0 = y3k y2k y3y2


6

11

12

13y

3 k

y3 k’

y’2 k’

output

K

STATE REGISTER

next state

present state

CLK

9

14x

15

16

17

18

y3

y2

xy’3y’

2y

1

ky’1

ky’3

y2

k

-- programmable connection

y3

-- connection made

y2

y1

y0

(from state register)

xk

9

10

y’

y3

y2

y’2

y1y

0

5

6

7

8

y2k

1

y’2

y3

1

2

3

4

568 7

Y1

Y0

Y2

Y3

124 3

z0

z1z

2z

3

y1

y0

y2

y3

y3

y’2k

Figure 12.3: psa IMPLEMENTATION IN Example 12.1.Introduction to Digital Systems 12 – Programmable Modules

7

READ-ONLY MEMORIES (rom)

AddressInputs

Outputs

x n-1

z k-1

x 1

x 0

z 0

ROM kX2n

En

E

Figure 12.4: READ-ONLY MEMORY (rom)


8EXAMPLE 12.2

Address Contentsx z

000 1011001 1101010 0111

011 1000100 0000101 1111110 1111111 1011


9

x1 x0E z1 z0z2z3

0 1 0 1

1 1 0 0

1 0 1 1

0 0 1 0

00

0 1

1 0

1 1

1

1

1

1

0 - - Z Z Z Z

Gnd

NOR Array

Gnd

Gnd

0 1 0 1

1 1 0

11 0 1

0

0 0 1 0

0

1

2

3

1

0

word 0

word 1

word 2

word 3

pull-updevices

Vdd

x1

x0

enable

Bin

ary

deco

der

three-statebuffers

E

z1 z0z2z3

(a)

(b)

Figure 12.5: mos IMPLEMENTATION OF A 4 × 4 READ-ONLY MEMORY: a) THE FUNCTION; b) THE CIRCUIT.


10IMPLEMENTATION OF SWITCHING FUNCTIONS USING roms

Input/output mapping:

0 0 0 0 0 0 0 0 0 1

1 1 0 0 1

0 1 1 0 1

1 1 1 1 1

01

349

356

511

01

78

BIN

AR

Y D

EC

OD

ER

z1 z0z2z3

z1 z0z2z3

y1 y0y2y3

x1 x0x2x3

cout

cin

+

cout

cin

x1

x0

x2

x3

y1

y0

y2

y3

111101010

11001

+101110101

1 1 0 0 1

ROM (512x5)

Figure 12.6: rom-BASED IMPLEMENTATION OF A 4-BIT ADDER.


11IMPLEMENTATION OF SEQUENTIAL SYSTEMS USING roms

INPUTS: x = (x1, x0), xi ∈ {0, 1}OUTPUTS: z ∈ {0, 1, }STATE: y = (y1, y0), yi ∈ {0, 1, }

FUNCTION: The transition and output function

PS x1x0

y1y0 01 10 1100 01,0 10,1 10,001 00,0 11,1 11,010 11,0 10,0 00,111 10,0 00,0 11,1

Y1Y0, z

NS, Output


12

(a)

ROM16 X 3

CLK

next state

0

1

2

3

zpresent state

x1

x0

S

Y1

Y0

y1

y0

(b)

0000 - - -0001 0 1 00010 1 0 10011 1 0 00100 - - -0101 0 0 00110 1 1 10111 1 1 01000 - - -1001 1 1 01010 1 0 01011 0 0 11100 - - -1101 1 0 01110 0 0 01111 1 1 1

ROM address ROM contents

outputnext state

y1y

0x1

x0 Y

1Y0

z

Figure 12.7: rom-based implementation of a sequential system: a) network; b) rom contents.


13TYPES OF rom MODULES

• MASK-PROGRAMMED rom

• FIELD-PROGRAMMABLE rom (proms)

• ERASABLE rom (eprom)

• ELECTRICALLY ERASABLE rom(flash-memory) or eeprom


14NETWORKS OF PROGRAMMABLE MODULES

f1(x4, x3, x2, x1, x0) = one-set(0,3,11,12,16,23,27)

f0(x4, x3, x2, x1, x0) = one-set(5,7,19,21,31)

rom MODULE: 8 × 2

x = (x(0), x(1))

x(0) = (x4, x3)

x(1) = (x2, x1, x0)


15

01234567

00010000

ROM3

00000001

10000001

ROM2

00010100

00011000

ROM1

00000000

10010000

ROM0

00000101

E E E E

DECODER

3 2 1 0

1 0

En

Row

f 1

f 0

3

3333

0 1 011

0 0 1 0

1 0Z Z Z Z Z Z

1

0

1E=

x4 x3 x2 x1 x0

Figure 12.8: rom-BASED NETWORK FOR THE IMPLEMENTATION OF TWO FUNCTIONS.


16

ROMN-1

ROMN-2

ROM0

En En En

DECODEREn k

kkk

N = 2n-k

N-1 N-2 0

n-k

f

xk-1 x0, . . . ,xn-1 xk, . . . ,

* three-state outputs

* * *

(a)

ROMN-1

ROMN-2

ROM0

En En Enkkk

N = 2n-k

xk-1 x0, . . . ,

xn-1 xk, . . . ,

f

MULTIPLEXEREn

N-1 N-2 0

k

1

n-k

(b)

E

E

Figure 12.9: IMPLEMENTATIONS OF FUNCTIONS WITH n VARIABLES: a) roms AND DECODER; b) roms AND MULTIPLEXER


17LARGE NUMBER OF SFs

ROM3

Enn

xn-1 x0, . . . ,

n

ROM2

Enn

ROM1

Enn

f11

f0

E

Figure 12.10: rom-BASED IMPLEMENTATION OF LARGE NUMBER OF SWITCHING FUNCTIONS.


18

FIELD PROGRAMMABLE GATE ARRAYS (FPGA)

Input/Output Blocks

Input/Output Blocks

Input/Output B

locks

Input/Output B

locks

ProgrammableLogic Block

Wiring channel

Sw

itches

Switch matrix

Figure 12.11: ORGANIZATION OF AN fpga chip.


19BASIC APPROACHES IN PROGRAMMING OF FPGAs

- ON-CHIP STATIC RAM LOADED WITHCONFIGURATION BIT PATTERNS (sram-fpgas). (volatile)

- ANTIFUSE-PROGRAMMED DEVICES PROGRAMMEDELECTRICALLY TO PROVIDE CONNECTIONS THAT DEFINE CHIP CON-FIGURATION

- ARRAY-STYLE eprom and eeprom PROGRAMMED DEVICESUSING SEVERAL plas AND A SHARED INTERCONNECTMECHANISM


20

1

Closed switch

TransistorSRAM cell

0

Open switch

(a)

0123

MUX

1 0

abcd

y=d

1 1

SRAM cells

011

0

1

1

0

0abc

y=f(a,b,c)

(b) (c)

LUT (Look-Up Table)

Dec

oder

SRAM cells

Figure 12.12: sram fpgaPROGRAMMABLE COMPONENTS: (a) Switch. (b) 4-input multiplexer. (c) Look-up table (LUT).


21Example: XILINX XC2000

D QS

KR

Look -Up Table(LUT)

G

F

K

Y

X

Outputs

Reset

Set

SRAM-controlled multiplexer

A

B

C

D

CLK

B

A

CK

D

X

Y

CLB CLB symbol

Figure 12.13: A CONFIGURABLE LOGIC BLOCK (CLB) (Courtesy of Xilinx, Inc.)


22

A 4-variablefunction

F

A

B

C

D

Q

G

G


F

A

B

C

D

Q


A

B

C

D

Q


F

A

C

D

Q


A

C

D

Q

G

MUX

B

(c)

(b)

(a)

Figure 12.14: sram-fpga options in generating functions: (a) One 4-variable function. (b) Two 3-variable functions. (c) Selectionbetween two functions of 3 variables. (Courtesy of Xilinx, Inc.)


23PROGRAMMABLE INTERCONNECT

1. DIRECT INTERCONNECTIONS BETWEEN HORIZONTALLY ANDVERTICALLY ADJACENT clbs– PROVIDE FAST SIGNAL PATHSBETWEEN ADJACENT MODULES

2. GENERAL-PURPOSE INTERCONNECT CONSISTS OF VERTICAL ANDHORIZONTAL WIRING SEGMENTS BETWEEN SWITCH MATRICES

3. LONG VERTICAL AND HORIZONTAL LINES SPAN THE WHOLE clbARRAY


24

CLBB

A

CK

D

X

YCLB

CLB CLB

CLB CLB

SwitchMatrices

Horizontallong line

Global longline

Two verticallong lines

General-purposeinterconnect

General-purposeinterconnect

Direct connection

Figure 12.15: PROGRAMMABLE INTERCONNECT. (Courtesy of Xilinx, Inc.)


25Example 12.5: BCD ADDER MODULE

• IMPLEMENT A ONE-DIGIT BCD ADDER USING A sram-fpgaMODULEOF XC2000 TYPE

INPUTS: x = (x3, x2, x1, x0), xj ∈ {0, 1}, x ∈ {0, . . . , 9}y = (y3, y2, y1, y0), yj ∈ {0, 1}, y ∈ {0, . . . , 9}cin ∈ {0, 1}

OUTPUTS: s = (s3, s2, s1, s0), sj ∈ {0, 1}, s ∈ {0, . . . , 9}cout ∈ {0, 1}

FUNCTION: x + y + cin = 10cout + s

• COMPUTE 16u + v = x + y + cin ∈ {0, . . . , 19} using a 4-bit binary adder


26


• THREE CASES:

u = 0 v ≤ 9 s = v cout = 0u = 0 v > 9 s = v − 10 = (v + 6) mod 16 cout = 1u = 1 s = v + 16 − 10 = v + 6 cout = 1

⇒ BCD OUTPUT

s =

(v + 6)mod16 if u = 1 or v ≥ 10v otherwise

cout =

1 if u = 1 or v ≥ 100 otherwise

THE CONDITION u = 1 or v ≥ 10 CORRESPONDS TO SWITCHINGEXPRESSION

t = u v3v2 v3v1


27


ut

3s

2s

1s

c out

0s

3x

3y

2x

2y

1x

1y

0x

0y

cin

0

4-bi

t Add

er

3-bi

t Add

er

2v

1v

0v

3v

Figure 12.16: IMPLEMENTATION OF BCD ADDER MODULE


28


• SIMPLIFICATION OF THE 3-BIT ADDER

s3 = v3 ⊕ t(v2 v1)

s2 = v2 ⊕ tv′1s1 = v1 ⊕ t

MOREOVER,

s0 = v0

cout = t


29

CLB CLB

CLB CLB

CLB CLB

CLBu

t

3s

2s

1s

cin

0s

0x

0y

1x

2y2x

1y

3x

3y

3v

1v

0v

A

X

Y

B

C

K D

3v

3v

2v

2v

2v

2v

1v

1v

1v

t

t

t

u

1vcout

Figure 12.17: fpga IMPLEMENTATION OF BCD ADDER MODULE


30DESIGN WITH FPGAs

INVOLVES INTENSIVE USE OF CAD TOOLS AND MODULE LIBRARIES

Design entry : A SCHEMATIC ENTRY OR A BEHAVIORAL DESCRIPTION

Implementation :

• PARTITION OF DESIGN INTO SUBMODULES THAT CAN BE MAPPEDONTO clbs,

• PLACEMENT OF SUBMODULES ONTO CHIP, AND

• ROUTING OF SIGNALS TO CONNECT THE SUBMODULES

Design verification :

• IN-CIRCUIT TESTING

• SIMULATION, AND

• TIMING ANALYSIS


1 programmable modules specification of … · pla state register clk x z y y k p n p present state...

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