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Memory Design Memory Design

EE 208 – Logic Design

Chapter 7

Sohaib Majzoub

2Combinational PLDs and PLAsCombinational PLDs and PLAs

• So far the logic you design is fixed before fabrication and it cannot be altered or changed.

• PLD stands for programmable logic device, and PLA stands for programmable logic array.

• PLD/PLA is a programmable logic that allows the designer to modify and change the underlying logic to implement any function after fabrication.

• PLD is a two level AND-OR device that can be programmed to realize any sum of products logic expression.

• Some of the limitations: the number of inputs (n), the number of outputs (m), and the product terms.

3PLDs and PLAsPLDs and PLAs

• Expressed as nxm PLA with p products: 4x3 PLA (not programmed yet)

4PLDsPLDs• A compact representation of 4x3 PLA:

5Programming PLDsProgramming PLDs• At each corner there is a fuse that can be blown

(disconnected) to build the targeted logic function. • Once programmed it cannot changed.

6Sequential PLDsSequential PLDs

• In addition to the AND-OR logic, DFFs are added to implement sequential state machine.

7Memory DesignMemory Design

• Memories are circuits or systems that store digital information in large quantities.

• Different forms: SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), ROM (Read Only Memory), EPROM (Erasable Programmable ROM), E2PROM (Electrically Erasable Programmable ROM), and Flash (a specific type of E2PROM).

• Most of these different types have same structure, organization and access mechanism, but different memory cell.

8RAM and ROMRAM and ROM

• Random Access Memories: memory locations (addresses) can be accessed in random order at a fixed rate, independent of physical location, for both reading or writing.

• RAM are volatile memories, the information is lost if power supply is interrupted.

• Read Only Memories: have the same access property as RAM (Random Access), however Read Only Memories or ROMs are a non-volatile type of memory.

9RAMRAM

• Two most common types: SRAM and DRAM.

• SRAM stores the logic value using Static CMOS gates (similar to flipflop circuits). SRAM is considered fast.

• DRAM stores the logic value in capacitors. Susceptible to Noise and Leakage current problems, (hence dynamic, contents need to be refreshed).

• It can be slower than SRAM, but can store much higher bit density (can reach up to 4x SRAM density).

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Static RAM Internal Structure

• Uses two back to back inverters as storage cell• Can also be built using D-latch

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Dynamic RAM Dynamic RAM CellCell

Bit Line

Word Line

Pass Transistor

Storage Capacitor

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DRAM RefreshDRAM Refresh

Time

Vcap

Vcc

0 V

HIGH

LOW

0 stored1 stored

Refresh

13ROMROM

• The simplest form of ROMs are programmed before manufacturing and the contents cannot change after fabrication.

• PROM are programmable ROM, such that the memory can be programmed after fabrication to store the data.

• After programming, the data cannot change.• EPROM are erasable programmable ROM. All bit

can be erased by exposure to ultraviolet light.• They have transparent windows over the chip to

permit the UV radiation to get into the chip.

14E2PROME2PROM

• Electrically erasable PROM, instead of using UV light, the erasing process uses electrical means.

• Unlike EPROM, where the exposure to UV erases the whole ROM, E2PROM has an advantage is that it can be selectively erased.

15Memory OrganizationMemory Organization• The storage array or core is made up of simple cell

circuits arranged to share connections in horizontal rows and vertical columns.

• The horizontal lines, which are driven only from outside the storage array, are called wordlines, while the vertical lines, along which data flow into and out of cells, are called bitlines.

• A cell is accessed for reading or writing by selecting its row and column.

• Each call can store 0 or 1.• Memories may simultaneously select 1, 4, 8, 16, 32,

or 64 columns in one row, which are determined by decoding binary address information.

16Memory OrganizationMemory Organization

• In a memory cell array with [n,m] address has 2nx2m memory cells.

• The row decoder is an n-bit decoder with n address bits and 2n outputs connected to the wordlines.

• The column multiplexer has m-bit address that selects out of 2m columns, bitlines, which can be of 1, 4, 8, 16, 32, or 64 bits at the same time.

17Memory OrganizationMemory Organization

18Two Dimensional Decoding

0

Example: 256 bytes ROM (256 words 1 byte = 256 byte)

1 15. . . . . . . . . .

16 31

. .

. .

.

. .

. .

.

17

. .

. .

.

. . . . . . . . . .

240 255241 . . . . . . . . . .

4-to-16 Row Decoder

0

1

2

3

0

1

15

16-to-18-bit Column Multiplexer

8 bit lines

0123

0 1 15

D[7:0]

A0A1A2A3

A4

A5A6A7

19Two Dimensional Decoding

0

Example: 16Kbytes RAM (16K words 1 byte = 16Kbyte)

1 127. . . . . . . . . .

128 255

. .

. .

.

. .

. .

.

129

. .

. .

.

. . . . . . . . . .

16256 1638416257 . . . . . . . . . .

1

2

3

4

0

1

127

(7-to-128) decoder(128-to-1) 8-bit Column Multiplexer

8 bit lines

0123

0 1 127

D[7:0]

A00A01A02A03

A08

A09A10A11

5A12

0A07

6A13

456

A04A05A06

(7-t

o-12

8) d

ecod

er(1

-to-

128)

8-b

it R

ow D

eMul

tiple

xer

Input Data Bus

8 bit lines

8 bit lines

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21

22

23

24

25

26

27

28

29

30

31

32

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41Field Programmable Gate ArraysField Programmable Gate Arrays

42Field Programmable Gate ArraysField Programmable Gate Arrays

43Field Programmable Gate ArraysField Programmable Gate Arrays

44Field Programmable Gate ArraysField Programmable Gate Arrays

45Field Programmable Gate ArraysField Programmable Gate Arrays

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2.5D Memory Organization2.5D Memory Organization

• 2.5D Memory Organization• The memory organization shown for RAMs and ROMs above suffers from a problem of scale: it works fine when the

number of words in the memory is relatively small but quickly mushrooms as the memory is scaled up or increased in size. This happens because the number of word select wires is an exponential function of the size of the address. Suppose that the MAR is 10 bits wide, which means there are 1024 words in the memory. The decoder will need to output 1024 separate lines. While this is not necessarily terrible, increasing the MAR to 15 bits means there will be 32,768 wires, and 20 bits would be over a million.

• Fig. 1 shows a 16-word memory of 5-bit words using the conventional organization:

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• Notice that the decoder gets quite complicated because the number of lines coming out of it is an exponential function of the number of wires coming in. Imagine a 32-bit address! There would be 4 billion wires coming out.

• One way to tackle the exponential explosion of growth in the decoder and word select wires is to organize memory cells into a two-dimension grid of words instead of a one-dimensional arrangement. Then the MAR is broken into two halves, which are fed separately into smaller decoders. One decoder addresses the rows of the grid while the other decoder addresses the columns. Fig. 2 shows a 2.5D memory of 16 words, each word having 5 bits:

488 by 4 Memory 8 by 4 Memory

• 8 by 4 Memory

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Extend size of memory Extend size of memory

• Extend size of memory

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51ROMROM

• Truth Table

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Simple Encoder Simple Encoder

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Design of 4 to 8 ROMDesign of 4 to 8 ROM

• Design of 4 to 8 ROM

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