1 lic presentation memory aware task assignment and scheduling for multiprocessor embedded systems...

34
1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design [email protected] http://www.cs.lth.se/home/ Radoslaw_Szymanek

Upload: gloria-shields

Post on 20-Jan-2016

222 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

1

Lic Presentation

Memory Aware Task Assignment and Scheduling for Multiprocessor

Embedded Systems

Radoslaw Szymanek / Embedded System Design

[email protected]

http://www.cs.lth.se/home/Radoslaw_Szymanek

Page 2: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

2

Outline

• Introduction

• Problem Formulation and Motivational Example

• CLP Introduction

• CLP Modeling

• Optimization Heuristic and Experimental Results

• Conclusions

Page 3: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

3

System Level Synthesis (SLS)

• Multiprocessor embedded systems are designed using CPU’s, ASIC’s, buses, and interconnection links

• The application areas range from signal and image processing to multimedia and telecommunication

• Task graph representation for application

• The main design activities are task assignment and scheduling for a given architecture

• Memory constraints (code and data memory)

Page 4: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

4

SLS with memory constraints

annotated task graph

target architecture

P1

ROM RAM

P2

ROM RAM

P3

ROM RAM

A1

RAM

B1

L1

L2

Page 5: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

5

• Data dominated application represented as directed bipartite acyclic task graph

• Each task is annotated with execution time, code and data memory requirements

• Heterogeneous architecture

• Both tasks and communications are atomic and they must be performed in one step

• Find a good CLP model

• Find a good heuristic for memory constrained time minimization task assignment and scheduling satisfying all constraints

Problem Assumptions and Formulation

Page 6: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

6

Motivation

• SoC multiprocessor architectures

• Co-design methodology needs tool support

• Memory consideration to decrease cost and power consumption

• System Level design for fast evaluation

Page 7: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

7

Motivating example (memory)

task graph

DC2t

4

86

DC2

DC3

t

4

86

architecture

P1 L1

C1

C3 C2C2

P1L1P2

C3

P1L1P2

DC3t

4

86

t

4

86

DC2

DC3

P1 P2

P1 P2

DC1

ScheduleData Memory

Task - 1kB code memory, 4kB data memory, Communication - 2kB data memory

P2

Page 8: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

8

CLP Introduction

“Constraint programming represents one of the closest approaches computer science has yet made to the Holy Grail of programming: the user states the problem, the computer solves it.”

Eugene C. Freuder

CONSTRAINTS, April 1997

Page 9: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

9

CLP Introduction

• Relatively young and attractive approach for modeling many types of optimization problems

• Many heterogeneous applications of constraints programming exist today

• State decision variables which constitute to solution

• State constraints which must be satisfied by solution

• Search for solutions using knowledge you can derive from constraints

Page 10: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

10

Constraints properties

• may specify partial information — need not uniquely specify the values of its variables,

• non-directional — typically one can infer a constraint on each present variable,

• declarative — specify relationship, not a procedure to enforce this relationship,

• additive — order of imposing constraints does not matter,

• rarely independent — typically they share variables.

Page 11: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

11

A simple constraint problem

1. Specify all decision variables and their initial domains

CLP description

TP1, TP2, TP3 :: 1..2,

TS1, TS2, TS3 :: 0..10,

Cost :: 0..10,

Natural language description

There are three tasks, namely, T1, T2, and T3. Each of these tasks can execute on any of two available processors, P1 and P2. Tasks T1 and T2 send data to task T3.

The tasks should be assigned and scheduled in such a way that the schedule length does not exceed 10 seconds.

Page 12: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

12

A simple constraint problem

2. Specify all constraints and additional variables

The execution time of task T1 is four seconds on processor P1 and two seconds on processor P2.

Task T2 requires three and five seconds to complete execution on processor P1 and P2 respectively.

Task T3 always needs three seconds for execution.

If TP1 = 1 then TD1 = 4.

If TP1 = 2 then TD1 = 2,

If TP2 = 1 then TD2 = 3,

If TP2 = 2 then TD2 = 5,

TD3 = 3,

Page 13: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

13

A simple constraint problem

Tasks T1 and T2 must execute on different processors.

Tasks T1 and T2 send data to task T3. If two communicating tasks are executed on different processors there must be at least one second delay between them so the data can be transferred.

The tasks should be assigned and scheduled in such a way that the schedule length does not exceed 10 seconds.

TP1 != TP2,

If TP1 != TP3 then D1 = 1 else D1 = 0,

TS1 + TD1 + D1 <= TS3,

[…],

Cost >= TS1 + TD1,

Cost >= TS2 + TD2,

Cost >= TS3 + TD3.

Page 14: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

14

Search Tree

Page 15: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

15

Modeling

• Constraint Logic Programming (finite domain, CHIP solver)

• Global constraints (cumulative, diffn, sequence, etc.) reduce model complexity of the synthesis problem and exploit specific features of the problem

• Global constraints are useful for modeling placement problems and graph problems

• Problem-specific search heuristic for NP-hard problem

Page 16: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

16

CLP Model

Decision variables for task

• TS – start time of the task execution

• TP – resource on which task is executed

• TDP – exact placement of task local data in memory

Additional variables for task

• TD – task duration

• TCM and TDM denote the amount of code and data memory for task execution

Page 17: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

17

CLP Model

Decision variables for data

• DS – start time of the data communication

• DB – resource on which data is communicated

• DCP and DPP – exact placement of data in memory of the producer and consumer processor

Additional variables for data

• DD – data communication duration

Page 18: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

18

CLP Model – Task Requirements

TS

TP

TD

1

time

PU

a) execution time

TP

1

TCM

PU

CM

b) code memory

TS

TDP

TD

TDM

DM

c) data memory

time

Page 19: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

19

CLP Model – Data Requirements

DS

DB

DD1

CU

communication time

timeTSp

DPPDA

DM

data mem (prod)

timeDS+DD DS

DCPDA

DM

data mem (cons)

time

TSc + TDc

Page 20: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

20

Simple Example

P2

P1

P2

P1

B1T2

C1T3T1

D1_eD1_p

D2_p D2_c

D3_e

D2_eD1_c

T1

D1 D2

T2 T3

Diffn constraint

Page 21: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

21

Code Memory Constraint

Processor

Code Memory Limit

T5

T2T7 T6

T3T4

T8

T1

Page 22: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

22

Constraints types

• precedence constraints

• processing resources constraints

• communication resource constraints

• pipelining constraints

• code memory constraints

• data memory constraints

Page 23: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

23

data memory estimate no. 1 holds?

Task Assignment and Scheduling Heuristic

Undo all decision – choose a task which consumes the most data

data memory estimate no. 2 holds?

Assign data memory

Schedule communications that Ti is minimal

Assign the task to a processor with the minimal implementaion cost ci

Choose a task from ready task set with min(max(Ti)) – minimize schedule length

Y

Y N

N

Page 24: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

24

Execution Cost

1IndL

LIndL )1(*

LIndL-

-LIndL-)1(*

-L Ind 1-

1

12

22

21

1

in

in

in

in

in

in

in

in

in

in

in

in

in

in

in

in

exec

ATS

dATS

dInd

ACM

cATS

d

ACM

c

IndATS

d

ACM

cACM

c

c

Ind = LowTS/PTS – LowCM/PCM

ATS = available time slots, ACM – available code memory

i-th task, n-th processor

Page 25: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

25

Data and Communication Cost

otherwise0

32

procMprocAM

0ΔdprocAM

Δdc

ni

n

i

data

i-th task, n-th processor

iD

2

)imax(DD)imin(DDccomm

Page 26: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

26

• Estimate no. 1

where S (Sn) is a set of tasks already scheduled on a processor (processor Pn), tasks tj are direct successors of task ti, and dij is amount of data communicated between ti and tj.

• Estimate no. 2 uses the global constraint diffn and it takes time into account

Estimates

StSt

ijn

inj

dP,

1 )(

Page 27: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

27

MATAS System

Page 28: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

28

Synthesis Results - H.261 example

DCT

FB1

IN

BMA

FIR

PRAE Q

IQ IDCT REK FB2

C96

553

64

96

96

96 96

96

96

96 96 96

Video Coding Algorithm H.261

Page 29: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

29

Experimental results H.261 example

EXP.

#

ALG

ORIT

HM

PIPE

LIN

E D

EPTH

DEA

DLI

NE

AVER

AG

E EX

ECU

TIO

N

TIM

E

D

ATA

MEM

ORY

TIM

E

D

ATA

MEM

.

1 both 1 2871 2871 2683 - -

2 greedy 4 6743 1686 3812 0 0

3 memory 4 6781 1696 3259 1% -16%

Page 30: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

30

Experimental results(random task graphs)

Experiment setup Result

Each CPU Data Mem. Code Mem.

Exp.

#

algo

rith

m

data

m

emor

y si

ze [

kb]

code

m

emor

y si

ze [

kb]

dead

line

[ms]

utili

zatio

n [k

b]

peak

[kb

]

utili

zatio

n [k

b]

peak

[kb

]

# s

olut

ions

1 greedy 100 100 171 243 78 319 98 22

2 greedy 75 100 182 233 68 310 96 8

3 greedy 100 75 169 257 79 294 75 4

4 greedy 75 75 - - - - - 0

5 memory 75 75 295 222 64 247 65 22

Page 31: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

31

Main Contributions

• Definition of the extended task assignment and scheduling problem

• Inclusion of memory constraints to decrease the cost for data dominated applications

• Specialized search heuristic to solve resource constrained task assignment and scheduling

• CLP modeling framework to facilitate an efficient, clean, and readable problem definition

Page 32: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

32

Conclusions and Future Work

• The synthesis problem modeled as a constraint satisfaction problem and solved by the proposed heuristic,

• Good coupling between model and search method for efficient search space pruning,

• Memory constraints and pipelined designs taken into account,

• Heterogeneous constraints can be modeled in CLP, important advantage over other approaches

Need for our own constraint engine implementation, approximate solutions, mixture of techniques

Need for better lower bounds, problem specific global constraints, designer interaction during search

Page 33: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

33

Lic Presentation

Memory Aware Task Assignment and

Scheduling for MultiprocessorEmbedded Systems

Radoslaw Szymanek / Embedded System Design

[email protected]

http://www.cs.lth.se/home/Radoslaw_Szymanek

Page 34: 1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design Radoslaw.Szymanek@cs.lth.se

34

Related Work

• J. Madsen, P. Bjorn-Jorgensen, “Embedded System Synthesis under Memory Constraints”, CODES ‘99 (GA, only RAM)

• S. Prakash and A. Parker, “Synthesis of Application-Specific Heterogeneous Multiprocessor Systems”, VLSI Signal Processing, ‘94 (MILP, no ASIC’s, optimal)