1 konstantin stefanov, cclrc rutherford appleton laboratory lcfi detector r&d status report wp2...
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1Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
LCFI Detector R&D Status Report
LCFI Detector R&D Status Report
WP2 – Sensor Development
WP3 – Readout and Drive Electronics
WP4 – External Electronics
WP5 – Integration and Testing
Introduction to the present Detector WP
Work during the last 6-month period
Current activities
Plans
2Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Introduction to the Detector R&D Work Packages
WP2Sensor Development
CPCCD and ISIS
•Design•Simulations•Interaction with the manufacturer
WP3Readout and Drive
Electronics
•Design•Simulations•Support
WP4External Electronics
•Circuit Design•PCB Design•Simulations on clock propagation in CPCCD•CPCCD transformer drive
WP5Integration and Testing
•Bump Bonding (VTT)•Tests of CPCCD, readout chips and hybrid assemblies•Firmware and software for tests•Data analysis
3Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
First CPCCD (CPC1) manufactured by e2V:
20 μm square pixels
750 (H) 400 (V) pixels
CMOS readout chip (CPR1) designed at RAL
Bump-bonded by VTT (Finland)
CPC1 clocked to 25 MHz stand-alone, metal-strapped gates for efficient clock propagation
CPC1 optimised for low clock amplitude and low drive power – works with 1.9 Vpp clocks
Readout chip has amplifiers, 5-bit ADCs and FIFO per column
Main detector R&D at LCFI:
Hybrid assembly with Column-Parallel CCD (CPCCD) and CMOS ASIC
Bump-bonded CPC1/CPR1 in a test PCB
CPCCD Work
4Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
5.9 keV X-ray hits, 1 MHz column-parallel readout
Voltage outputs, non-inverting (negative signals)
Noise 60 e-Charge outputs, inverting (positive signals)
Noise 100 e-
First time e2V CCDs have been bump-bonded
High quality bumps, but assembly yield only 30% - reason still unclear
Differential non-linearity in ADCs (100 mV full scale) – addressed in CPR2
Bump bonds on CPC1 under microscope
CPCCD Work
5Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Yield summary from batch 1 Assembly Left hand side chip Right hand side chip CCD
1 OK OK OK
2 OK OK Problem
3 OK OK Problem
4 OK Low resistance CGND-VDD Problem
5 OK OK OK
6 OK Short CGND-VDD OK
7 Subtle defect (VPRE-VDC) Short CGND-VDD OK
CPCCD Work – Hybrid Assembly Testing (WP5)
Summary: ● Only 4 complete assemblies fully working, out of 13 (30% yield)● Right hand side chips show problems:
● Short between the power supplies or defective in other ways● Parasitic connection to SS
● Readout chips diced by IBM exhibit yield close to 100%● All CCDs have been DC probed at e2V – 23 good chips (out of 24). ● Dicing has been checked, does not seem to be the problem● What is the explanation?
6Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Possible problem explanation (1)
CGND pad, parasitic connection to SS? Mechanical damage?
SS
Right hand side of the CPCCD
CPCCD Work – Hybrid Assembly Testing (WP5)
7Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Possible problem explanation (2)
CGND pad, parasitic connection to SS? Mechanical damage?
CGND
SS
Right hand side of the CPCCD
CPCCD Work – Hybrid Assembly Testing (WP5)
8Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Right-hand side CPR1, 100 mA between CGND and SS (360 Ω between them)
Thermal images
Batch 1, Assembly 2, right hand side chip
CPCCD Work – Hybrid Assembly Testing (WP5)
9Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Clock bus
Main clock wire bonds
Main clock wire bonds
CPR1 CPR2
Temperature diode on
CCD
Charge injection
Four 1-stage and 2-stage SF in adjacent
columns
Four 2-stage SF in adjacent columns
Standard Field-enhanced Standard
No connections
this side
Image area
Extra pads for clock monitoring and
drive every 6.5 mm
CPC2 Design
Three different chip sizes with common design:
CPC2-70 : 92 mm 15 mm image area
CPC2-40 : 53 mm long
CPC2-10 : 13 mm long
Compatible with CPR1 and CPR2
Two charge transport sections
Choice of epitaxial layers for different depletion depth: 100 .cm (25 μm thick) and 1 k.cm (50 μm thick)
Baseline design allows few MHz operation for the largest size CPC2
10Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
CPC1 did not have optimal drive conditions due to single level metal
Novel idea from LCFI for high-speed clock propagation: “busline-free” CCD:
The whole image area serves as a distributed busline
50 MHz achievable with suitable driver in CPC2-10 and CPC2-40 (L1 device)
Transformer drive for CPC2, will evolve into dedicated driver chip
Φ1 Φ2
Φ1 Φ2
Level 1 metal
Polyimide
Level 2 metal
Φ2 Φ1
Φ2 Φ1
To multiple
wire bonds
To multiple
wire bonds
1 mm
CPC2 Clock Driving
11Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
CPC2 + ISIS1 Wafer
2 ISIS chips
CP
C2-70
CP
C2-40
CPC2-10
12Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
CPC2 + ISIS1 Manufacture
● Delivery was scheduled to March 2005
● Delays at e2V due to equipment breakdown
● Operator error caused the entire batch to be scrapped
● e2V immediately started new batch at their expense
● First devices expected mid July
● “Bad batch” processed to 1st polysilicon, could be used for thinning studies
● New diamond grinder at e2V comes next month
13Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Beam-related RF pickup is a concern for all sensors converting charge into voltage during the bunch train;
The In-situ Storage Image Sensor (ISIS) eliminates this source of EMI:
Charge collected under a photogate;
Charge is transferred to 20-pixel storage CCD in situ, 20 times during the 1 ms-long train;
Conversion to voltage and readout in the 200 ms-long quiet period after the train, RF pickup is avoided;
1 MHz column-parallel readout is sufficient;
In-situ Storage Image Sensor (ISIS)
14Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Additional ISIS advantages:
~100 times more radiation hard than CCDs – less charge transfers
Easier to drive because of the low clock frequency
ISIS combines CCDs, active pixel transistors and edge electronics in one device: specialised process
Development and design of ISIS is more ambitious goal than CPCCD
Plus additional logic for row selection and clock gating (not shown)
In-situ Storage Image Sensor (ISIS)
15Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
ISIS1
“Proof of principle” device (ISIS1) designed by e2V:
1616 array of ISIS cells with 5-pixel buried channel CCD storage register each;
Cell pitch 40 μm 160 μm, no edge logic (CCD process)
Size 6.5 mm 6.5 mm
● Test board designed by a Sandwich student at RAL
● ISIS1 fits into 100-pin socket
● Software being written
16Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Simulations on CMOS-based ISIS
● Targeting 0.25 μm or 0.18 μm process● 3.3 V maximum voltage
● 6.5 nm SiO2 as both CCD and transistor
gate dielectric ● Non-overlapping polySi gates (0.35 μm
gap, 0.25 μm design rules )
Keeping in touch with:
● Jim Janesick (Sarnoff) – simulations, advice, possibly MPW
● Chronicle Technology – design
● e2V: David Burt, Ray Bell – CCD experts
● “Fine Pixel ISIS” – new concept from e2V
Simulations for the next generation
CMOS-based ISIS2
● Thin oxide unfavourable for the CCD
structure – dual gate oxide possible ● LCFI solution – modify the buried channel
implant, keep one oxide only● Major simplification, reduce costs
17Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
DIOS simulated doping (part of ISE-TCAD)
● P+ shield implant: 800 keV (B), 51011 cm-2
● Buried channel: 200 keV (P), 41011 cm-2 and 40 keV (P), 31011 cm-2
● Annealed at 1050 C for 40 min
Analytical and simulated doping profiles
Analytical profiles:
Gaussians
Alternative ISIS structure Proposed super-pixel
20 µm
20 µm
4µm, 4Ø line
Apertures in p-well
Charge can be collected when a high phase is over a p-well aperture
Commercial in confidence
•Pure CCD process, simpler than the ISIS
but
•Too many transfers?
•Radiation damage concerns
•Complicated output structure
19Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
CPR2 designed for CPC2
Results from CPR1 taken into account
Designed by the Microelectronics Group at RAL
Size : 6 mm 9.5 mm
0.25 μm CMOS process (IBM)
Manufactured and delivered February 2005
Bump bond pads
Wire/Bump bond pads
CPR1
CPR2
Voltage and charge amplifiers 125 channels each
Analogue test I/O
Digital test I/O
5-bit flash ADCs on 20 μm pitch
Cluster finding logic (22 kernel)
Sparse readout circuitry
FIFO
WP3 : CPCCD Readout Chip CPR2
20Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
WP3 : CPR2
● Improved clock distribution, should improve ADC performance
● Sparse readout circuitry with position and timestamp, outputs 49 pixels/cluster
● Charge amplifiers:
Half with 3 fF feedback capacitor (as in CPR1)
Half with 2 fF capacitor for increased gain
● Voltage amplifiers:
Selectable 10 ns low-pass filter (was 5 ns in CPR1)
● Direct analogue outputs from one voltage and charge amplifier
● Three analogue inputs to one voltage channel triplet
● Test register with 3 functions:
Input to sparsifying logic
ADC data capture
Selection of an ADC channel for direct output
21Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
WP3 : Testing CPR2
● Test board made at Oxford U
● Work in the CCD lab has begun
● First results indicate the chip is operational
● Testing at RAL/ID imminent
● 2 wafers for bump-bonding available
22Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
WP4 : Transformer drive for CPC2
Tests of planar transformers with dummy capacitive load
Requirements: 2 Vpp at 50 MHz over 40 nF (half CPC2-40)
Frequency scan with network analyser, performance promising
Parasitic inductance of bond wires is a major effect – fully simulated
Different planar transformers on 10-layer PCB
Size : 1 cm
Air core operation from 1 MHz to > 70 MHz unloaded
Prototypes ready to be incorporated into the CPC2 test board (under design now at Oxford U)
IC driver could be a better solutionDesign of CPCCD driver chip - CPD1 in WP3
23Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
WP4 : External electronics
Base VME module (BVM2):
● Large FPGA on-board
● 32 TTL I/O
● 32 LVDS I/O
● Two 1M16-bit SRAM
● Two external clocks
● Daughterboard for extensions: delay lines, clock management, etc.
● Workhorse for the next 3 years
● Two modules manufactured (ver. 1)
● Second version being designed
24Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Immediate Plans
WP2:
● Get CPC2 and ISIS1
● Continue ISIS simulations,
WP3:
● Provide support for CPR2 tests
● Start the design of CPD1
WP4:
● Design motherboards for CPC2+CPR2 (bump-bonded and stand-alone)
● Transformer drive, work on the driver chip
WP5:
● Test CPR2, CPC2, ISIS1
● Bump-bond CPC2 to CPR2 and test
25Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Readout Chip Dicing – Upper Left Corner
IBM dicing
VTT batch 1
VTT batch 2
CPCCD Work – Hybrid Assembly Testing (WP5)
26Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
How CPC1+CPR1 work
ADCBLR +
ADC_
OG RG RD OD
+12.7 V
+18.0 V
OG RD
+17.0 V
2.5 V
CPR-1CPC-1
110 µA
BC
SC
BC
Gain ≈ 40
≈ +14.0 V
≈ +14.0 V
+15.2 V
+2.0 V
FB_V
FB_Q
VDC
Floating CPR-1 ground
LPF
3 fF
X-ray signal ≈ 200 mV
X-ray signal ≈ 90 mV
Correlated Double Sampling
27Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
p+ shielding implant
n+
buried channel (n)
substrate (p+)
storage
pixel #1
storage
pixel #20 sense node (n+)
Charge collection
row select
reset gate
Source follower
VDD
p+ well
reflected charge
reflected charge
photogate
transfer
gate
Reset transistor Row select transistor
output
gate
High resistivity epitaxial layer (p)
To column load
n+
buried channel (n)
substrate (p+)
storage
pixel #1
storage
pixel #20 sense node (n+)
Charge collection
row select
reset gate
VDD
p+ well
reflected charge
reflected charge
photogate
transfer
gate
output
gate
High resistivity epitaxial layer (p)
Design A
Design B
28Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
1
Storage gate 2
45
6
20
19
1817
7
8
RSEL OD RD RG
OSto column load
Storage gate 3
Transfer gate 8Output gate
Output node
Photogate
Charge generationTransfer Storage
Readback from gate 6Idea by D. Burt and R. Bell (e2V)
29Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
0 5
0 5
0000
0000
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 5 5 0
0 0 0 0
0 0 0 0 0 00
0 0 0 0 0 00
0 0 0 0 0 00
0 0 0 0 0 00
0 0 0 0 0 00
0 0 0 00
0 0 0 00
Cluster found
Expanded cluster to be read out
0 0 0 0 0 00
0 0 0 0 0 00
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
Cluster Finding in CPR2
30Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Yield summary from batch 1
Assembly Left hand side chip Right hand side chip CCD
1 OK OK OK
2 OK OK Problem
3 OK OK Problem
4 OK Low resistance CGND-VDD Problem
5 OK OK OK
6 OK Short CGND-VDD OK
7 Subtle defect (VPRE-VDC) Short CGND-VDD OK
Problem description:● Parasitic ohmic connection between right hand side chip substrate (CGND) and CCD substrate (SS)● Should see reverse-biased diode between CGND and SS ● The problem disappears when right hand side chip is removed● Not caused by contamination, resistance too small (e.g. 360 Ω)
CPCCD Work – Hybrid Assembly Testing (WP5)