1 fdl 2009 forum on specification and design languages automatic transformation of rtl models from...

1FDL 2009Forum on Specification and Design Languages

Automatic Transformation of RTL Modelsfrom VHDL to SystemC

Ralph Görgen – OFFISPhilipp A. Hartmann – OFFISFrank Oppenheimer – OFFISJan-Hendrik Oetjens – Robert Bosch GmbHJoachim Gerlach – Robert Bosch GmbH

Introduction

Development processes are not only top-down … Validation Integration of IP

… and they are not seamless Co-operation of companies or company divisions

Goal: Seamless integration of RTL components into system level simulation for the safety-critical automotive domain

FDL 2009, Sophia-Antipolis2

Common strategies

Co-simulation Requires …

… expertise in simulation hardware

… simulation environment

… source code

Manually implemented system models Time-consuming Error-prone Must be kept consistent

Automatic generation of system models


SC_MODULE ( arbiter ) { vh_in < sc_logic > clk; vh_in < sc_logic > m1_req; vh_out < int > s1_data; … SC_CTOR ( arbiter ) { SC_METHOD ( arbiter_process ) sensitive << clk;};

Matlab/Simulink A tool for …

…modeling

…simulating

…and analyzing For multi domain systems Is widely spread in the automotive domain

SystemC A set of …

…library routines

…and Macros Implemented in C++

VHDL Synthesizable Low level optimizations

SFunc-Wrapper

Modeling Environments


SC_MODULE ( arbiter ) { vh_in < sc_logic > clk; vh_in < sc_logic > m1_req; vh_out < int > s1_data; … SC_CTOR ( arbiter ) { SC_METHOD ( arbiter_process ) sensitive << clk;};

ENTITY mux is port ( d1, d2, sel : in std_logic; q1 : out std_logic );END ENTITY;ARCHITECTURE struct OF mux ISBEGIN q1 <= d1 when sel = `0` else d2;END ARCHITECTURE;

BoschFDL 08

?

Outline

Introduction

Transformation Framework

VHDL vs. SystemC

C++-Library for VHDL-Support

Resolution of Overloaded Function Calls

Evaluation of Simulation Performance

Conclusion


XML-based Transformation Framework

Allows automation of individual design steps

Definition of transformation rules Translation of transformation rules

to XSLT Automated application to design

descriptions

Supported HDLs VHDL SystemC

Transformation result is Human readable Recognizable


Designflow Transformation

HDLdescription

XMLdata structure

(AST)

TransformedHDL

description

VHDL-to-SystemC Transformation

Goal: A transformation rule that … … reads a synthesizable VHDL model and … generates an equivalent SystemC model. Transformation output should look like input.


BusµP/µC

RAM

BusIF

BusIF

BusArbiter

MemoryController

BusIF

BusµP/µC

RAM

BusIF

BusIF

BusArbiter

MemoryController

BusIF

VHDL vs. SystemC

Very similar at first sight (at RT level) Both languages offer …

… discrete event simulation

… hierarchical design (modules)

… concurrent design (processes)

… ports and signals for inter process communication

… RT level types (arbitrary integer, logic vector)


VHDL vs. SystemC: Basic Mapping

Design units Package declaration namespace Entity declaration SC_MODULE Architecture SC_MODULE derived from entity module

Object declarations Generics template parameter Ports sc_port Signals sc_signal

Statements Process statement SC_METHOD/SC_THREAD Concurrent statement equivalent process statement


VHDL vs. SystemC: Syntactical Differences

Syntactical differences i.e. …

… function declaration in another function

… array type expression in case statement

… operator precedence (unary +/- and multiply)

… non-recursive use vs. recursive using

Caused by formal C++ syntax

Solution: workaround …

… function declaration in particular namespace

… if-elsif-statement instead of case statement

… explicit order with brackets

… encapsulated namespace to hide recursive using


case reg is when “001” =>

v := s1; when “011” => v := s2; …

if ( reg == “001” ) v = s1;else if ( reg == “011” ) v := s2;…

use work.p2.all;package p1 is...

use work.p1.all;entity e is... --p2 not visible

namespace p1 { namespace inner { using namespace p2; void foo(); } using inner::foo;}

VHDL vs. SystemC: Type System

Differences arising from VHDL type system ...

… boundary checks on variable assignment

… attributes of objects and types

… constrained and unconstrained subtypes

… ascending and descending ranges that do not start with 0

… character literals as enumeration literal

… bit string literals as array objects

… aggregates

Solution: Library containing C++ templates for ... types signals and ports

… that behave and look like VHDL


Constrained integer types and subtypes

VH_INT( integer, -255, 255 );

VH_INT_SUBTYPE( natural, integer, 0, integer::high_ );

Boundary checks Operators as in VHDL

base_type_A + sub_type_A1: Correct sub_type_A1 + sub_type_A2: Correct base_type_A + base_type_B: Error

Implicit conversion of literals Attributes: high, low, left, right, next, …

struct A_desc : public int_type_desc<-255,255>{};typedef int_type<A_desc> A;

struct B_desc : public int_type_desc<-255,255>{};typedef int_type<B_desc> B;

var_A + var_B : Error

typedef int_type<-255,255> A;

typedef int_type<-255,255> B;

var_A + var_B : Correct

Integer Types


Enumeration types and subtypes

VH_ENUM( boolean ){ IDLE, RUNNING, BLOCKED };

VH_CHAR_ENUM( std_ulogic ){‘U’,‘X’,‘0’,‘1’,‘Z’,‘W’,‘L’,‘H’,‘-’};

VH_CHAR_ENUM_SUBTYPE_CONSTRAINED( x01, std_ulogic, ‘X’, ‘1’ );

Boundary checks for constrained subtypes Operators as in VHDL Implicit conversion of literals Attributes: pos, val, high, low, left, right, …

struct std_ulogic_tag { static const char[] values; };

typedef char_enum_type< std_ulogic_tag > std_ulogic;

const char std_ulogic_tag::values[] =

Enumeration Types


{‘U’,‘X’,‘0’,‘1’,‘Z’,‘W’,‘L’,‘H’,‘-’};

Array Types

Constrained and unconstrained array types

VH_UNCONSTRAINED_ARRAY( std_logic_vector, std_logic, natural );

VH_CONSTRAINED_ARRAY( x01_table, x01, range<‘U’,’-’,std_logic> );

VH_CONSTRAINED_ARRAY( std_logic_1d, std_logic, std_logic );

VH_CONSTRAINED_ARRAY_SUBTYPE( rtype, std_logic_vector, 15, 7 );

Index range checks Operators as in VHDL (incl. shift and concat) Attributes: left, right, low, high, … Implicit conversion of string literals Explicit conversion between closely related types (std_logic_vector, unsigned, …) Aggregates

std_logic_vector v ( 15, 7, vh_others() >> ‘0’ );

v = ( vh_at(13) >> ‘1’, vh_at(9) >> ‘X’, vh_others() >> ‘0’ );


Signals, Ports, and Parameters

Customized implementations of SystemC templates vh_signal< T > vh_in< T > vh_out< T > vh_inout< T >

Supporting VHDL attributes event, last_value Resolved signals of arbitrary type

Wrapper classes to support in, out, and inout parameters in functions vh_in_param< T > vh_out_param< T > vh_inout_param< T >

Control of read and write operations Conversion functions for out and inout parameters


Return type is part of signature in VHDL Solution: add return type to name

function foo( p : integer ) returns integer;

integer foo_ret_integer( p: integer );

function foo( p : integer ) returns std_logic_vector;

std_logic_vector foo_ret_std_logic_vector( p: integer );

Resolution of Overloaded Function Call


Ambiguous parameter types in C++

A: function conv_integer( p : integer ) returns integer;

B: function conv_integer( p : std_logic_vector ) returns integer;

conv_integer( integer_variable ) A

conv_integer( std_logic_vector_variable ) B



conv_integer( 20 ) ?

ambiguous: ‘const int’ and ‘const char*‘

conv_integer( “110011” ) ?


Ambiguity between ‘const int’ and ‘const char*’ Compiler knows about difference but standard defines equality

Solution: Eliminate undesired candidate Suppress template constructor instantiation with ‘enable_if’-template SFINAE: substitution failure is not an error

template < typename U >

in_param ( U const & val,

typename enable_if <

is_basically_same <

U, param_type::basic_c_type

>::value

>::type * = 0 )

{ … }


Bus-arbiter model

Configurable IP block implemented in synthesizable VHDL n master ports m slave ports

Testbench in Simulink

Experiments


Results: Automatic Generated Simulink Module

Manual conversion The designer has to …

… understand the design

… have C know-how

… guarantee equivalent behavior Takes several days

Automatic generation Takes a few minutes

Performance 31% overhead for actual component 2% overhead for entire simulation


Actual Component

Entire Simulation

Conclusion and Outlook

Presented solution allows …

… automatic integration of VHDL designs into Matlab/Simulink

… distribution of precompiled designs

Transformation of VHDL designs to SystemC Library to instantiate VHDL-like types and objects in SystemC

Allows straight-forward VHDL-to-SystemC transformation Wrapper to convert types to standard SystemC types Acceptable loss of performance

Future work Support for additional VHDL features Specialized implementation of often used VHDL types to improve performance



Thank you for your attention.

Questions?

For-Loop with Range


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