1

Demonstrations of Evolvable Systems

• Evolution on JPL EHW Testbed

• Details of EHW Pack (SW tools)

• platform for mixtrinsic evolution

• Evolution on JPL SABLES (Stand-Alone Board-Level Evolvable System)

• Half-Wave rectifier

• Adaptive Filters,

• Digital circuits

2

Block diagram of an EHW System

Reconfiguration Mechanism: Evolutionary Processor - Supercomputer, PC/CPU -DSP, FPGA, ASIC

Reconfigurable Hardware - Unconstrained (model in SPICE) - FPGA (Xilinx chips) - FPAA (model, Lattice) - FPTA (model, chips)

3

JPL EHW Testbed

Link to Software Evaluation

D/A

Digital I/O

A/D

Reconfigurable hardwareChips under test

LabView

256-processor machinerunning SPICE

GUI

Link to Hardware Evaluation

SW model of the HW

DBEvolutionary ReconfigurationMechanism (PGAPack)

SW Tool: EHWPackHW resources: PC + NI HW/SW,

Supercomputer

User can draw a function using the graphical tablet

A few minutes later the hardware has evolved(synthesized) a circuit providing the function

4

National Instruments Boards

• PCI-DIO: digital inputs and outputs;• AT-MIO-64E board is the multipurpose board which can

be used for both analog and digital inputs and outputs.• The FFT signal analyzer board is used to speed up the

computation for the FFT of a desired signal.• The Image board is used to capture pictures for robot

training.• The AT-AO/10 board can generate up to 10 different

analog signals at the same time, which helps to reduce number of signal generators.

5

EHW Testbed details

• HP Exemplar shared-memory supercomputer;

• 256 CPUs and 64 GB of memory; • 16 nodes, with each node having 16 processors;

• Different queues for jobs requiring different numbers of processors: 8, 16, 32 and 128;

• One node dedicated to the users login session and compilation of jobs;

• All the other nodes are reserved for batch jobs or interactive job requiring input-output interface with the user during execution;

• The EHWPack parallel implementation uses a master/slave algorithm, in which one process, the master, executes all steps of the genetic algorithm except the function evaluations (SPICE simulation or evolvable hardware evaluation);

• The function evaluations are executed by slave processors;

• The master is running on one processor of the HP exemplar and the slaves are running on the other processors allocated for the job or on the FPTA hardware through an internet communication.

6

EHW Pack

• Based on PGAPack

• GUI

• Can run Extrinsic Intrinsic & Mixtrinsic evolution

• Access over Internet (e.g.by NASA Ames & NSI)

• Built for easy add-on simulators/evaluators currently supports SPICE, NEMO, Diehard

• New search/optimization algorithms

7

PGAPack and SW evaluation

GraphicalUser Interface

PGAPACKParallel

Genetic Algorithm Genes

Fitness of individual device/circuit

DesiredData

Data from simulation

Simulator SPICEParametric model

1 of 256 processorsCaltech supercomputer (HP Exemplar)

NEMO

Diehard

8

Main Window: PGA spice.pga

Parameter to Gene Mapping General Optimizer Input Parameters

GA Standard Parameters

GA Output/input Options

TOOL SPICE3F5

Fitness Function Parameters

Submit to Queue

View Complete Queue

EHW Pack GUI

9

GUI Detail

10

Differences between HW and SW evaluation

Differences between model and real HW: • Simplified models (e.g. to gain speed in SPICE runs),• Incomplete models because of lack of information about fabrication,• HW can change from the moment was modeled/identified (temperature, radiation, operating conditions), •HW can change in time after evaluation (e.g. slow discharge)

Simulator limitations (SW evaluation): •Convergence conditions, which humans may be able to help by setting/adjusting values, •Conditions unknown a-priori (e.g. charges, initial conditions), in which case the system of differential equations can not be solved

HW testing limitations: a) Transients, b) Charge, e.g. remaining from a previously evaluated individual, c) Impedance loading of measured circuit, d) Time delays between physical signals (e.g. excitatory) and outputs, e) Artifacts originating in signal generators, data acquisition paths, sampling, A/D, etc

11

Extrinsic, Intrinsic and Mixtrinsic

Population of Software models

Parallel SearchAlgorithm SW1 SW2 SWn

Population of candidate solutions

...

Extrinsic EHW: evaluations of software solutions

Mixed Population of Software and Hardware

Parallel SearchAlgorithm SW1 HW2 SWn

Population of candidate solutions

...

Mixtrinsic EHW: evaluations of mixed populations comprised of both hardware and software solutions

Parallel SearchAlgorithm HW1 HW2 HWn

Population of candidate solutions

... Population of Hardware solutions

Intrinsic EHW: evaluations of hardware solutions

Simulator

ModelReconfigurable

HW

StimulusData file

Path from chromosome to behavior data file a)extrinsic and b)intrinsic

HW evaluatortesting equipment

Configuration Parameters

Data file

b)a)

Portability problem...

12

The FPTA enables rapid evolution (seconds), orders of magnitude faster than in simulations. Simulations scale poorly, while HW evaluation is size independent.

10,000 times faster evolution for for circuits with ~200 transistors compared to SPICE simulations on Sun Ultra 80).

HW is needed for complex circuits

13

EHW Experiments

Evolutionary circuit synthesis and repair

• Synthesis

• Analog computational circuits (fuzzy neuron, multipliers)

• Logic Circuits (XNOR, AND gates)

• Filters (band-pass)

• Repair: From faults and degradation with temperature

GenerationsF

itn

ess

0 15 30 45 60 75 90 105 1200

0.15

0.3

0.45

0.6

0.75

0.9

1.05

1.2

No Fault

1 Fault is Injected

Free Des ign FitnessFault Tolerant Fitness

Frequency(Hz)

Gai

n(dB

)

10 100 1,000 10,000 100,000 1,000,000-60

-50

-40

-30

-20

-10

0

10

14

Programmable Transistor Array Cell

Binary chromosomes used in GAs are a straightforward mapping for downloading circuits onto reconfigurable chips.

100011….1111

S7P1

S4

S1

P2

V+

S12

S5

P4

S14

S15

S22

N6

N8S24

S23N7

S20

N5S11

S18

S17

S6S9

S8

S2

S3P3

S13

S10

S16

S19S21

V-

Each bit of the chromosome determines the state of a switch in the reconfigurable device.

Simplified Cell in Field Programmable Transistor Array

Step-by-step evolution example

Evolve a computational circuit which responds with a Gaussian current output when the input is ramped between Gnd to Vdd.

Sample

Ou

tpu

t (V

olts

)

0 1.5 3 4.5 6 7.5 9 10.5 120

0.5

1

1.5

2

2.5

3

16

Mapping classical circuits on FPTA

(B)

Input (V)Ou

tput

(V)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50.8

1.2

1.6

2

2.4

2.8

3.2

3.6

4S7

P1

S4

S1

P2

V+

S12

S5

P4

S14

S15

S22

N6

N8S24

S23

N7S20

N5S11

S18

S17

S6S9

S8

S2

S3P3

S13

S10

S16

S19

S21

(A)

In+ In-

Out

Transconductance Amplifier mapped into FPTA

17

Genes and their mapping to hardware

What is needed first: the “genes” representation for the system to be evolved (STBE), and the mapping/transformation from genes to an “embodiment” of the

STBE. Gene representation: could be a binary word “10101100” , each bit defines the value of a 2-

state device. Mapping/transformation from genes to an “embodiment” In extrinsic Evolvable Hardware the “embodiment” is a description of a

model of the STBE submitted to a simulator that evaluates the model and generates a behavioral response.

1 R = 10 Turn Switch ON0 R=10M Turn Switch OFF

In intrinsic Evolvable Hardware the “embodiment” is the programmable circuit itself.

18

TemplateFPTA SPICE Netlist

.MODEL NMOS NMOS LEVEL=8 TOX=7.6000E-09 XJ=0.100000U + VTO=0.4777253 DELTA=1.00E-02 ….MODEL PMOS PMOS LEVEL=8 TOX=7.6000E-09 XJ=0.100000U + VTO=-0.7111998 DELTA=1.00E-02 …* Basic Circuit Configuration for evolvable hardware m1 n1d n1g 1 1 PMOS l=1.2u w=1.2u m2 n2d n2g 1 1 PMOS l=1.2u w=1.2u … m7 n7d n7g 0 0 NMOS l=1.2u w=1.2u m8 n8d n8g 0 0 NMOS l=1.2u w=1.2u

* the tgate-based switches m9 n1g S1 n2g 0 NMOS w=1.2u l=.6u m10 n2g _S1 n1g 1 PMOS w=3.6u l=.6u m11 n1d S2 n3s 0 NMOS w=1.2u l=.6u m12 n3s _S2 n1d 1 PMOS w=3.6u l=.6u …m55 n7g S24 n8g 0 NMOS w=1.2u l=.6u m56 n8g _S24 n7g 1 PMOS w=3.6u l=.6u

vdd 1 0 DC 3.3v vin+ n5g 0 DC 1.5vin- n6g 0 DC 1.5.DC vin+ 0.0v 3.3v 0.15v.Print DC v(n4d).END

*Resistance Based switchesR1g2g 1g 2g R1_R1d3s 1d 3s R2_…R7g8g 7g 8g R24_

S7P1

S4

S1

P2

V+

S12

S5

P4

S14

S15

S22

N6

N8S24

S23N7

S20

N5S11

S18

S17

S6S9

S8

S2

S3P3

S13

S10

S16

S19S21

V-

10000….0001

1 means closed switch0 means open switch

Field Programmable Transistor Array

Each bit of the chromosome determines the state of a switch in he reconfigurable device.

19

From chromosome to voltages (or resistances)

Biti = 1

3.3V

0V

Switchi

Biti = 0

0V

3.3V

Switchi

Ri = 50

Ri=1010

OR

OR

20

Output netlist with resistances

R1g2g 1g 2g 50 R1d3s 1d 3s 1e+10 R1d5d 1d 5d 1e+10 R1g1d 1g 1d 50R2d4s 2d 4s 50R1d6d 1d 6d 50R3sdd 3s 1 1e+10R3s4s 3s 4s 1e+10R3g4g 3g 4g 50R3d5d 3d 5d 1e+10…R7d7g 7d 7g 1e+10R7g8g 7g 8g 50

01100??

21

Output netlist with transistors

vs1 S1 0 0.000000v_s1 _S1 0 3.300000vs2 S2 0 3.300000v_s2 _S2 0 0.000000…vs24 S24 0 3.300000v_s24 _S24 0 0.000000

Voltages Switches

m9 n1g S1 n2g 0 NMOS w=1.2u l=.6u m10 n2g _S1 n1g 1 PMOS w=3.6u l=.6u m11 n1d S2 n3s 0 NMOS w=1.2u l=.6u m12 n3s _S2 n1d 1 PMOS w=3.6u l=.6u …m55 n7g S24 n8g 0 NMOS w=1.2u l=.6u m56 n8g _S24 n7g 1 PMOS w=3.6u l=.6u

22

Circuit Output

vin+ V(n4d) 0.000E+00 1.828E-04 1.500E-01 1.800E-04 3.000E-01 1.773E-04 4.500E-01 1.744E-04 6.000E-01 1.708E-04 7.500E-01 1.670E-04 9.000E-01 1.630E-04 1.050E+00 1.591E-04 1.200E+00 1.552E-04 1.350E+00 1.513E-04

Output File 0.0819710.2462550.6056901.2197092.0109602.7145123.0000002.7145122.0109601.2197090.6056900.2462550.081971

2.005E-047.598E-026.637E-011.556E+002.299E+002.482E+002.428E+002.252E+002.006E+001.717E+001.406E+001.102E+008.186E-01

Target Actual Data

Sample

Out

put (

Volts

)

0 1.5 3 4.5 6 7.5 9 10.5 120

0.5

1

1.5

2

2.5

3

Target (T)

Actual Data (Y)

Fitness = (Yi – Ti)2

i

23

Selection: Ranking

Rank individuals according to the quality of their response

24

PopulationInitialization(Randomly)

Evaluation• Simulators (SPICE)• Hardware (PTAs)

New Population(Pop. Size 512,

24 bits)

Evaluations(30 samples)

Fitness(MSE)

0.11

Population

01001110111001

0

0,5

1

1,5

2

2,5

3

3,5

0,2

2

0,3

6

0,5

1

0,6

6

0,8

2

0,9

7

1,1

2

1,2

7

1,4

3

1,5

8

1,7

3

1,8

9

2,0

4

2,1

9

2,3

4

2,5

2,6

5

2,8

2,9

5

3,1

1

3,2

6

3,4

1

3,5

7

3,7

2

3,8

7

4,0

3

4,1

8

4,3

5

4,5

4,4

6

Vin(V)

Vo

ut(

V)

0

0,5

1

1,5

2

2,5

3

3,5

0,22 0,51 0,82 1,12 1,43 1,73 2,04 2,34 2,65 2,95 3,26 3,57 3,87 4,18 4,5

Vin(V)

Vo

ut(

V)

0

0,5

1

1,5

2

2,5

3

3,5

4

0,22 0,51 0,82 1,12 1,43 1,73 2,04 2,34 2,65 2,95 3,26 3,57 3,87 4,18 4,5

Vin(V)

Vo

ut(

V)

0

0,5

1

1,5

2

2,5

3

3,5

4

4,5

5

0,2

2

0,3

6

0,5

1

0,6

6

0,8

2

0,9

7

1,1

2

1,2

7

1,4

3

1,5

8

1,7

3

1,8

9

2,0

4

2,1

9

2,3

4

2,5

2,6

5

2,8

2,9

5

3,1

1

3,2

6

3,4

1

3,5

7

3,7

2

3,8

7

4,0

3

4,1

8

4,3

5

4,5

4,4

6

Vin(V)

Vin

(V)

0.34

0.10

0.53

0.10

01001010110000

10110111110110

01011110111001

0.15

0.29

01001110110000

11001110111001

01100010100001

01000111101000

0.11

0.27

0.34

0.53

0.39

Sort

01001010110000

01000111101000 01001010110000

Two Points Crossover(Prob. 70%)

Elite(10%)

Uniform Mutation(Prob. 4%)

Elite(10%)

Binary Tournament Selection (size 2)

Elite(10 %)

0.39

0.15

01011110111001

10110111110110 0.53

0.29 01011110111001

01001110110000

01011010111001

Best

01101111110000

11011010011011

RecombinedIndividuals

RecombinedIndividuals

0

0.5

1

1.5

2

2.5

3

3.5

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vin(V)

Vo

ut(

V)

0

0.5

1

1.5

2

2.5

3

3.5

4

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vin(V)

Vo

ut(

V)

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vin(V)

Vo

ut(

V)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vin(V)

Vo

ut(

V)

0

0,5

1

1,5

2

2,5

3

3,5

0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5

Vin(V)

Vo

ut(

V)

Vout

Vin

Vout

Vin

Vout

Vin

Vout

Vin

Compare to

Target

2*2 rand

Evolutionary algorithms visualized

25

Results of on-chip evolutionary synthesis

Board with 4 PTA chips

LabView captured output of 4 circuit solutionsD/A

Digital I/O

A/D

Evolvable hardwarechips under test