1. current and voltage referencesbel.utcluj.ro/ci/eng/aic/documents/references.pdf · 2018. 10....

Analog Integrated Circuits – Fundamental Building Blocks Current and Voltage References

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1. Current and voltage references

Current and voltage references are the electronic implementations of independent, ideal sources. They provide currents or voltages that are independent on load impedance, temperature variations and supply vol-tage. In real implementations the term reference is used to designate a special category of circuits that feature better precision, lower sensitivity and lower temperature coefficient than average electronics.

The performance indicators of an electronic reference are quantitatively described by calculating the effects of different circuit parameters and temperature variations on the generated current or voltage. Apart of the supply current or voltage values, references are often characterized by two parameters: sensitivity and temperature coefficient.

The sensitivity is defined as the relative variation of the reference current or voltage Xref with any cir-cuit parameter y. Typical quantities influencing Xref are for example resistances, transistor parameters and the supply voltage.

refyXref

ref

X ySy X

(1)

The temperature coefficient is defined as the sensitivity of Xref to temperature variations, normalized to one degree. The temperature coefficient can be specified in V(A)/°C or ppm/°C (ppm=parts per million). More often than not, all components in the reference circuitry are temperature dependent. Therefore, the ri-gorous derivation of the TC may prove to be an extremely labor intensive task.

1ref

ref

XTC

T X

(2)

1.1. Supply dependent voltage and current references

1.1.1. The voltage divider reference

The most simple form of a voltage reference can be implemented by using a voltage divider that pro-vides a fraction of the supply voltage as reference. The passive resistor and the MOS diode implementations are illustrated in Figure 1.

Figure 1. A resistive and a MOS divider as voltage references

The reference voltage of the resistive divider can be easily found as

2

1 2ref DD

RV VR R

(3)

The sensitivity of the reference voltage to the variations of the supply voltage is found by evaluating the derivatives from the definition (1) of the sensitivity.


2

2 1 2

1 2 2

1DD

ref

refV DD DDV

DD ref DD

V V R V R RSV V R R R V

(4)

The sensitivity equal to unity means that a 1% variation of the supply voltage will produce a 1% varia-tion of the reference voltage. This fact is obvious due to the linear dependence of Vref on VDD.

The temperature coefficient of the resistive divider depends on the variation of the resistor ratio and of the supply voltage with temperature. Typically, if the resistor are of the same type and matched, their ratio is insensitive to temperature variations and the main influencing factor will be the supply voltage.

The reference voltage generated by the MOS diode divider is found by matching the operating points of the two transistors. The drain currents are by definition

21 1

2

2 2

21

1 2

| |

;2 2

D n GS Thn

D p SG Thp

pnn p

I V V

I V V

k Wk WL L

(5)

The voltages in the circuit are related to each other according to

2

1

DD SG ref

GS ref

V V VV V

(6)

The gate-source voltages of M1 and M2 result from (5):

11

22 | |

DGS Thn

n

DSG Thp

p

IV V

IV V

(7)

The matched operating points assume the drain currents to be equal, ID1=ID2=I. In this case the combi-nation of (6) and (7) leads to

| |

1 1DD Thp Thn

n p

V V VI

(8)

Replacing I in the expression of VGS1 yields the reference voltage

| |

1

DD Thn Thpref Thn

n

p

V V VV V

(9)

The corresponding sensitivity to the supply voltage variations is found to be

1| |

DD

ref

refV DD DDV

DD ref nDD Thn Thp

p

V V VSV V

V V V

(10)


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In the particular case when βn=βp and VThn=|VThp|, the sensitivity approaches unity. The temperature coefficient of the reference voltage can be determined by calculating the partial deri-

vatives of all temperature dependent parameters. The rigorous calculation is difficult, but the result will be a function

1 , , , ,DD n p Thn Thp

refV V V

ref

VTC f TC TC TC TC TC

T V

(11)

The equations (3) and (9) show that for both dividers the reference voltage is a linear function of VDD. Consequently, the sensitivities will approach unity. Intuitively, the sensitivities could be reduced by creating a non-linear dependence of Vref on VDD.

1.1.2. A voltage reference using MOS and bipolar diodes

The voltage reference built around a MOS or bipolar diode aims the successive linear conversion of the supply voltage into a constant current and the non-linear reconversion into the reference voltage. The cir-cuit works as a hybrid passive-active voltage divider. The schematic is illustrated in Figure 2.

Figure 2. Transistors in diode connection as voltage references

The reference voltage and its sensitivity to supply variations can be derived by matching the operating points of the resistors and of the transistors.

the MOS implementation

The reference voltage is found by writing the following set of equations:

DD ref

ref GS Th

V VI

RIV V V

, (12)

where β is the intrinsic, geometry dependent current gain of the MOS transistor. By replacing the current into the second equation, the reference voltage results

DD refref Th

V VV V

R

(13)

This expression leads to a second order equations with two distinct solutions. However, the sensitivity can be determined without explicitly solving the equation for Vref, by simply differentiating both sides of (13). The calculations yield

2

DD

ref

refV DD DDV

DD ref ref DD ref

V V VSV V V R V V

, (14)


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which is lower than unity due to the compressive behavior of the square-root function. The temperature coef-ficient is again a complicated function of all the temperature dependent parameters (VDD, VTh, β, R) in the cir-cuit.

the bipolar implementation

The reference voltage of the bipolar implementation is found in a similar manner. The equations that describe the operating points of the resistor and of the diode are

ln

CC ref

ref BE TS

V VI

RIV V VI

(15)

The reference voltage is the solution of the transcendental equation

ln CC refref T

S

V VV V

RI

(16)

The sensitivity of Vref with the supply voltage results by differentiating both sides of (16) with respect to VDD.

DD

ref

refV CC TDDV

DD ref ref CC ref

V V VVSV V V V V

(17)

Apart from supply sensitivity, a drawback of the diode reference is the limited range of the output vol-tage. This problem can be alleviated by introducing an additional voltage divide between the reference out-put and the bases of the transistors as shown in Figure 3.

Figure 3. MOS and bipolar diode voltage references with extended output range

The range of the reference voltage is increased by the ratio of R1 and R2 according to

1

2

1

2

1

1 ln

DD refref MOS Th

CC refref BJT T

S

V VRV VR R

V VRV VR RI

(18)

Since the ratio R1/R2 is independent of the supply voltage and temperature, the sensitivities and tempe-rature coefficients will not be influenced.


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1.1.3. The Zener diode voltage reference

The source of large sensitivities in diode based references of the previous paragraph was the proportio-nality between Vref and VDD. If the voltage Vref was somehow made constant with the supply dependent bias current I, then the reference voltage would be independent on VDD. This leads to the idea of swapping the diodes in Figure 2 with a Zener diode as illustrated in Figure 4.

Figure 4. Zener diode voltage reference

The operation of the Zener diode is based on the breakdown of a pn junction under the influence of a strong enough reverse bias voltage. If the voltage is large, the depletion region around the junction boundary increases creating a strong electric field. This field can break the bonds of the electrons in the semiconductor crystal, creating an avalanche breakdown condition. The voltage drop VBV across the diode will be relatively well defined and independent on the break-down current IBV flowing through the junction.

The reference voltage is found at the intersection of the abrupt Zener diode characteristic with the load line specific to the resistor. The operating point must be located on the vertical, current independent section of the diode characteristic.

The main drawback of this reference is the incompatibility with modern CMOS technologies where supply voltages typically fall below 1.8-2V. As the breakdown effect only happens at large enough reverse bias, usually around 5V, the Zener diodes cannot be correctly biased at low supply voltages.

1.1.4. The self biased current mirror reference

The self biased current mirror reference is derived from the diode voltage reference in Figure 2 by re-converting the reference voltage into a current. The result is a current mirror, where the input, or reference current is determined by the intersecting characteristics of the diode and of the resistor. The input current is copied by the mirror and delivered to the output. The schematic of the circuit is given in Figure 5.

Figure 5. Self biased current mirror references

The output current is found by writing the dependence of ID and IC on the gate-source and base-emitter voltages of the transistors

2

2

2

ref

T

out MOS D ref Th

VV

out BJT C S

I I V V

I I I e

(19)

By replacing the expression of Vref from (13) and (16) it results that the output current is in both cases


6

/DD CC refout ref

V VI I

R

(20)

Consequently, the sensitivity of the output current to the variations of the supply voltage inherits its value from the sensitivity of Iref to VDD. This sensitivity is equal to unity as the reference current is a first or-der function of VDD.

DD DD

out ref

V VI IS S (21)

The sensitivity of the output current to the supply voltage cannot be eliminated as long as Iref is a func-tion of VDD, but may be reduced by scaling the sensitivity of Iref with a factor smaller than unity. This scaling is achieved by a linear or partially linear reconversion the reference voltage into the output current.

1.1.5. Widlar current mirrors

Widlar current mirrors resemble classical mirrors but the gate-source voltage of the input transistor in diode connection is distributed between the VGS of the output transistor and a series degeneration resistor. The schematic of the circuit is illustrated in Figure 6.

Figure 6. Schematic of the Widlar current mirror/reference

the MOS implementation

The operation of the circuit can be described by the following system of equations:

1 2 2

11

22

GS GS out

refGS Th

outGS Th

V V R I

IV V

IV V

(22)

Inserting the gate-source voltages into the first equation leads to

22 1

0refoutout

III R

(23)

This second order equation can be solved for Iout.

22 2 12

1 1 1 42

refout

II R

R

(24)


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Since the result is the square root of Iout, that must always be positive, only the positive solution in (24) is acceptable. The sensitivity of Iout to variations of the supply voltage is calculated by differentiating both sides of (24) with respect to VDD. The calculation yield

1 1

1 2

1 2

22

DD DD DD DD

out ref ref ref

ref

V V V VDSatI I I I

DSat DSatref out

IVS S S k S

V VI I

(25)

From the circuit topology it results that VGS1>VGS2 and implicitly VDSat1>VDSat2. Therefore, the scaling coefficient k is always smaller than unity and the sensitivity of Iout is lower than the sensitivity of Iref.

the bipolar implementation

The output current of the bipolar Widlar mirror can be found by writing a system of equations analo-gous to (22).

1 2 2

11

22

ln

ln

BE BE out

refBE T

S

outBE T

S

V V R II

V VI

IV VI

(26)

After replacing VBE1 and VBE2 into the first equation, the output current results

2

2 1

ln ref STout

out S

I IVIR I I

(27)

The sensitivity of Iout with the supply voltage is again calculated by simple differentiation

2

CC CC CC

out ref ref

V V VTI I I

T out

VS S k SV R I

(28)

The scaling coefficient is clearly less than unity and the sensitivity of Iout has been decreased compared to the sensitivity of Iref.

1.1.6. VTh and VBE current mirror references

In VTh and VBE mirrors the output current is obtained from the Vref voltage of Figure 2 by a linear con-version. The schematic of the circuit is given in Figure 7.

Figure 7. Schematic of the VTh-VBE current mirror/reference


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For both, the MOS and the bipolar implementations, the output current can be found by similar calcu-lations as for the Widlar current mirrors.

12

2 1

1

2 2 1

ln

refTh

GSout MOS

refBE Tout BJT

S

IV

VIR R

IV VIR R I

(29)

The corresponding sensitivities will be

1

1

1

2DD DD DD

out ref ref

CC CC CC

out ref ref

V V VDSatI I I

DSat Th

V V VTI I I

BE

VS S k SV V

VS S k SV

(30)

Since the voltage to current conversion is entirely linear, the scaling coefficient k takes the lowest pos-sible value among self biased references. The result is the lowest possible supply voltage sensitivity for this category of references.

1.2. Supply independent references

The sensitivity of the output current in Widlar, VTh and VBE references has been invariably connected to the supply voltage dependence of the biasing current in the input branch of the circuits. Even if scaled down, this sensitivity cannot be sufficiently decreased in order to insure the stability and accuracy required by some applications.

The solution to the above problem is provided by the idea to derive the biasing current from the output current, thereby simplifying the equations and eliminating the supply voltage altogether. The sensitivity will then only depend on the influence of VDD/VCC on the accuracy in copying Iout to Iref. As Iref determines Iout but also Iout determines Iref, it is clear that the resulting circuit would have a positive feedback loop causing each of the currents to be doubly determined. This kind of positive feedback, with the double definition of some parameters, is often called bootstrapping.

The easiest way of copying Iout to Iref is to use a current mirror on top of a Widlar, VTh or VBE reference. This principle is illustrated in Figure 8. The PMOS current mirror M3-M4 copies Iout to Iref, while the transis-tors M5-M6 act as current sources routing the output current for further usage.

Figure 8. Bootstrapped Widlar and VTh-VBE current references

An intuitive analysis of the bootstrapped current reference suggests that the positive feedback creates multiple stable operating points of the circuit. One operating point is in the origin, where Iref=Iout=0. The se-


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cond stable operating point is defined by the intersection of the Iref and Iout curves changing against the vol-tage drop across the resistor R. The variations of Iout and Iref at the circuit start-up are illustrated in Figure 9.

Figure 9. Stable operating points and evolution of the positive feedback loop

Obviously, the operating point located at the origin is not desired. In practical implementations a start-up circuit will move the currents away from the origin and will be deactivated as the circuit converges to the stable, desired operating point

The start-up circuit in Figure 8 is built around the self biased current mirror Rp-M7-M8 and it works de-pending on the instantaneous values of Iout and Iref.

if Iref=Iout=0 – the operating point of the reference is at the origin. Therefore, the gate-source voltage of M1, equal to VS7, is zero while the gate potential VG7 of M7 is set by Rp and M8. Then, the transistor M7 forces a current into M1 and the raising ID1 is copied to a rising ID2=Iout. The increasing Iout also causes Iref to grow and the circuit is moved away from the origin.

if Iref and Iout are further increased by the effect of the positive feedback loop, the VGS1 voltage also increases pushing up the source potential VS7 of M7. Since VG7 is held constant by M8, the VGS7 voltage will be decreased and the transistor M7 is progressively turned off. When the cir-cuit converges to the stable operating point where Iref=Iout, the start-up circuit is completely dis-connected from the reference and does not influence the operation.

The output current of the bootstrapped Widlar reference is found by replacing Iref with Iout in the equa-tion (24). The resulting expression does not contain VDD and the theoretical sensitivity of Iout on the supply voltage is equal to zero.

22 2 12

1 1 1 42

outout

II RR

(31)

In practical implementations the equality of Iref and Iout is influenced by the current gain errors of the mirror M3-M4. From the schematic in Figure 8 it can be seen that the source-drain voltages of M3 and M4 are not balanced. The voltage imbalance of the mirror is

3 4 1 4out in SD SD DD SG SGV V V V V V V V , (32)

which is clearly VDD dependent. This voltage imbalance causes a systematic current gain error that leads to a non-zero sensitivity of Iout to the supply voltage. The solution, that decreases the sensitivity of a bootstrapped reference, is to decrease the voltage imbalance, for example by using a cascode or balanced Wilson mirror.

1.3. Temperature compensated references

All the references discussed so far are influenced by temperature variations through the device and cir-cuit parameters. The outputs may have positive of negative temperature coefficients, depending on the domi-nant parameters and their temperature dependence. However, practical applications often require a voltage or current that is very stable with temperature.

The main idea for implementing temperature independent references is to add two currents or voltages with opposite temperature coefficients. If correctly weighted, these would compensate each other's tempera-


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ture dependence and would provide a stable reference current or voltage over a wide range of temperatures. The principle is illustrated in Figure 10.

Figure 10. Compensating temperature variations by summing two voltages with opposite TC

The two often used voltage types in temperature compensated references are the base-emitter voltage VBE of a bipolar transistor and the difference of base-emitter voltages ΔVBE.

the variation of VBE with temperature

Before defining the temperature coefficient of VBE, let us recall the saturation current IS of the bipolar transistor:

2

/ / 0 /

/

E n p p n E n p iS

B A D B

qA D n qA D nI

W N W , (33)

where q is the electronic charge, AE is the emitter area, Dn/p is the diffusion constant of electrons/holes, np/n0 is the minority carrier concentration passing the base-emitter junction boundary under the effect of VBE, WB is the base width, ni is the intrinsic carrier concentration in silicon and NA/D is the doping concentration of the emitter. The temperature dependent parameters Dn/p and ni can be written:

0

/ /

2 3G

an p n p

qVkT

i

kT kTD C Tq q

n DT e

(34)

In the above equations µn/p is the electron/hole mobility, C and D are constants depending on material and process parameters, but independent on temperature, VG0 is the silicon band gap extrapolated to 0K and a is a constant, equal to 2.4 for electrons and 2.2 for holes in Si. By replacing the diffusion coefficient and the intrinsic concentration into the expression (33) of IS it results that

0 0

1 3 4

/

G GqV qVa aE kT kT

SA D B

b

kA CDI T T e bT eN W

(35)

The base-emitter voltage is then

0

0

4 40

4

ln ln ln lnG

G

qVa aC C CkT

BE GqVa kT

I I IkT kT kTV T e V Tq q b q b

bT e

(36)

The temperature coefficient of VBE is determined by differentiating the equation (36) with respect to T.

4 5 0

4

4 4ln Ca aC BE GBE

aC

a I a kI V VV k kT bT TT q b q I T b T q

(37)


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For the typical values VBE=600mV, VG0=1.205V, T=300K and a=2.4 the temperature coefficient of VBE results to be approximately -2mV/°C. Therefore, VBE decreases with temperature and is often called comple-mentary with absolute temperature, or simply CTAT voltage

the variation of ΔVBE with temperature

The temperature dependence of ΔVBE is found by considering two transistors, for example Q1 and Q2, connected in a circuit topology where Kirchhoff's law written for a voltage loop leads to VBE1-VBE2. Each VBE can be expressed as a function of the thermal voltage, collector current and saturation current.

11

1

22

2

ln

ln

CBE T

S

CBE T

S

IV VI

IV VI

(38)

The ΔVBE voltage is then

1 2 1 21 2

1 2 2 1

ln ln lnC C C SBE BE BE T T T T

S S C S

I I I IV V V V V V VI I I I

(39)

The temperature dependence of both, the collector currents and the saturation currents, are canceled by the ratios. Consequently the weighting factor α is independent of temperature, while the slope of the function ΔVBE =f(T) is found by differentiation.

0.085mV /BE TV V kT k C

T T T q q

(40)

It can be easily seen that the base-emitter voltage linearly increases with temperature and is therefore often called to be a proportional to absolute temperature, or simply a PTAT voltage.

A temperature compensated reference is obtained by summing a base emitter voltage with a weighted PTAT voltage as illustrated in Figure 11. The PTAT voltage is always obtained with some form of a bipolar Widlar current mirror, in which a mechanism has been used to equal the reference and the output currents. If the resistor R is considered to be temperature independent for the moment, the output current will be a linear function of temperature through ΔVBE and the thermal voltage VT.

Figure 11. The band gap voltage reference – principles of operation

The output voltage of the circuit is of the form

out BE TV V V , (41)

where α is a temperature independent scaling factor. The temperature compensation is achieved by correctly choosing the weighting factor α of the thermal voltage and adjust the slopes of the two complementary tem-perature dependences. The temperature coefficient of Vout is calculated by differentiation.


12

out BE TV V VT T T

(42)

In order to completely cancel out the temperature dependence of Vout, its temperature coefficient must be equal to zero. The weighting coefficient α can be calculated by replacing the variations of VBE and VT with temperature

2mV/°C 23.530.085mV/°C

BE TV VT T

(43)

If VT is 26mV at the room temperature, then the temperature independent output voltage will have va-lues around 1.2V. This corresponds to the silicon band gap voltage and this type of temperature compensated references are generally called band gap references.

Theoretically, the correct choice of the weighting coefficient would lead to the perfect compensation of Vout with temperature as long as the variation of both voltages is linear with the temperature. However, the equation (37) shows that this is not true and the VBE(T) will exhibit a non-zero curvature. It results that the e-quation (43) can only be satisfied for a single temperature, typically chosen to be the nominal operating tem-perature of the circuit. The output voltage will then exhibit a weak temperature dependence and its overall TC will not be zero. This is illustrated in Figure 12.

Figure 12. The band gap output voltage curvature

1.4. Band gap references - examples

1.4.1. The Widlar band gap reference

The Widlar reference is one of the first band gap voltage references, built with bipolar transistors. Its output voltage takes the form in the equation (41). The schematic of the circuit is illustrated in Figure 13.

Figure 13. Schematic of the Widlar band gap voltage reference


13

For simplicity in calculations, the transistors are considered to be ideal, their current gain approaching infinity. The output voltage is then

1 1 1out BEV V I R (44)

If all the transistors are identical, then IS1=IS2=IS3 and VBE1 is approximately equal to VBE3. This leads to

1 1 1 3 2 2 1 1 2 2BE BEV I R V I R I R I R (45)

The output voltage becomes

1 2 2out BEV V I R (46)

Kirchhoff’s voltage law written for the bases of Q1 and Q2 yields

1 2 1 21 2 2 3 2

3 3 2 3 1

ln lnBE BE T TBE BE

V V V I V RV V I R IR R I R R

(47)

After replacing I2 into the equation (46), the output voltage results

2 21 1

3 1

( )

lnout BE T BE T

f T

R RV V V V VR R

(48)

This equation shows that the output voltage is compensated with temperature. Furthermore, since the ratio of the currents I1 and I2 only depends on the ratio of resistances R1 and R2, the output voltage is also in-sensitive to variations of the supply voltage.

1.4.2. The Song band gap reference

The Song band gap reference uses a bipolar Widlar current mirror to generate a PTAT current. Depen-ding on the available bipolar transistors, the Widlar mirror may be implemented with vertical NPN transis-tors (bipolar or BiCMOS technologies) or with lateral PNP transistors (pure CMOS technologies). The sche-matics of both implementations are given in Figure 14. In this implementation all current mirrors have been balanced by cascoding in order to also insure supply voltage independence.

Figure 14. Schematics of the Song band gap voltage reference – implementations with vertical NPN and lateral PNP transistors


14

The calculation of the output voltage starts with the fundamental Widlar mirror:

1 2 2 1BE BEV V I R (49)

The PTAT current is equal to I2 due to the PMOS current mirror.

21 2 12

1 1 2 1

ln SBE BE TPTAT

S

IV V V II IR R I I

(50)

The current I1 and I2 are equal due to the bootstrapped topology, while the ratio of the saturation cur-rents is defined by the ratio of emitter areas. If the transistor Q2 is N times larger than Q1, then IS2/IS1=N and the PTAT current becomes

1

lnTPTAT

VI NR

(51)

The output voltage is obtained by passing IPTAT through the resistor R2 and converting it into a PTAT voltage as required by the band gap operating principle. This voltage is then added to VBE3 and the final out-put voltage will be

23 3

1

( )

lnout BE T BE T

f T

RV V V N V VR

(52)

1.4.3. The Brokaw band gap reference

The structure of the Brokaw cell is similar to the Song band gap reference, but the Widlar mirror and the output branch are combined into a single circuit. The supply voltage independence is insured either by bootstrapping or by a high gain negative feedback loop. The two most often used implementations are given in Figure 15.

Figure 15. Schematics of the Brokaw band gap reference – implementations with bootstrapping and high gain negative feedback

The Widlar mirror in the bootstrapped implementation is built with the transistors Q1-Q2 and the resis-tor R1. Kirchhoff’s voltage law gives

1 2 2 2BE BEV V I R (53)


15

The currents I2 and I1 can be expressed as

21 2 12 1

2 2 2 1 2

ln lnSBE BE T T

S

IV V V I VI I NR R I I R

(54)

Then, the output voltage can be written as

11 1 1 2 1 1

2

( )

2 lnout BE BE T BE T

f T

RV V R I I V V N V VR

(55)

In the second schematic of Figure 15 the bootstrapping is replaced with a high gain negative feedback loop. If the gain of the operational amplifiers is sufficiently large then the positive and negative input volta-ges will be equal. Consequently, if R3=R4, then the equality of the currents I1 and I2 is also insured and the reference works according to the equation (55).

1.4.4. Example 4

Another band gap voltage reference is illustrated in Figure 16. This circuit is suitable for implementa-tion in BiCMOS technologies, where high quality vertical NPN transistors are available.

Figure 16. BiCMOS band gap reference example

Kirchhoff’s voltage law written at the Q1 transistor base leads to

1 2 3 1BE BEV V I R (56)

The current I3 may be expressed as

21 2 1 13

1 1 3 1 1 3

ln lnSBE BE T T

S

IV V V I V II NR R I I R I

(57)

The transistor pairs Q1-Q4, Q2-Q3 and M1-M2 form current mirrors with unity current gain. Therefore, it holds true that I1=I2=I3=I5. In this case, the output voltage results

24 2 3 5 4 4

1

( )

2 lnout BE BE T BE T

f T

RV V R I I V V N V VR

(58)


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1.4.5. Example 5

The sub-band gap voltage reference in Figure 17 is suitable for implementation in pure CMOS techno-logies where only lateral PNP bipolar transistors are available. The term “sub-band gap” refers to a classical band gap voltage reference where the temperature independent output voltage is scaled down to values below 1.2V. The scaling factor must also be independent on temperature.

Figure 17. CMOS sub-band gap reference with lateral PNP transistors

The calculation of the output voltage starts with Kirchhoff’s voltage law written for the Widlar mirror formed by the lateral PNP transistors Q1-Q2 and the resistor R1.

21 2 1 11 2 2 1 2

1 1 2 1 1 2

ln lnSEB EB T TEB EB

S

IV V V I V IV V I R I NR R I I R I

(59)

If the gain of the opamp is sufficiently large, then its input voltages are maintained equal by the nega-tive feedback and the transistor pair M1-M2 acts as a balanced current mirror, forcing the equality I1=I2. This current is also copied to the drain of M3. The balance of current at the output node leads to

52 3 4 5 3 2 4 5 2

4 5 3 4 5

out outV V RI I I I I I I I IR R R R R

(60)

The output voltage is written

3 3 2out EBV V I R (61)

Replacing I3 and then I2 into (61) gives

53 2

1 4 5 3 4 5

ln out outTout EB

V V RVV V R NR R R R R R

(62)

After rearranging the terms and solving the equation, Vout results

3 4 5 2

3 33 4 5 2 3 5 1

( )( )

lnout EB T EB T

f Tf T

R R R RV V V N V VR R R R R R R

, (63)

where the scaling factor β is always smaller than unity and independent on temperature.


17

1.4.6. Example 6

Another sub-band gap reference, implemented in bipolar technologies, is illustrated in Figure 18. This reference is based on the Brokaw cell in which the output voltage is scaled with a temperature independent factor that is smaller than unity.

Figure 18. Bipolar sub-band gap voltage reference

The output voltage is written similarly as for the simple Brokaw cell:

1 1 1 2 3out BEV V R I I I , (64)

where I1=I2, an equality ensured by the opamp and the feedback, while I3 is expressed as a function of Vout.

73

5 6 7

outV RIR R R

(65)

The current I2 is found from Kirchhoff’s voltage law written for the Q1-Q2-R2 loop:

21 2 11 2 2 2 2

2 2 2 1 2

ln lnSBE BE T TBE BE

S

IV V V I VV V I R I NR R I I R

(66)

After replacing I2 and I3 into the equation (64), it results:

71 1

2 5 6 7

2 ln outTout BE

V RVV V R NR R R R

(67)

The final expression of Vout is then

5 6 7 1

1 15 6 7 1 7 2

( )( )

2 lnout BE T BE T

f Tf T

R R R RV V V N V VR R R R R R

(68)


18

Bibliography

1. P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002 2. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2002 3. D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, 1996 4. P.R.Gray, P.J.Hurst, S.H.Lewis, R.G, Meyer, Analysis and Design of Analog Integrated Circuits,

Wiley,2009 5. R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3rd edition, IEEE Press, 2010

1. current and voltage referencesbel.utcluj.ro/ci/eng/aic/documents/references.pdf · 2018. 10....

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