1 cs/coe0447 computer organization & assembly language multi-cycle execution
TRANSCRIPT
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CS/COE0447
Computer Organization & Assembly Language
Multi-Cycle Execution
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A Multi-cycle Datapath
• A single memory unit for both instructions and data• Single ALU rather than ALU & two adders• Registers added after every major functional unit to hold
the output until it is used in a subsequent clock cycle
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Multi-Cycle ControlWhat we need to cover
• Adding registers after every functional unit– Need to modify the “instruction execution” slides to reflect this
• Breaking instruction execution down into cycles– What can be done during the same cycle? What requires a
cycle? – Need to modify the “instruction execution” slides again– Timing
• Control signal values – What they are per cycle, per instruction– Finite state machine which determines signals based on
instruction type + which cycle it is
• Putting it all together
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Execution: single-cycle (reminder)
• add– Fetch instruction and add 4 to PC add $t2,$t1,$t0– Read two source registers $t1 and $t0– Add two values $t1 + $t0– Store result to the destination register $t1 + $t0 $t2
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A Multi-cycle Datapath
•For add:•Instruction is stored in the instruction register (IR)•Values read from rs and rt are stored in A and B •Result of ALU is stored in ALUOut
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Execution: single-cycle (reminder)
• lw (load word) – Fetch instruction and add 4 to PC lw $t0,-12($t1)– Read the base register $t1– Sign-extend the immediate offset fff4 fffffff4– Add two values to get address X = fffffff4 + $t1– Access data memory with the computed address M[X]– Store the memory data to the destination register $t0
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A Multi-cycle Datapath
•For lw: lw $t0, -12($t1)•Instruction is stored in the IR•Contents of rs stored in A $t1•Output of ALU (address of memory location to be read) stored in ALUOut•Value read from memory is stored in the memory data register (MDR)
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Execution: single-cycle (reminder)
• sw – Fetch instruction and add 4 to PC sw $t0,-4($t1)– Read the base register $t1– Read the source register $t0– Sign-extend the immediate offset fffc fffffffc– Add two values to get address X = fffffffc + $t1– Store the contents of the source register to the compu
ted address $t0 Memory[X]
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A Multi-cycle Datapath
•For sw: sw $t0, -12($t1)•Instruction is stored in the IR•Contents of rs stored in A $t1•Output of ALU (address of memory location to be written) stored in ALUOut
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Execution: single-cycle (reminder)
• beq– Fetch instruction and add 4 to PC beq $t0,$t1,L
• Assume that L is +4 instructions away
– Read two source registers $t0,$t1– Sign Extend the immediate, and shift it left by 2
• 0x0003 0x0000000c
– Perform the test, and update the PC if it is true • If $t0 == $t1, the PC = PC + 0x0000000c
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A Multi-cycle Datapath
•For beq beq $t0,$t1,label•Instruction stored in IR•Registers rs and rt are stored in A and B•Result of ALU (rs – rt) is stored in ALUOut
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Execution: single-cycle (reminder)
• j– Fetch instruction and add 4 to PC– Take the 26-bit immediate field– Shift left by 2 (to make 28-bit immediate)– Get 4 bits from the current PC and attach to
the left of the immediate– Assign the value to PC
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A Multi-cycle Datapath
•For j•No accesses to registers or memory; no need for ALU
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Multi-Cycle ControlWhat we need to cover
• Adding registers after every functional unit– Need to modify the “instruction execution” slides to reflect this
• Breaking instruction execution down into cycles – What can be done during the same cycle? What requires a
cycle? – Need to modify the “instruction execution” slides again– Timing
• Control signal values – What they are per cycle, per instruction– Finite state machine which determines signals based on
instruction type + which cycle it is
• Putting it all together
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• Break up the instructions into steps– each step takes one clock cycle– balance the amount of work to be done in each step/cycle so
that they are about equal– restrict each cycle to use at most once each major functional unit
so that such units do not have to be replicated– functional units can be shared between different cycles within
one instruction
Multicycle Approach
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Operations
•These take time:•Memory (read/write); register file (read/write); ALU operations
•The other connections and logical elements have no latency (for our purposes)
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Five Execution Steps
• Each takes one cycle• In one cycle, there can be at most one memory
access, at most one register access, and at most one ALU operation
• But, you can have a memory access, an ALU op, and/or a register access, as long as there is no contention for resources
• Changes to registers are made at the end of the clock cycle– PC, ALUOut, A, B, etc. save information for the next
clock cycle
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Step 1: Instruction Fetch
• Access memory w/ PC to fetch instruction and store it in Instruction Register (IR)
• Increment PC by 4 – We can do this because the ALU is not being
used for something else this cycle
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Step 2: Decode and Reg. Read
• Read registers rs and rt– We read both of them regardless of necessity
• Compute the branch address in case the instruction is a branch– We can do this because the ALU is not busy– ALUOut will keep the target address
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Step 3: Various Actions
• ALU performs one of three functions based on instruction type (later – cycles per type of instruction; easier to understand)
• Memory reference– ALUOut <= A + sign-extend(IR[15:0]);
• R-type– ALUOut <= A op B;
• Branch:– if (A==B) PC <= ALUOut;
• Jump:– PC <= {PC[31:28],IR[25:0],2’b00};
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Step 4: Memory Access…
• If the instruction is memory reference– MDR <= Memory[ALUOut]; // if it is a load– Memory[ALUOut] <= B; // if it is a st
ore• Store is complete!
• If the instruction is R-type– Reg[IR[15:11]] <= ALUOut;
• Now the instruction is complete!
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Step 5: Register Write Back
• Only the lw instruction reaches this step– Reg[IR[20:16]] <= MDR;
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Multicycle Execution Step (1):Instruction Fetch
IR = Memory[PC];PC = PC + 4;
4PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (2):Instruction Decode & Register
FetchA = Reg[IR[25-21]]; (A = Reg[rs])B = Reg[IR[20-15]]; (B = Reg[rt])ALUOut = (PC + sign-extend(IR[15-0]) << 2)
BranchTarget
Address
Reg[rs]
Reg[rt]
PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (3):Memory Reference Instructions
ALUOut = A + sign-extend(IR[15-0]);
Mem.Address
Reg[rs]
Reg[rt]
PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (4):Memory Access - Write (sw)
Memory[ALUOut] = B;
PC + 4
Reg[rs]
Reg[rt]
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (4):Memory Access - Read (lw)
MDR = Memory[ALUOut];
Mem.Data
PC + 4
Reg[rs]
Reg[rt]
Mem.Address
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (5):Memory Read Completion (lw)
Reg[IR[20-16]] = MDR;
PC + 4
Reg[rs]
Reg[rt]Mem.Data
Mem.Address
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (3):ALU Instruction (R-Type)
ALUOut = A op B
R-TypeResult
Reg[rs]
Reg[rt]
PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (4):ALU Instruction (R-Type)
Reg[IR[15:11]] = ALUOUT
R-TypeResult
Reg[rs]
Reg[rt]
PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (3):Branch Instructions
if (A == B) PC = ALUOut;
BranchTarget
Address
Reg[rs]
Reg[rt]
BranchTarget
Address
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (3):Jump Instruction
PC = PC[31-28] concat (IR[25-0] << 2)
JumpAddress
Reg[rs]
Reg[rt]
BranchTarget
Address
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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For Reference
• The next 5 slides give the steps, one slide per instruction
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Multi-Cycle Execution: R-type
• Instruction fetch– IR <= Memory[PC]; sub $t0,$t1,$t2
– PC <= PC + 4;
• Decode instruction/register read– A <= Reg[IR[25:21]]; rs
– B <= Reg[IR[20:16]]; rt
– ALUOut <= PC + (sign-extend(IR[15:0])<<2);
• Execution– ALUOut <= A op B; op = add, sub, and, or,…
• Completion– Reg[IR[15:11]] <= ALUOut; $t0 <= ALU result
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Multi-cycle Execution: lw• Instruction fetch
– IR <= Memory[PC]; lw $t0,-12($t1)– PC <= PC + 4;
• Instruction Decode/register read– A <= Reg[IR[25:21]]; rs– B <= Reg[IR[20:16]];– ALUOut <= PC + (sign-extend(IR[15:0])<<2);
• Execution– ALUOut <= A + sign-extend(IR[15:0]); $t1 + -12 (sign extended)
• Memory Access– MDR <= Memory[ALUOut]; M[$t1 + -12]
• Write-back– Load: Reg[IR[20:16]] <= MDR; $t0 <= M[$t1 + -12]
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Multi-cycle Execution: sw• Instruction fetch
– IR <= Memory[PC]; sw $t0,-12($t1)
– PC <= PC + 4;
• Decode/register read– A <= Reg[IR[25:21]]; rs
– B <= Reg[IR[20:16]]; rt
– ALUOut <= PC + (sign-extend(IR[15:0])<<2);
• Execution– ALUOut <= A + sign-extend(IR[15:0]); $t1 + -12 (sign extended)
• Memory Access– Memory[ALUOut] <= B; M[$t1 + -12] <= $t0
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Multi-cycle execution: beq
• Instruction fetch– IR <= Memory[PC]; beq $t0,$t1,label– PC <= PC + 4;
• Decode/register read– A <= Reg[IR[25:21]]; rs– B <= Reg[IR[20:16]]; rt – ALUOut <= PC + (sign-extend(IR[15:0])<<2);
• Execution– if (A == B) then PC <= ALUOut;
• if $t0 == $t1 perform branch
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Multi-cycle execution: j
• Instruction fetch– IR <= Memory[PC]; j label– PC <= PC + 4;
• Decode/register read– A <= Reg[IR[25:21]];– B <= Reg[IR[20:16]];– ALUOut <= PC + (sign-extend(IR[15:0])<<2);
• Execution– PC <= {PC[31:28],IR[25:0],”00”};
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Multi-Cycle ControlWhat we need to cover
• Adding registers after every functional unit– Need to modify the “instruction execution” slides to reflect this
• Breaking instruction execution down into cycles– What can be done during the same cycle? What requires a
cycle? – Need to modify the “instruction execution” slides again– Timing
• Control signal values – What they are per cycle, per instruction– Finite state machine which determines signals based on
instruction type + which cycle it is
• Putting it all together
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Datapath w/ Control Signals
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Final Version w/ Control
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Examplefrom beginning to end
• lw $t0,4($t1)
• Machine code: opcode rs rt immediate• 100011 01001 01000 0000 0000 0000 0100• IR[31:26] IR[25:21] IR[20:16] IR[15:0]
rt rs
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Multi-cycle Execution: lw• Instruction fetch
– IR <= Memory[PC]; lw $t0,-12($t1)– PC <= PC + 4;
• Instruction Decode/register read– A <= Reg[IR[25:21]]; rs– B <= Reg[IR[20:16]];– ALUOut <= PC + (sign-extend(IR[15:0])<<2);
• Execution– ALUOut <= A + sign-extend(IR[15:0]); $t1 + -12 (sign extended)
• Memory Access– MDR <= Memory[ALUOut]; M[$t1 + -12]
• Write-back– Load: Reg[IR[20:16]] <= MDR; $t0 <= M[$t1 + -12]
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Example: Load (1)
01 0 0
1
01
00
1
00
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Example: Load (2)
0
00
11
rs
rt
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Example: Load (3)
10
1
00
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Example: Load (4)
11 0
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Example: Load (5)
1
1
0
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Example: Jump (1)
01 0 0
1
01
00
1
00
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Example: Jump (2)
0
00
11
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Example: Jump (3)
1
10
1
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52
A FSM State Diagram
this one is wrong; RegDst = 0; MemToReg = 1
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Multicycle Control Step (1):Fetch
IR = Memory[PC];PC = PC + 4;
1
0
1
0
1
0X
0X
0010
1
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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Multicycle Control Step (2):Instruction Decode & Register
FetchA = Reg[IR[25-21]]; (A = Reg[rs])B = Reg[IR[20-15]]; (B = Reg[rt])ALUOut = (PC + sign-extend(IR[15-0]) << 2);
0
0X
0
0X
3
0X
X
010
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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0X
Multicycle Control Step (3):Memory Reference Instructions
ALUOut = A + sign-extend(IR[15-0]);
X
2
0
0X
0 1
X
010
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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Multicycle Control Step (3):ALU Instruction (R-Type)
ALUOut = A op B;
0X
X
0
0
0X
0 1
X
???
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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1 if Zero=1
Multicycle Control Step (3):Branch Instructions
if (A == B) PC = ALUOut;
0X
X
0
0
X0 1
1
011
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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Multicycle Execution Step (3):Jump Instruction
PC = PC[21-28] concat (IR[25-0] << 2);
0X
X
X
0
1X
0 X
2
XXX
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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Multicycle Control Step (4):Memory Access - Read (lw)MDR = Memory[ALUOut];
0X
X
X
1
01
0 X
X
XXX
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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Multicycle Execution Steps (4)Memory Access - Write (sw)Memory[ALUOut] = B;
0X
X
X
0
01
1 X
X
XXX
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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10
0X
0
X
0
XXX
X
X
1
15 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
0
1
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
Multicycle Control Step (4):ALU Instruction (R-Type)
Reg[IR[15:11]] = ALUOut; (Reg[Rd] = ALUOut)
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Multicycle Execution Steps (5)Memory Read Completion (lw)
Reg[IR[20-16]] = MDR;
1
0
0
X
0
0X
0 X
X
XXX
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
0
1
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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63
Multi-Cycle ControlWhat we need to cover
• Adding registers after every functional unit– Need to modify the “instruction execution” slides to reflect this
• Breaking instruction execution down into cycles– What can be done during the same cycle? What requires a
cycle? – Need to modify the “instruction execution” slides again– Timing: Registers/memory updated at the beginning of the next
clock cycle
• Control signal values – What they are per cycle, per instruction– Finite state machine which determines signals based on
instruction type + which cycle it is • Putting it all together
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For reference
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65
A FSM State Diagram
this one is wrong; RegDst = 0; MemToReg = 1
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66
State Diagram, Big Picture
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Handling Memory Instructions
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R-type Instruction
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Branch and Jump
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FSM Implementation
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71
To Summarize…
• From several building blocks, we constructed a datapath for a subset of the MIPS instruction set
• First, we analyzed instructions for functional requirements
• Second, we connected buildings blocks in a way to accommodate instructions
• Third, we refined the datapath and added controls
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To Summarize…
• We looked at how an instruction is executed on the datapath in a pictorial way
• We looked at control signals connected to functional blocks in our datapath
• We analyzed how execution steps of an instruction change the control signals
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73
To Summarize…
• We compared a single-cycle implementation and a multi-cycle implementation of our datapath
• We analyzed multi-cycle execution of instructions
• We refined multi-cycle datapath
• We designed multi-cycle control
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74
To Summarize…
• We looked at the multi-cycle control scheme in detail
• Multi-cycle control can be implemented using FSM
• FSM is composed of some combinational logic and memory element
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Summary
• Techniques described in this chapter to design datapaths and control are at the core of all modern computer architecture
• Multicycle datapaths offer two great advantages over single-cycle– functional units can be reused within a single instruction if they are
accessed in different cycles – reducing the need to replicate expensive logic
– instructions with shorter execution paths can complete quicker by consuming fewer cycles
• Modern computers, in fact, take the multicycle paradigm to a higher level to achieve greater instruction throughput: – pipelining (later class) where multiple instructions execute
simultaneously by having cycles of different instructions overlap in the datapath
– the MIPS architecture was designed to be pipelined