1 cs612 algorithms for electronic design automation cs 612 – lecture 1 course overview mustafa...
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CS612 Algorithms for Electronic Design Automation
CS 612 – Lecture 1
Course Overview
Mustafa Ozdal Computer Engineering Department, Bilkent University
Mustafa Ozdal
2CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University
What is EDA?
Stands for Electronic Design Automation a.k.a VLSI CAD
Software tools to support engineers in the creation of new IC designs.
EDA tools significantly reduce the cost and time-to-market of new projects. A CPU can easily contain > 1B transistors in a single chip Manual design is prohibitive
3CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University
What is EDA?
Solves a wide-range of problems high-level system design to fabrication (and everything in between)
Strong software skills required
This course will cover the physical design problems Abstract and algorithmic problems No EE knowledge needed
4CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University
Why Study EDA Algorithms?
You may consider a career in the EDA field EDA companies: Synopsys, Cadence, Mentor Graphics, … Design companies: Intel, IBM, Apple, AMD, Nvidia, TI,
Qualcomm, ARM, TSMC, … You may be working in a related field
e.g. Computer architecture: What is the hardware cost, energy cost, etc. of a new feature?
e.g. Scientific computing: Common algorithms used in both domains (e.g. graph partitioning, clustering, etc.)
You may want to improve your algorithmic skills We will study algorithms for abstract problems that also occur in
other domains. e.g. routing, rectangle packing, partitioning, etc.
5CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University
Course Overview
Schedule:Lecture: Tue. 13:40-14:30 EA502
Lecture: Thu. 15:40-17:30 EA502
Spare Hour: Tue. 14:40:15:30
Course project: More in-depth study of a topic
Literature survey + implementation + experiments Presentation (survey + plans) Final report (implementation + experiments + conclusions)
6CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University
Sneak Preview of the Problems
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning
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Circuit: 1
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4
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Partitioning Problem
Partition the netlist into 2 equal parts (i.e. each part must have 4 gates)such that the # of edges between two partitions is minimized.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning
© K
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Lien
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Circuit:
Cut ca: four external connections
1
2
4
5
3
6
7 8
5
6
48
7 23
1
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48
7 2
3 1
Cut ca
Cut cb
Block A Block B Block A Block B
Cut cb: two external connections
Partitioning Problem
How to do this for > 1M gates?
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning
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Floorplanning Problem
ExampleGiven: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1
Task: Floorplan with minimum total area enclosed
A
A
A
B
BC
C
A
BC
4
3
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning
© K
LMH
Lien
ig 10
Floorplanning Problem
ExampleGiven: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1
Task: Floorplan with minimum total area enclosed
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning
© K
LMH
Lien
ig 11
Floorplanning Problem
Solution:Aspect ratiosBlock A with w = 2, h = 2; Block B with w = 2, h = 1; Block C with w = 1, h = 3
This floorplan has a global bounding box with minimum possible area (9 square units).
ExampleGiven: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1
Task: Floorplan with minimum total area enclosed
How to do this for 1000s of blocks?
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Placement
A
C
B
D
E
F
B D F
A C E
A C B
E D F
Which is better?
More wirelengthHarder routing
Less wirelengthEasier routing
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Placement as an Optimization Problem
Place all cells in the netlist such that:Minimize chip areaMinimize wire lengthMake routing easySatisfy timing constraints
Keep cells on critical paths closer
Satisfy various other design constraints
A typical design can have > 1M cells
NP-complete problem
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing
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011
Spr
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C
D
A
B
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1
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654
Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5}
N4 = {B1, A1, C3}
Technology Information (Design Rules)
Placement result
Routing Problem
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing
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011
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Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5}
N4 = {B1, A1, C3}
Technology Information (Design Rules)
Routing Problem
C
D
A
B
43
21
4
3
4
1
1
654
N1
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing
© K
LMH
Lie
nig
© 2
011
Spr
inge
r V
erla
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16
Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5}
N4 = {B1, A1, C3}
Technology Information (Design Rules)
Routing Problem
C
D
A
B
43
21
4
3
4
1
1
654
N2 N3N4 N1
How to do this for > 1M nets?