1 course introduction purpose this training course provides an overview of the architecture of the...
TRANSCRIPT
1
Course Introduction
Purpose
• This training course provides an overview of the architecture of the R8C series microcontrollers (MCUs).
Objectives
• Learn the basic characteristics of the R8C architecture.
• Understand the differences between the architectures of the R8C Tiny series MCUs and M16C series devices.
Content
• 20 pages
• 4 questions
Learning Time
• 30 minutes
2
The M16C MCU Platform
Ultra Performance
32-bit Performance
16-bit “Sweet Spot”
8- to 16-bit Transition
Platform Entry Device
High Performance
Per
form
ance
P
oin
t8
-Bit
16-
Bit
32-
Bit
M32C Core
M32C/10x
M32C/8x
M16C/6x
M16C/2x
R8C Tiny
M32C/9x
R8C Core Covered in this training course
M16C Core Covered in other training courses
3
General Features
M16C core 16-bit CPU• 8-bit internal data bus (M16C has a 16-bit internal bus.)
Register-based architecture• 4 x 16-bit, 4 x 8-bit, 2 x 32-bit (2 sets)• 2 x 16-bit address registers• 2 x 16-bit base registers
89 basic instructions (two less than M16C)• Hardware multiplier is a standard core feature.
Eight standard addressing modesUp to 20MHz operation
• 50ns execution of shortest instruction
Low-power modes
4
CPU Core/Register Model
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
08 / 0
8 / 0 0
0
0
0
17 / 0
015
31 / 15
15
15
15
15 / 7
15 / 7
7
7
8 bits
16 bits
SB 015
ISP
USP
0
015
15
FLG
PC
INTB
0
0
019
19
15
Data Registers2 x 32-bit registers (R0R2 , R1R3) or4 x 16-bit registers (R0, R1, R2 , R3) or4 x 8-bit registers (R0L, R0H, R1L, R1H)
20 bits
Address Registers2 x 16-bit address/general-purpose Register (A0, A1)1 x 32-bit address register [A0A1]
Base RegistersSB and FB registers can be used in indexed addressing modes (e.g., C-language stack frame addressing)
Control Registers2 stack pointers allow H/W interrupt stack and OS stack
Flag Register – Condition flags and interrupt priority
20-bit Program Counter
Interrupt Table Pointer allows multiple Interrupt Vector Tables
Click each register to learn more.
5
Question
What are the general features of the R8C architecture? Select all that apply and then click Done.
91 basic instructions
Register-based architecture
16-bit internal data bus
Up to 20MHz operation
Done
6
Register Bank 0, Register Bank 1
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
08 / 0
8 / 0 0
0
0
0
16 / 0
015
31 / 16
15
15
15
15 / 7
15 / 7
7
7 R0H R0L
R1H R1L
R2
R3
A0
A1
FB
08 / 0
8 / 0 0
0
0
0
16 / 0
015
31 / 15
15
15
15
15 / 7
15 / 7
7
7
SB 015
ISP
USP
0
015
15
FLG
PC
INTB
0
0
019
19
15
Bank 0 Active when bank bit “B” in flag register = 0
(default state)
Bank 1 Active when bank bit
“B” in flag register = 1
Single set of registers Always active, regardless
of bank bit “B”
Click each set of registers to learn more.
7
IPL : Processor interrupt priority level (Interrupt Priority Level ) Levels 0 to 7 set by software or hardware.
U : Stack pointer select flag (When U=0, the ISP is selected; when U=1, the USP is selected.)
I : Interrupt enable flag (When I=1, the interrupt is enabled.)
O : Overflow flag (This bit is set when an arithmetic operation generates an overflow.)
B : Register bank select flag (When B=0, register bank 0 is selected; when B=1, register bank 1 is selected. )
S : Sign flag (This bit is set when an arithmetic operation results in a negative value; otherwise, this bit is 0. )
Z : Zero flag (This bit is set when an arithmetic operation results in 0; otherwise, this bit is 0. )
D : Debug flag (This flag enables a single-step interrupt. When D=1, a single-step interrupt is generated after an instruction is executed. When an interrupt is acknowledged, this flag is cleared to 0. )
C : Carry flag (This flag holds a carry, borrow, or shifted-out bit that has occurred in the arithmetic/logic unit. )
Mouse over the IPL, U, I, O, B, S, Z, D, and C fields in the register to learn more.
Configuration of Flag Register
FLG
IPL U I O B S Z D C
b15 b0
: Reserved area
8
Memory Map
Internal Reserved Area
External Memory Area
SFR Area
Internal ROM Area
0000016
003FF16
0040016
FFE0016
FFFFF16
Internal RAM Area
Fixed Vector Table Area
E000016
02BFF1602C0016
0400016
Internal Reserved Area D000016
M16C/60 SeriesSFR Area
Internal ROM Area
0000016002FF16
0040016
FFFFF16
Internal RAM Area
Fixed Vector Table Area
01FFF16
0200016
Reserved Area
R8C/10 Series
0FFFF16
1000016
Mouse over R8C/10 Series and M16C/60 Series for a review of their operation modes.
.
Modes Operated:
• Single-Chip
Modes Operated:
• Single-Chip
• Memory Expansion
• Microprocessor
9
Cycle Times and Data Accesses
• An instruction cycle is equal to the CPU clock cycle time.
− In Divide-by-1 mode, single-cycle instructions execute in one clock period. For example, with a 20MHz clock, the shortest instruction executes in 50ns.
• Accesses to internal RAM and ROM or Flash for data are single cycle for the M16C core.
• When accessing Word (16-bit) data, the R8C CPU must access the memory space twice, in 8-bit units.
− Due to the 8-bit data bus, getting 16-bit data from RAM takes two cycles. Getting 8-bit data takes only one cycle, the same as the M16C.
• SFR accesses always take four cycles for R8C MCUs.
− The M16C CPU takes two cycles for SFR accesses.
10
Instruction Set
ADD, ADDC, ADDCF, SUB, SUBB, MUL, MULUU,
DIV, DIVU, DIVX, DADD, DADC, DSUB, DSBB,
INC, DEC, RMPA, CMP, ABS, EXTS, NEG
Arithmetic (21)
JMP, JCnd, JMPI, JMPS*, JSR, JSRI, JSRS*, RTS, ADJNZ, SBJNZBranch (8)
LDC, STC, LDINTB, LDIPL, PUSHC, POPC, FSET, FCLR, LDCTX, STCTX, ENTER, EXITD, BRK, REIT, INT, INTO, UND, WAIT, NOP
Control/Other (19)
SMOVF, SMOVB, SSTRString (3)
BCLR, BSET, BNOT, BTST, BNTST, BAND, BNAND, BOR, BNOR, BXOR, BXNOR, BCmd, BTSTS, BTSTCBit Manipulation (14)
AND, OR, XOR, NOT, TXT, SHL, SHA, ROT, RORC, ROLCShift/Logic (10)
MOV, MOVA, PUSH, PUSHM, PUSHA, POP, POPM, LDE, STE, MOVDir, XCHG, STZ, STNZ, STZXData Transfer (14)
InstructionsTypes of Operations
R8C instruction set is same as M16C set except two instructions are deleted:- JMPS (Jump Special Page) - JSRS (Jump Subroutine Special Page) Deleted from R8C
11
Question
FLG
IPL I S Z D
b15 b0
: Reserved area
A
B
C
D
O: Overflow flag
B: Register bank select flag
U: Stack pointer select flag
C: Carry flag
Match each Flag register function to its correct sequence by dragging the letters on the left to the corresponding location on the Flag register. Click Done when you are finished.
C A B D
Done ResetShow
Solution
12
C Language Instructions
main( ) {
int i, j ;
i = j = 0 ; i = j + 5 ;
}
……
……
……
.
2 int. areas(total of 4 bytes)
Return from Function.
ENTER #4
EXITD
Creates Stack Frame
[ 3-byte instruction ]
[ 2-byte instruction ]
SPReturn address
Return address
FBSP
Return address
FBFB
Return address
FBFB
j
iSP
Return address
FBSP
Remove Auto Area
Return (Restore PC)
Put SP to FB Move SPby 4-byte
Save FB
Removes Stack Frame
Return address
FB FB
j
iSP
Return address
SP
Restore FB
SP
PC saved by JSR
Mouse over ENTER and EXITD to learn more.
13
Addressing Modes
abs16,abs20Absolute
displacement is signeddsp:8[SP]SP Relative
displacement is signeddsp:8[FB]FB Relative
CommentSymbolAddressing Mode
jump commandsProgram-counter Relative
(special addressing mode)
displacement is unsigneddsp:8[SB]
dsp:16[SB]
SB Relative
dsp:8[An]
dsp:16[An]
dsp:20[An]
Address Register Relative
[An]Address Register Indirect
RnRegister Direct
#imm:8/16Immediate
Click the nine addressing modes to learn more.
14
Clock Generating Circuit
Main clock oscillator circuit:
• Operates at frequencies up to 20MHz
• Provides an Oscillation-Stop Detect feature
– Includes high-speed and low-speed On-chip oscillator
On-chip oscillator circuit:
• Allows operation without an external crystal
• Options to select 125kHz or 8MHz
• Has high-speed ring frequency adjustment register
15
Circuit
High-speedring oscillator
Low-speedring oscillator
S Q
R
S Q
R
Voltagedetection
circuit
Oscillationstop
detection
Divider
HR00
CM14
CM10
HR01=1
HR01=0
fRING-fast
fRING
fRING128
f1
f1SIO
fAD
f2
f8
f8SIO
f32
f32SIO
CM05
CM02
WAIT instruction
RESET
Hardware reset2
Power on reset
Interrupt request level
Voltage detection interrupt
1/128
XINXOUT
OCD2=0
OCD2=1
CPU clock(BCLK)
CM13
Peripheralfunction clock
Ring oscillatorclock
Mainclock
16
Operating Modes and Transitions
On-chip oscillatorLow-SpeedHigh-Speed
Main ClockMedium-Speed
Divide by 8
Main ClockHigh-Speed
Medium-Speed
Low-SpeedOn-chip oscillator
Divide by 8
RESET MODE
STOP MODE WAIT MODE
All Oscillators Stopped
CPU Clock Stopped
NORMAL MODE
17
Question
When an R8C Tiny series MCU enters Normal mode from RESET, which of the following statements are true? Select all that apply and then click done.
The clock will be in Divide-by-8 mode.
The default clock will be the main clock.
The clock will be in Divide-by-1 mode.
The CPU will be in Wait mode.
The default clock will be the low-speed On-chip oscillator.
Done
18
Flash MCU Power Consumption
175µW35µA125kHz ring osc.3V
12mW5mA10MHz 3V
24mW8mA20MHz3V
PowerConsumption
Icc(typical)
ClockVccOperating Mode
2.1mW0.7µA______3V
4µW0.8µA______5VStop
190µW38µA125kHz ring osc.5VWait
45mW9mA20MHz5VActive
R8C/11
19
Interrupts
BRKKey input interruptA/DINT0_INT1_INT2_INT3_UART0 transmitUART0 receiveUART1 transmitUART1 receiveSoftware Interrupts (32 interrupt sources)
Interrupt Sources
Different Interrupt SourcesCompare 1Compare 0 Timer XTimer YTimer ZTimer C
Click the green box for a list of the different interrupt sources.
20
Question
Which of the following are differences between the R8C and M16C CPU core architectures? Select all that apply and then click Done.
16-bit CPU core
8-bit data busBit-manipulation instructionsProcessor modesRegister setReset Vector Table locationAddressing modes
Done
21
Course Summary
Overview of the R8C CPU core architecture
Differences with M16C architecture
Register set, instructions, and addressing modes
Clock circuits, operating modes, power consumption, and interrupt sources