1 computer architecture part ii-b: cpu instruction set
TRANSCRIPT
![Page 1: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/1.jpg)
1
Computer ArchitectureComputer Architecture
Part II-B: CPU Instruction Set
![Page 2: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/2.jpg)
2
Levels of RepresentationLevels of Representation
High Level Language Program
Assembly Language Program
Machine Language Program
Control Signal Specification
Compiler
Assembler
Machine Interpretation
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
mov BL, 02hmov AX,0A56hmul BL
0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
ALUOP[0:3] <= InstReg[9:11] & MASK
![Page 3: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/3.jpg)
3
Instruction Set DesignInstruction Set Design
instruction set
software
hardware
Which is easier to change?
![Page 4: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/4.jpg)
4
Instruction SetInstruction Set
The set of machine level instructions for a particular type of computer or hardware
![Page 5: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/5.jpg)
5
Instruction CycleInstruction Cycle
The sequence of operations involved in processing an instruction
![Page 6: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/6.jpg)
6
Instruction CycleInstruction CycleInstruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
Obtain instruction from program storage
Determine required actions and instruction size
Locate and obtain operand data
Compute result, value or status
Deposit results in storage for later use
Determine successor instruction
![Page 7: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/7.jpg)
7
CPU-Memory HandshakeCPU-Memory Handshake
The CPU operates, then memory There is a need for synchronization
between CPU and memory Can be done through handshaking
Memory can inform the CPU that it has completed its read/write request through a Memory Function Complete (MFC) signal
![Page 8: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/8.jpg)
8
Types of ControlTypes of Control
Hardwired Microprogrammed
![Page 9: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/9.jpg)
9
Hardwired ControlHardwired Control
Pure hardware mode of control The control unit tells the rest of the CPU
what is to be done every clock cycle during the execution of instructions
Involves complex circuit design
![Page 10: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/10.jpg)
10
Hardwired Control ConsiderationsHardwired Control Considerations
Fast Everything is done through hardware
Permanent Difficult and costly to do modifications
Difficult to implement in a large instruction set
![Page 11: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/11.jpg)
11
Microprogrammed ControlMicroprogrammed Control
Each instruction is broken down into a series of steps, i.e. microinstructions (or microcode) The control unit becomes a miniature
computer The complete set of steps for each
instruction is stored in a ROM called the control store, and is executed sequentially
![Page 12: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/12.jpg)
12
Microprogrammed ControlMicroprogrammed Control
Decoding involves obtaining the starting address in the control store of the first control word (or microinstruction) for the instruction
![Page 13: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/13.jpg)
13
Microprogrammed Control Microprogrammed Control Considerations Considerations
Flexible Only the control store needs
modifications to implement/modify instruction execution
Slower May require more hardware
![Page 14: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/14.jpg)
14
Microprogrammed Control UnitsMicroprogrammed Control Units
Introduced by IBM in 1964 Microprogrammed control units have
seen widespread use for several reasons: Easy to implement complex instructions Cost of microprogramming is far less than
the cost of implementing a conventional hardwired control unit
Easy to add instructions and/or modify existing ones
![Page 15: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/15.jpg)
15
CISC and RISCCISC and RISC
There are two schools of thought on instruction set design: Complex instruction set computers
(CISC) Reduced instruction set computers
(RISC)
![Page 16: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/16.jpg)
16
Complex Instruction Set Complex Instruction Set Computers (CISC)Computers (CISC)
Upward compatibility New processor designs had to provide
more power over older models while maintaining compatibility
More complex and powerful instructions! Generally requires the use of
microcode Easily benefits from improved
technology
![Page 17: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/17.jpg)
17
CISCCISC
Richer or more complex instruction sets simplify compiler design Reduced software development and
learning costs More powerful instructions means
fewer instructions are needed to implement software routines Reduced system memory and bandwidth
requirements
![Page 18: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/18.jpg)
18
CISC IssuesCISC Issues
The more complex the instruction set, the larger the required control store
Compilers tend to make use of few of the available instructions
80/20 rule: Analysis of the instruction mix generated by CISC machines shows that 80% of the instructions executed used only 20% of the instructions set
![Page 19: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/19.jpg)
19
CISC IssuesCISC Issues
CISC designers may have introduced a lot of instructions simply because it was easy to do OR because its competitors did so
Manufacturing cost is increased because of the need to test all operations and combinations of operations
Design cost is increased for future systems because of the need to maintain upward or forward compatibility
![Page 20: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/20.jpg)
20
Reduced Instruction Set Reduced Instruction Set Computers (RISC)Computers (RISC)
80/20 rule: If the most often used instructions (the 20%) was speeded up then the performance benefits would be greater
Studies showed that these instructions tend to perform simpler operations and would use only the simpler addressing modes
Complex operations can still be done by using several simpler operations
![Page 21: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/21.jpg)
21
Why RISC?Why RISC?
Basic hardware is simpler to implement Easier to adopt hardwired control.
Easier to compile for a RISC than a CISC architecture
Design effort and development cost is less for RISC than for a CISC processor
![Page 22: 1 Computer Architecture Part II-B: CPU Instruction Set](https://reader035.vdocuments.mx/reader035/viewer/2022070404/56649f335503460f94c50710/html5/thumbnails/22.jpg)
22
RISC CPU CharacteristicsRISC CPU Characteristics
Fewer instructions More CPU registers More instructions needed to execute
routines May mean more memory space and
increased bandwidth requirements