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COMP541COMP541

More on More on State MachinesState Machinesand Video Scanoutand Video Scanout

Montek SinghMontek Singh

Feb 13, 2007Feb 13, 2007

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OutlineOutline Look at Verilog coding practicesLook at Verilog coding practices Types of state machinesTypes of state machines How to generate video signalHow to generate video signal

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Good Verilog PracticesGood Verilog Practices Best to use single clock for all FFsBest to use single clock for all FFs

Make all signals synchronousMake all signals synchronous Avoids “weird” and frustrating problemsAvoids “weird” and frustrating problems

Multiple modulesMultiple modules Tested individuallyTested individually

One module per fileOne module per file Just to make it easier to follow and testJust to make it easier to follow and test

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Assignment (of signals)Assignment (of signals) ContinuousContinuous ProceduralProcedural

Note there are two uses for Note there are two uses for alwaysalways To generate FFs and latches (plus gates)To generate FFs and latches (plus gates) Combinational onlyCombinational only

Latter does not introduce unnecessary FFsLatter does not introduce unnecessary FFs If synthesizer detects all possibilities covered (i.e. no If synthesizer detects all possibilities covered (i.e. no

state)state)

Look at the synthesizer logLook at the synthesizer log

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Procedural Assignment 1Procedural Assignment 1

module C2(output reg C = 0, input A, input B);module C2(output reg C = 0, input A, input B);

always @ (A or B)always @ (A or B)

case ({A, B})case ({A, B})

2'b11: C <= 1;2'b11: C <= 1;

default: C <= 0;default: C <= 0;

endcaseendcase

endmoduleendmodule

Schematic next pageSchematic next page

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SchematicSchematic

LUT is a look-up tableLUT is a look-up table Double clicking it showsDouble clicking it shows

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Procedural Assignment 2Procedural Assignment 2module C1(output reg C = 0, input A, input B);module C1(output reg C = 0, input A, input B);

always @ (A or B)always @ (A or B)beginbegin

if(A == 1 && B == 1)if(A == 1 && B == 1)C <= 1;C <= 1;

endendendmoduleendmodule

Synthesizer now saysSynthesizer now saysWARNING:Xst:737 - Found 1-bit latch for signal <C>.WARNING:Xst:737 - Found 1-bit latch for signal <C>.WARNING:Xst:1426 - The value init of the FF/Latch C hinder the constant WARNING:Xst:1426 - The value init of the FF/Latch C hinder the constant cleaning in the block C1.cleaning in the block C1.

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SchematicSchematic LDE is latchLDE is latch Small box is clock driverSmall box is clock driver

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In fact…In fact… If I change the INIT of C like it saysIf I change the INIT of C like it says

output reg C = 1output reg C = 1 Synthesizer saysSynthesizer says

INFO:Xst:1304 - Contents of register <C> in INFO:Xst:1304 - Contents of register <C> in unit <C1> never changes during circuit unit <C1> never changes during circuit operation. The register is replaced by logic.operation. The register is replaced by logic.

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SchematicSchematic

module C1(output reg C = 1, input A, input B);module C1(output reg C = 1, input A, input B);

always @ (A or B)always @ (A or B)beginbegin

if(A == 1 && B == 1)if(A == 1 && B == 1)C <= 1;C <= 1;

endendendmoduleendmodule

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Types of state machineTypes of state machine Try to explain what synthesizer is doingTry to explain what synthesizer is doing

Read the messages on the consoleRead the messages on the console

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Example State MachineExample State Machine From XST manualFrom XST manual

Small errorSmall error

~x1

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One Always Block One Always Block (simplified – see (simplified – see handout)handout)always@(posedge clk) beginalways@(posedge clk) begin

case (state)case (state) s1: if (x1 == 1'b1) begins1: if (x1 == 1'b1) begin

state <= s2; outp <= 1'b1;state <= s2; outp <= 1'b1; endend else beginelse begin

state <= s3; outp <= 1'b0;state <= s3; outp <= 1'b0; endend

s2: begins2: begin state <= s4; outp <= 1'b1;state <= s4; outp <= 1'b1; endend s3: begins3: begin state <= s4; outp <= 1'b0;state <= s4; outp <= 1'b0; endend s4: begins4: begin state <= s1; outp <= 1'b0;state <= s1; outp <= 1'b0; endend endcaseendcaseendend

~x1

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Synthesis OutputSynthesis OutputSynthesizing Unit <v_fsm_1>.Synthesizing Unit <v_fsm_1>. Related source file is "v_fsm_1.v".Related source file is "v_fsm_1.v". Found finite state machine <FSM_0> for signal <state>.Found finite state machine <FSM_0> for signal <state>. ---------------------------------------------------------------------------------------------------------------------------------------------- | States | 4 || States | 4 | | Transitions | 5 || Transitions | 5 | | Inputs | 1 || Inputs | 1 | | Outputs | 4 || Outputs | 4 | | Clock | clk (rising_edge) || Clock | clk (rising_edge) | | Reset | reset (positive) || Reset | reset (positive) | | Reset type | asynchronous || Reset type | asynchronous | | Reset State | 00 || Reset State | 00 | | Power Up State | 00 || Power Up State | 00 | | Encoding | automatic || Encoding | automatic | | Implementation | LUT || Implementation | LUT | ---------------------------------------------------------------------------------------------------------------------------------------------- Found 1-bit register for signal <outp>.Found 1-bit register for signal <outp>. Summary:Summary:

inferred 1 Finite State Machine(s).inferred 1 Finite State Machine(s).inferred 1 D-type flip-flop(s).inferred 1 D-type flip-flop(s).

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Split Output OffSplit Output Off Separate Separate alwaysalways for outp for outp

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Code (see handout for full)Code (see handout for full)always @(posedge clk)always @(posedge clk) case (state)case (state)

s1: if (x1 == 1'b1)s1: if (x1 == 1'b1) state <= s2;state <= s2; elseelse state <= s3;state <= s3; s2: state <= s4;s2: state <= s4; s3: state <= s4;s3: state <= s4; s4: state <= s1;s4: state <= s1; endcaseendcase always @(state)always @(state)

case (state)case (state) s1: outp = 1'b1;s1: outp = 1'b1; s2: outp = 1'b1;s2: outp = 1'b1; s3: outp = 1'b0;s3: outp = 1'b0; s4: outp = 1'b0;s4: outp = 1'b0; endcaseendcase

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Synthesis (no latch)Synthesis (no latch)Synthesizing Unit <v_fsm_2>.Synthesizing Unit <v_fsm_2>. Related source file is "v_fsm_2.v".Related source file is "v_fsm_2.v". Found finite state machine <FSM_0> for signal <state>.Found finite state machine <FSM_0> for signal <state>. ---------------------------------------------------------------------------------------------------------------------------------------------- | States | 4 || States | 4 | | Transitions | 5 || Transitions | 5 | | Inputs | 1 || Inputs | 1 | | Outputs | 1 || Outputs | 1 | | Clock | clk (rising_edge) || Clock | clk (rising_edge) | | Reset | reset (positive) || Reset | reset (positive) | | Reset type | asynchronous || Reset type | asynchronous | | Reset State | 00 || Reset State | 00 | | Power Up State | 00 || Power Up State | 00 | | Encoding | automatic || Encoding | automatic | | Implementation | LUT || Implementation | LUT | ---------------------------------------------------------------------------------------------------------------------------------------------- Summary:Summary:

inferred 1 Finite State Machine(s).inferred 1 Finite State Machine(s).Unit <v_fsm_2> synthesized.Unit <v_fsm_2> synthesized.

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Textbook Uses 3 Textbook Uses 3 alwaysalways Blocks Blocks

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Three Three alwaysalways Blocks Blocks

always @(posedge clk)always @(posedge clk) beginbegin

state <= next_state;state <= next_state; endend

always @(state or x1)always @(state or x1) beginbegin case (state)case (state) s1: if (x1==1'b1)s1: if (x1==1'b1) next_state = s2;next_state = s2; elseelse next_state = s3;next_state = s3; s2: next_state = s4;s2: next_state = s4; s3: next_state = s4;s3: next_state = s4; s4: next_state = s1;s4: next_state = s1; endcaseendcase endend

always @(state)always @(state) beginbegin case (state)case (state) s1: outp = 1'b1;s1: outp = 1'b1; s2: outp = 1'b1;s2: outp = 1'b1; s3: outp = 1'b0;s3: outp = 1'b0; s4: outp = 1'b0;s4: outp = 1'b0; endcaseendcase endend

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Synthesis (again, no latch)Synthesis (again, no latch)Synthesizing Unit <v_fsm_3>.Synthesizing Unit <v_fsm_3>. Related source file is "v_fsm_3.v".Related source file is "v_fsm_3.v". Found finite state machine <FSM_0> for signal <state>.Found finite state machine <FSM_0> for signal <state>. ---------------------------------------------------------------------------------------------------------------------------------------------- | States | 4 || States | 4 | | Transitions | 5 || Transitions | 5 | | Inputs | 1 || Inputs | 1 | | Outputs | 1 || Outputs | 1 | | Clock | clk (rising_edge) || Clock | clk (rising_edge) | | Reset | reset (positive) || Reset | reset (positive) | | Reset type | asynchronous || Reset type | asynchronous | | Reset State | 00 || Reset State | 00 | | Power Up State | 00 || Power Up State | 00 | | Encoding | automatic || Encoding | automatic | | Implementation | LUT || Implementation | LUT | ---------------------------------------------------------------------------------------------------------------------------------------------- Summary:Summary:

inferred 1 Finite State Machine(s).inferred 1 Finite State Machine(s).Unit <v_fsm_3> synthesized.Unit <v_fsm_3> synthesized.

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My PreferenceMy Preference The one with 2 The one with 2 alwaysalways blocks blocks Less prone to error than 1 Less prone to error than 1 alwaysalways Easy to visualize the state transitionsEasy to visualize the state transitions

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State EncodingState Encoding So far we’ve used So far we’ve used binarybinary encoding encoding Not necessarily bestNot necessarily best

XST chooses one to minimize hardwareXST chooses one to minimize hardware

Can change by right-clicking Can change by right-clicking Synthesize-XSTSynthesize-XST

Possible encodings next slidesPossible encodings next slides

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Gray Code (synthesis output)Gray Code (synthesis output)========================================================================================================================* Advanced HDL Synthesis ** Advanced HDL Synthesis *========================================================================================================================

Analyzing FSM <FSM_0> for best encoding.Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <state> on signal <state[1:2]> with gray encoding.Optimizing FSM <state> on signal <state[1:2]> with gray encoding.-------------------------------------- State | EncodingState | Encoding-------------------------------------- 00 | 0000 | 00 01 | 0101 | 01 10 | 1110 | 11 11 | 1011 | 10--------------------------------------

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One-Hot EncodingOne-Hot EncodingOptimizing FSM <state> on signal <state[1:4]> with one-Optimizing FSM <state> on signal <state[1:4]> with one-

hot encoding.hot encoding.-------------------------------------- State | EncodingState | Encoding-------------------------------------- 00 | 000100 | 0001 01 | 001001 | 0010 10 | 010010 | 0100 11 | 100011 | 1000--------------------------------------

Hmmm, state register grew.

What’s up?

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Safe Implementation ModeSafe Implementation Mode “ “XST can add logic to your FSM XST can add logic to your FSM

implementation that will let implementation that will let your state machine recover your state machine recover from an invalid state. If during from an invalid state. If during its execution, a state machine its execution, a state machine gets into an invalid state, the gets into an invalid state, the logic added by XST will bring it logic added by XST will bring it back to a known state, called a back to a known state, called a recovery state. This is known recovery state. This is known as Safe Implementation mode.” as Safe Implementation mode.” from XST manualfrom XST manual

Tuesday’s counter

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How Do Monitors Work?How Do Monitors Work? Origin is TV, so let’s look at thatOrigin is TV, so let’s look at that

LCDs work on different principle, but all signaling still LCDs work on different principle, but all signaling still derived from TV of 1940sderived from TV of 1940s

Relies on your brain to do two thingsRelies on your brain to do two things Integrate over spaceIntegrate over space Integrate over timeIntegrate over time

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Many Still ImagesMany Still Images Video (and movies) a series of stillsVideo (and movies) a series of stills

If stills go fast enough your brain interprets as If stills go fast enough your brain interprets as moving imagerymoving imagery 50-60 Hz or more to not see flicker50-60 Hz or more to not see flicker

In fact, even single “still” image displayed over In fact, even single “still” image displayed over timetime

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Cathode Ray TubeCathode Ray Tube

From wikipedia: http://en.wikipedia.org/wiki/Cathode_ray_tube

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Deflection CoilsDeflection Coils

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Simple Scanning TVSimple Scanning TV Electron beam scans acrossElectron beam scans across Turned off whenTurned off when

Scanning back to the left (horizontal retrace)Scanning back to the left (horizontal retrace) Scanning to the top (vertical retrace)Scanning to the top (vertical retrace)

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ScanningScanning TVs use TVs use interlacinginterlacing

Every other scan line is swept per fieldEvery other scan line is swept per field Two fields per frame (30Hz)Two fields per frame (30Hz) Way to make movement less disturbingWay to make movement less disturbing

Computers use Computers use progressive scanprogressive scan Whole frame refreshed at onceWhole frame refreshed at once 60Hz or more, 72Hz looks better60Hz or more, 72Hz looks better

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ColorColor Three colors of phosphorThree colors of phosphor Beams hit eachBeams hit each Black – beam offBlack – beam off White – all onWhite – all on

Picture is a bit misleading. Mask (or aperture grill) ensures beams hit only correct color phosphor.

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AsideAside Frustrated with VerilogFrustrated with Verilog See what to do to relieve stressSee what to do to relieve stress

http://science.howstuffworks.com/what-if-shoot-tv.htmhttp://science.howstuffworks.com/what-if-shoot-tv.htm

Educational tooEducational too

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VGA SignalingVGA Signaling RGB and two synchronization pulses, RGB and two synchronization pulses,

horizontal and verticalhorizontal and vertical

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VGA TimingVGA Timing You supply two pulses, hsync and vsync, that let the You supply two pulses, hsync and vsync, that let the

monitor lock onto timingmonitor lock onto timing One hsync per scan lineOne hsync per scan line One vsync per frameOne vsync per frame

Image from dell.com

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Horizontal Timing TermsHorizontal Timing Terms hsync pulsehsync pulse Back porch (left side of display)Back porch (left side of display) Active VideoActive Video

Video should be Video should be blankedblanked (not sent) at other times (not sent) at other times Front porch (right side)Front porch (right side)

Picture not accurate for our case; just for illustration.

Video and HSYNC not on same wire

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Horizontal TimingHorizontal Timing

640 Horizontal Dots 640 Horizontal Dots Horiz. Sync Polarity NEG Horiz. Sync Polarity NEG Scanline time (A) 31.77 usScanline time (A) 31.77 usSync pulse length (B) 3.77 usSync pulse length (B) 3.77 usBack porch (C) 1.89 usBack porch (C) 1.89 usActive video (D) 25.17 us Active video (D) 25.17 us Front porch (E) 0.94 usFront porch (E) 0.94 us

Image from http://www.epanorama.net/documents/pc/vga_timing.html

This diagram shows video as a digital signal. It’s not – video is an analog level.

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Vertical Timing (note ms, not us)Vertical Timing (note ms, not us)

Vert. Sync Polarity NEGVert. Sync Polarity NEGVertical Frequency 60HzVertical Frequency 60HzTotal frame time (O) 16.68 ms Total frame time (O) 16.68 ms Sync length (P) 0.06 msSync length (P) 0.06 msBack porch (Q) 1.02 msBack porch (Q) 1.02 msActive video (R) 15.25 msActive video (R) 15.25 msFront porch (S) 0.35 msFront porch (S) 0.35 ms

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Timing as PixelsTiming as Pixels Easiest to derive all timing from single-pixel Easiest to derive all timing from single-pixel

timingtiming

How “long” is a pixel?How “long” is a pixel? Active video / number of pixelsActive video / number of pixels 25.17 us / 640 = 39.32ns25.17 us / 640 = 39.32ns Conveniently close to 25 MHz – just use thatConveniently close to 25 MHz – just use that Actual VESA spec is 25.175 MHzActual VESA spec is 25.175 MHz

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StandardsStandards 640 x 480 (sometimes x 60Hz) is “VGA”640 x 480 (sometimes x 60Hz) is “VGA” I’ll have spec sheets in labI’ll have spec sheets in lab

You can try for 800x600 at 60 Hz (40 MHz exactly) You can try for 800x600 at 60 Hz (40 MHz exactly) or 800x600 at 72 Hz (50 MHz exactly)or 800x600 at 72 Hz (50 MHz exactly)

Note that some standards have vsync and hsync Note that some standards have vsync and hsync positive true, some negative true – choose correct onepositive true, some negative true – choose correct one

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Color DepthColor Depth Voltage of each of RGB determines colorVoltage of each of RGB determines color 2-bit color here (4 shades)2-bit color here (4 shades) Turn all on for whiteTurn all on for white

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What To Do FridayWhat To Do Friday Make Verilog module to generate Make Verilog module to generate

hsync, vsync, horizontal count, vertical count, and hsync, vsync, horizontal count, vertical count, and signal to indicate active videosignal to indicate active video

Use higher-level module to drive RGB using Use higher-level module to drive RGB using counts gated by activecounts gated by active Just do something simple; need to meet 25MHz Just do something simple; need to meet 25MHz

constraintconstraint

Later will use memory addressed by counts to Later will use memory addressed by counts to make terminalmake terminal

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What do you Need for VGA?What do you Need for VGA? Think firstThink first

Need counter(s)?Need counter(s)? Will you need a state machine?Will you need a state machine?

Sketch out a designSketch out a design Block diagramBlock diagram

Go over them individually in labGo over them individually in lab Keep in MindKeep in Mind

Verilog has these operatorsVerilog has these operators ==, <, >, <=, >===, <, >, <=, >=

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VGA LinksVGA Links

VGA TimingVGA Timing http://www.epanorama.net/documents/pc/vga_timing.htmlhttp://www.epanorama.net/documents/pc/vga_timing.html http://appsrv.cse.cuhk.edu.hk/~ceg3480/Tutorial7/tut7.dochttp://appsrv.cse.cuhk.edu.hk/~ceg3480/Tutorial7/tut7.doc

Code (more complex than you want)Code (more complex than you want) http://www.stanford.edu/class/ee183/index.shtmlhttp://www.stanford.edu/class/ee183/index.shtml

InterestingInteresting http://www.howstuffworks.com/tv.htmhttp://www.howstuffworks.com/tv.htm http://computer.howstuffworks.com/monitor.htmhttp://computer.howstuffworks.com/monitor.htm http://www.howstuffworks.com/lcd.htmhttp://www.howstuffworks.com/lcd.htm http://plc.cwru.edu/http://plc.cwru.edu/ Liquid Crystals by S. Chandrasekhar, Cambridge Univ. PressLiquid Crystals by S. Chandrasekhar, Cambridge Univ. Press