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COMP541COMP541

Memories, Part IMemories, Part I

Montek SinghMontek Singh

Feb 27, 2007Feb 27, 2007

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TopicsTopics Overview of Memory TypesOverview of Memory Types

ROMs: PROMs, FLASH, etc.ROMs: PROMs, FLASH, etc. RAMsRAMs

Random-Access Memory (RAM)Random-Access Memory (RAM) Static todayStatic today Dynamic nextDynamic next

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Properties of MemoryProperties of Memory What would you want?What would you want?

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Non-Volatile Memory Non-Volatile Memory TechnologiesTechnologies Mask (old)Mask (old) Fuses (old)Fuses (old) Electrically erasableElectrically erasable

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Details of ROMDetails of ROM Memory that is permanentMemory that is permanent k address linesk address lines 22kk items items n bitsn bits

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Notional View of InternalsNotional View of Internals

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Programmed Truth TableProgrammed Truth Table

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Resulting ProgrammingResulting Programming

In truth, they’re laid out in 2D (row, col)In truth, they’re laid out in 2D (row, col)

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Mask ROMsMask ROMs Oldest technologyOldest technology Originally “mask” used as last step in Originally “mask” used as last step in

manufacturingmanufacturing Specify metal layer (connections)Specify metal layer (connections) Used for volume applicationsUsed for volume applications Long turnaroundLong turnaround Used for applications such as embedded systems and, Used for applications such as embedded systems and,

in the old days, boot ROMin the old days, boot ROM

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Programmable ROM (PROM)Programmable ROM (PROM) First ones had fusible linksFirst ones had fusible links High voltage would blow out linksHigh voltage would blow out links Fast to programFast to program Single useSingle use

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UV EPROMUV EPROM ErasableErasable PROM PROM Common technologies used UV light to erase Common technologies used UV light to erase

complete devicecomplete device Took about 10 minutesTook about 10 minutes

Holds state as charge in very well insulated Holds state as charge in very well insulated areas of the chipareas of the chip

Nonvolatile for several (10?) yearsNonvolatile for several (10?) years

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EEPROMEEPROM Electrically ErasableElectrically Erasable PROM PROM Similar technology to UV EPROMSimilar technology to UV EPROM Erased in blocks by higher voltageErased in blocks by higher voltage Programming is slower than readingProgramming is slower than reading Some called Some called flash memoryflash memory

Digital cameras, MP3 players, BIOSDigital cameras, MP3 players, BIOS Limited lifeLimited life Some support individual word write, some blockSome support individual word write, some block One on Xess board has 5 blocksOne on Xess board has 5 blocks Has a Has a boot blockboot block that is carefully protected that is carefully protected

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Random Access MemoriesRandom Access Memories So called because it takes same amount of So called because it takes same amount of

time to address any particular locationtime to address any particular location This is not quite true for modern DRAMsThis is not quite true for modern DRAMs

First look at asynchronous static RAMFirst look at asynchronous static RAM Ones on Xilinx are synchronousOnes on Xilinx are synchronous

Data available at clock edges, like registersData available at clock edges, like registers

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Simple View of RAMSimple View of RAM Of some word size Of some word size nn Some capacity 2Some capacity 2kk

k bits of address linek bits of address line Maybe have read lineMaybe have read line

Strictly speaking may not needStrictly speaking may not need

Have a write lineHave a write line

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1K x 16 memory1K x 16 memory Variety of sizesVariety of sizes

From 1-bit wideFrom 1-bit wide

Issue is no. of pinsIssue is no. of pins

Memory size often specified in bytesMemory size often specified in bytes This would be 2KB memoryThis would be 2KB memory

10 address lines and 16 data lines10 address lines and 16 data lines

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WritingWriting Sequence of stepsSequence of steps

Setup address linesSetup address lines Setup data linesSetup data lines Activate write line (maybe a pos edge)Activate write line (maybe a pos edge)

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ReadingReading StepsSteps

Setup address linesSetup address lines Activate read lineActivate read line Data available Data available after specified amt of timeafter specified amt of time

Some use a clockSome use a clock

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Chip SelectChip Select Usually a line to Usually a line to enableenable the chip the chip Why?Why?

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WritingWriting

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ReadingReading

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Static vs Dynamic RAMStatic vs Dynamic RAM SRAM vs DRAMSRAM vs DRAM DRAM stores charge in capacitorDRAM stores charge in capacitor

Disappears after short period of timeDisappears after short period of time Must be refreshedMust be refreshed

SRAM easier to useSRAM easier to use Uses transistors (think of it as latch)Uses transistors (think of it as latch) FasterFaster More expensive per bitMore expensive per bit Smaller sizesSmaller sizes

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Structure of SRAMStructure of SRAM Control logicControl logic One memory One memory cellcell per bit per bit

Cell consists of one or more transistorsCell consists of one or more transistors Not really a latch made of NANDs/NORs, but logically Not really a latch made of NANDs/NORs, but logically

equivalentequivalent

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Bit SliceBit Slice

Cells connected to form 1 Cells connected to form 1 bit positionbit position

Word Select gates one Word Select gates one latch from address lineslatch from address lines

Note it selects Reads alsoNote it selects Reads also B (and B’) set by R/W, B (and B’) set by R/W,

Data In and BitSelectData In and BitSelect Funny thing here when Funny thing here when

you write. What is it?you write. What is it?

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Bit Slice can Become ModuleBit Slice can Become Module Basically bit slice is a X1 Basically bit slice is a X1

memorymemory NextNext

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16 X 1 RAM16 X 1 RAM Now shows Now shows

decoderdecoder

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Row/ColumnRow/Column If RAM gets large, there is a large decoderIf RAM gets large, there is a large decoder Also run into chip layout issuesAlso run into chip layout issues Larger memories usually “2D” in a matrix Larger memories usually “2D” in a matrix

layoutlayout Next SlideNext Slide

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16 X 1 RAM as 4 X 4 Array16 X 1 RAM as 4 X 4 Array

Two decodersTwo decoders RowRow ColumnColumn

Address just Address just broken upbroken up

Not visible Not visible from outside from outside on SRAMson SRAMs

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Change to 8 X 2 RAMChange to 8 X 2 RAM Minor change in Minor change in

logiclogic Also pinoutsAlso pinouts What’s different?What’s different?

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Realistic SizesRealistic Sizes Imagine 256K memory as 32K X 8Imagine 256K memory as 32K X 8 One column layout would need 15-bit decoder One column layout would need 15-bit decoder

with 32K outputs!with 32K outputs! Can make a square layout with 9-bit row and Can make a square layout with 9-bit row and

6-bit column decoders6-bit column decoders

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SRAM PerformanceSRAM Performance Current ones have cycle times in low Current ones have cycle times in low

nanoseconds (say 2.5ns)nanoseconds (say 2.5ns) Used as cache (typically onchip or offchip Used as cache (typically onchip or offchip

secondary cache)secondary cache) Sizes up to 8Mbit or so for today’s chipsSizes up to 8Mbit or so for today’s chips

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RAM on FPGARAM on FPGA Ours has 10 4Kb blocks for a total of 40KbitsOurs has 10 4Kb blocks for a total of 40Kbits

They call it They call it block RAMblock RAM Can also use LUTs as RAMCan also use LUTs as RAM Block RAM: Two ports, and 5 possible layoutsBlock RAM: Two ports, and 5 possible layouts

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Using from VerilogUsing from Verilog Instantiate a block (here called R1)Instantiate a block (here called R1)

RAMB4_S8_S8 R1 (.DOA (data_a), RAMB4_S8_S8 R1 (.DOA (data_a), .DOB (data_b), .DOB (data_b), .ADDRA (addr_a), .ADDRA (addr_a), .ADDRB (addr_a), .ADDRB (addr_a), .CLKA (clk), .CLKA (clk), .CLKB (clk), .CLKB (clk), .DIA (data_in), .DIA (data_in), .DIB (data_in), .DIB (data_in), .ENA (ena), .ENA (ena), .ENB (enb), .ENB (enb), .RSTA (rsta), .RSTA (rsta), .RSTB (rstb), .RSTB (rstb), .WEA (wea), .WEA (wea), .WEB (web)); .WEB (web));

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Synthesizer can InferSynthesizer can Infer Careful how you specify (see ISE/XST manual)Careful how you specify (see ISE/XST manual)

module inferRAM(clk, addr, data, we);module inferRAM(clk, addr, data, we);input clk;input clk;input [8:0] addr;input [8:0] addr;// 512 locations// 512 locationsoutput [7:0] data;output [7:0] data; // by 8 bits// by 8 bitsinput we;input we;

reg [7:0] mem [511:0];reg [7:0] mem [511:0];reg [8:0] ra;reg [8:0] ra;

always @ (posedge clk)always @ (posedge clk)beginbegin

if(we)if(we)mem[addr] <= data;mem[addr] <= data;

ra <= addr;ra <= addr;endendassign data = mem[ra];assign data = mem[ra];

endmoduleendmodule

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Can Initialize Block RAMCan Initialize Block RAM Have to do it two ways, one for simulator, Have to do it two ways, one for simulator,

another for hardwareanother for hardware//synthesis attribute INIT_00 of R1 is "08192A3B4C5... total of 256 bits //synthesis attribute INIT_00 of R1 is "08192A3B4C5... total of 256 bits

(64 hex characters)..."(64 hex characters)..."

//synthesis attribute INIT_01 of R1 is //synthesis attribute INIT_01 of R1 is "08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F“"08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F“

// Up to INIT_0F// Up to INIT_0F

Above is for hardware (next software)Above is for hardware (next software)

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For SimulationFor Simulation//synopsys translate_off //synopsys translate_off

defparam R1.INIT_00 = defparam R1.INIT_00 = 64'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B464'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F; // 256-bit hex valueC5D6E7F; // 256-bit hex value

defparam R1.INIT_01 = defparam R1.INIT_01 = 64'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B464'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F; // 256-bit hex valueC5D6E7F; // 256-bit hex value

......defparam R1.INIT_0F = defparam R1.INIT_0F =

64'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B464'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F; // up to INIT_0FC5D6E7F; // up to INIT_0F

//synopsys translate_on //synopsys translate_on

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Look at Test CodeLook at Test Code A RAM exampleA RAM example

Posted online (under Labs)Posted online (under Labs)

Note how memory values are specifiedNote how memory values are specified Addresses go Addresses go right-to-leftright-to-left, top-to-bottom, top-to-bottom See the See the Constraints GuideConstraints Guide and and LibraryLibrary manuals in manuals in

Xilinx docsXilinx docs

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Wider MemoryWider Memory What if you don’t have What if you don’t have

enough bit width?enough bit width?

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Deeper MemoryDeeper Memory Adding chips to increase Adding chips to increase

storage, but keep same storage, but keep same widthwidth

Need decoderNeed decoder

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TodayToday Fast look at non-volatile memoryFast look at non-volatile memory Learned about Static RAMLearned about Static RAM

Specifics: synchronous RAM in FPGASpecifics: synchronous RAM in FPGA

Next: Dynamic RAMNext: Dynamic RAM Complex, largest, cheapComplex, largest, cheap Much more trouble to useMuch more trouble to use