1 basic mos device physics. 2 concepts understanding of semiconductor devices is essential in analog...
TRANSCRIPT
1
Basic MOS Device Physics
2
Concepts
understanding of semiconductor devices is essential in analog IC design Performance affected by second order effects, often neglected in digital design
More for deep submicron technologies
Develop transistor model for circuit performance and analysis MOS structure, IV characteristics, second order
effects, parasitic capacitances, small-signal model for MOSFET ,SPICE model
3
MOS Device Structure
Structure: 2 heavily-doped n regions defining D and
S, heavily-doped polysilicon forming G, thin layer of oxide insulating G from substrate
Useful action occurs in substrate region under gate oxide
4-terminal device, with S and D interchangable
Digital IC: transistor acts like a switchTurns on (S and D “connected together”)
when VG high, off when VG low
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NMOS and PMOS with Well
CMOS – both NMOS and PMOS available on the same substrate Ok for NMOS, but PMOS must define a local n-
substrate -> n-wellNMOS: S/D junction must be reverse-biased ->
substrate connected to most negative supply voltagePMOS: S/D junction must be reverse-biased ->
substrate connected to most positive supply
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MOS Symbols
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triode region I-V characteristic
Triode region when VDS <= VGS - VTH
ID nCoxW
L[(VGS VTH)VDS
1
2VDS
2 ]
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Operation in Triode Region
ID nCoxW
L[(VGS VTH)VDS
1
2VDS
2 ]
ID nCoxW
L(VGS VTH)VDS, VDS 2(VGS VTH)
RON 1
nCoxW
L(VGS VTH)
-> ID linear function of VDS
Parabola approximated by straight line.S-D can now be modelled as a linear controlled-resistor given by VDS/ID and value controlled by overdrive voltage (VGS – VTH)
8
Active Region (cont.)
Active Region
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If VDS > VGS-VTH? I/V curve no longer parabolic ID constant, device in saturation/active region
Density of inversion layer proportional to VGS – V(x) – VTH
If VDS slightly greater that VGS – VTH, inversion layer stops at x <= L; i.e. channel is pinched off
As VDS increases further Point at which Qd equals zero gradually moves toward S
Operation in Active (Saturation) Region
ID nCoxW
L[(VGS VTH)VDS
1
2VDS
2 ]
ID nCox
2
W
L(VGS VTH)2
V 'DS VGS VTH (Pinch off )
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Drain current characteristics
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Drain current
Linear region (Vds < Vgs - Vt): Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5 Vds
2)
Saturation region (Vds >= Vgs - Vt): Id = 0.5k’ (W/L)(Vgs - Vt) 2
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MOS operation conclusion
region VG condition VDS condition ID
OFF VG < VTH Any value 0
TRIODE/ LINEAR
VG >VTH VDS < VDS -VTH nCoxW/L (VDS-VTH)VDS – 0.5VDS
2
SATURATION
VG >VTH VDS > VDS -VTH 0.5nCoxW/L (VDS-VTH)2
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Transconductance, gm
Let’s define gm as an indicator of how well a device converts a voltage to a current (consider saturation region)
gm represents device sensitivity e.g. small change in VGS results in large change in ID
As seen in eqn above, gm is equal to inverse of Ron in deep triode region
gm IDVGS VDS constan t
nCoxW
L(VGS VTH) gm 2nCox
W
LID
2ID
VGS VTH
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gm behavior – from gm plot
Notice: gm increases with overdrive if W/L constant
gm decreases with overdrive if ID constant
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Triode and Active Region Transition
Rule of thumb when trying to know if device is in saturation or linear NMOS: VG - VD < VTHN, pinch-off occurs
PMOS: VD – VG < |VTHP|, saturationActive Active
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Second-Order Effects
Now let’s look at second order effects and get some idea on how our circuit could be affected by the phenomena
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Body Effect
What happens when bulk and source are not at the same potential
Consider NMOS: When VB drops below VS S and D still reverse-biased -> device continues to operate properly
but some device properties might change e.g. VS=VD=0; VG a bit less than VTH -> depletion layer formed but no
inversion layer As VB becomes more negative -> more holes attracted to substrate
connection, leaving larger –ve charge behind (i.e. depletion region becomes wider)
VTH = f(total charge in depln region), and gate charge must mirror Qd (channel charge density) before an inversion layer formed
VB drops, Qd increases, VTH increases -> “Body effect” / “Backgate” Effect
VTH VTH0 2F VSB 2F , 2qsiNsub
Cox
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Body Effect …
denotes body effect coefficient Typical values: 0.3 to 0.4V1/2
Could take place when: Bulk potential change Source potential varies wrt bulk potential
2ox
depFMSTH
C
QV
19
No Body Effect With Body Effect Ignore body effect:
As Vin varies, Vout closely follows the input Drain current remains I1
• I1=0.5nCox(W/L)(Vin-Vout-VTH)2
• i.e. (Vin-Vout) is constant if I1 is constant
Body effect significant, substrate tied to gnd As Vin and Vout become more positive VSB increases -> VTH increases
To maintain constant ID, Vin-Vout must increase as well
Body Effect: Undesirable, complicates design of analog and digital Ics
Nsub and Cox has to be balanced for reasonable device engineers’ job!!!)
VTH and Body Effect
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Noted earlier that VGDL’ (pinch-off) L’=f(VDS) channel length modulation We can then write: Assume 1st order relationship btwn L/L and VDS,
and define as CLM coefficient:
We can re-write current equation in saturation:
L' L L )/1(1
'/1 LLL
L
1/ L' 1
L(1VDS), VDS L / L
ID nCox
2
W
L(VGS VTH)2 (1VDS)
L L’
Channel Length Modulation
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Channel Length Modulation (cont’d…)
CLM results in non-zero slope in IV characteristics Non-ideal current source btwn D and S in saturation regime represents relative variation in length for a given increment in VDS
Short channel -> must consider bcoz it’s bigger compared to longer channels L/L VDS linear approximation becomes less accurate for shorter
channel Re-write equation for current in saturation -> must rewrite equation
for transconductance, gm
gm nCoxW
L(VGS VTH)(1VDS) gm
2nCoxW LID
(1VDS)gm
2ID
VGS VTH, (unchanged)
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Subthreshold Conduction
When VGSVTH, weak inversion layer still exists (transistor do not fully turn off) hence allowing some current flows from D to S ID drops at a finite rate as VGS falls below VTH
Exponential dependence on VGS
> 1 = nonideality factor, VT=kT/q Eqn similar to bipolar’s characteristic
Subthreshold Conduction: Static Power Dissipation (Leakage)
a problem for large circuits (e.g. memory)
ID I0 expVGS
kT q
Subthreshold conduction
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MOS Layout
Brief look at layout to better understand / visualize device capacitance & MOS model
Layout determined by: Electrical properties required of the device & design rules
(e.g. W/L dictates gm, L governed by the process)
(a) 3D view of an NMOS (b) top-view
Poly extends beyond diffusion Ensure reliable definition of edge of transistor Total S and D area minimized to minimize capacitance
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Layout…
Draw layout of circuit in (a)
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Device Capacitances
Need to consider to predict ac behaviorValue of capacitance depends on bias
conditions of transistorSource of capacitance:
Oxide capacitance, Cdepln, Coverlap
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Device cap… cont’d
Oxide capacitance Btwn gate and channel
C1 = WLCox
Depletion capacitance Btwn channel and substrate
C2 = WL(qsiNsub/(4F))
Overlap capacitance C3 and C4, simplest formula WLDCox
More elaborate calculations required for accurate value Junction capacitance
Btwn S/D and substrate Cbottom-plate (Cj) + Cside-wall (Cjsw) Cj = Cjo/[1 + VR/B]m, VR = reverse voltage across junction, B built-in
potential, m a power in between 0.3 and 0.4
27
Layout for Low Capacitance
Folded structureFor layout in (a)
For the same transistor in (b)
Note: (b) has less CDB than (a)
jswjSBDB CEWWECCC )2(
jswj
jswjSB
jswjDB
CEWWEC
CEW
ECW
C
CEECW
C
)4(
)22
(22
2
)(22
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G-S and G-D Capacitance
Device off CGD = CGS = CoverlapW CGB = Cox in series with Cdepln
CoxCdepln/(Cox + Cdepln)
Device in deep triode region (VS VD) CGS = CGD = Cox/2 + overlap cap = WLCox/2 + Wcov
Cox/2 because WLCox divided equally btwn GS and GD terminals• Change V in VG draws equal amount of charge from S and D
Device in saturation CGD Wcoverlap
Non-uniform vertical electrical field in gate oxide along channel because Potential across channel varies from VGS @ S to VGS – VTH at pinch-off point
CGS = 2WLeffCox/3 + Wcoverlap
CGB neglected in triode & saturation because inversion layer acts as shield btwn G and bulk. Charge supplied by S and D rather than bulk for a change in VG
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MOS Small Signal Models
Channel length modulation modeled as VDS
Channel length modulation modeled as a resistor
Body effect modeled as gmVBS
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Models explained…
Channel Length Modulation ID varies with VDS -> modeled by a voltage-
dependent current source Note: I linearly varies with V -> linear resistor
ro affects circuit’s performanceLimits amplifier gain, affect output impedance, etc.
DTHGS
oxnDSDD
DSo
IVVL
WCVII
Vr
1
)(2
1
/
1
2
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Bulk Transconductance, gmb
Bulk potential affects VTH hence gate-source overdrive
When all other terminals held constant ID = f(VB) -> bulk behaves like a second gate
Modeled as a dependent current-source -> gmVBS
gmb IDVBS
nCox
2
W
L(VGS VTH)
VTH
VBS
gmb gm
2 2F VSBgm
Also,
VTH
VBS VTH
VSB
2
(2F VSB) 1/ 2
saturation
F = work function of polysilicon gate – work function of silicon substrateF = (kT/q)[ln(Nsub/ni)]
32
Gate Resistance
Need to consider resistivity
as well Each terminal exhibits finite ohmic resistance How to minimize the resistance?
Folded structure?Reduces RG by 4X
33
MOS Small Signal Model with Capacitance
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C-V of NMOS
Capacitor on chip very expensive Transistor capacitive (monolithic)
NMOS: S,D, and bulk GND-ed VG inversion layer forms from VGS VTH
For VG –ve Holes in substrate atrracted to oxide interface
• NMOS in “accummulation region” Device viewed as Cox (gate plate and substrate plate, tox separation)
As VGS density of holes @ interface falls Depletion region starts to form, device enters weak inversion C = Cox and Cdepln
For VGS > VTH
Channel formed. Capacitance = Cox