1 advanced challenges with real time systems
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Microcontrollers, Advanced
Advanced Challenges With Real-Time Systems
January 30, 2012
Jack Ganssle
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Design for Speed
Keep ISRs Short!
Avoid loopsRemove all unneeded code
Understand the cost of a LOC
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8051 186
u sec /M Hz u sec /M Hz
int = 36 12
int + 90 8
int - 120 8
int * 462 20int / 1344 40
int for 132 44
long = 624 64
long + 540 32
long - 546 32
long * 1128 1068long / 4878 3420
long for 642 44
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8051 8051 186 186
M in M ax M in M ax
usec /MHz usec /MHz usec /MHz usec /MHz
acos 3690 52632 5232 5238
asin 4950 53550 5232 5238atan 12300 26214 48096 102388
cos 4944 23748 69644 82092
sin 5406 23616 38696 79444
exp 2844 35046 6832 189240
sqrt 13800 15990 58644 59396
tan 7878 35820 120428 179028
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8051 8051 186 186
M in M ax M in M ax
usec /MHz usec /MHz usec /MHz usec /MHz
cos 4944 23748 69644 82092
Hart cos 7.3 digits 6660 6744 4160 4216
Hart cos 5.2 digits 5586 5670 3180 3236
Hart cos 3.2 digits 4548 4632 2204 2260
Hart 7.3 digit cos(x):
a=.9999999523 - .4999990534 * b**2 + .04166358 * b**4
- .001385370 * b**6 + .000023233 * b**8
Computer Approximations, by John Hart
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A Commercial Product
Micro Digitals GoFast: www.smxrtos.com
For NIOS-II processor at 24 MHz, times in microseconds:
double precision single precisionGoFast GCC GoFast GCC
cos 16.0 120.9 4.0 38.4
acos 32.2 201.5 9.6 59.6
pow 43.5 542.0 10.6 163.6
Note GoFast is fully reentrant.
http://www.smxrtos.com/http://www.smxrtos.com/ -
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Reentrancy Problems
A function is reentrant if:
If it uses all shared variables in an atomic way,
If it does not call non-reentrant functions
If it does not use the hardware in a non-atomic
way
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Shared Variable Perils
Using statics or globals non-atomically
makes the code non-reentrant.
void function(int *data){
count=data*2;data=count;
}
int count;
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Shared Variable Perils
Using statics or globals non-atomically
makes the code non-reentrant.
void function(int *data){
count=data*2;data=count;
}
int count;static
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Shared Variable Perils
Atomic operations may not be
atomic.
int data;void function(){
++data;}
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Shared Variable Perils
mov cx,[bx]add cx,1
mov [bx],cx
Atomic alternative:
inc [bx]lock
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The Danger of DI
long i;void do_something(void){disable_interrupts();
i+=0x1234;enable_interrupts();}
long i;void do_something(void){int key;key=disable_interrupts();
i+=0x1234;restore_interrupts(key);
}
NO!
Better
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Using a Handshake Flag
while (in_use); //wait till resource freein_use=TRUE; //set resource busyDo non-reentrant stuffin_use=FALSE; //set resource available
Bad Code! An interrupt between the first two statements may
cause two sections of code to think they both have exclusiveaccess to the shared resource.
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TSET Substitute
loop: mov al,0 ; 0 means in uselock xchg al,variablecmp al,0
je loop ; loop if in useIf al=0, we swapped 0 with zero; nothing changed
but the code loops since someone else is using the resource.
If al=1, we put a 0 into the in use variable,
marking the resource as busy. We fall out of the loop, nowhaving control of the resource.
On some ARM processors, use LDREX/STREX
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Calling non-reentrant Routines
Calling a non-reentrant function makes the
caller non-reentrant.
Be wary of runtime packages, and purchased
code.
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Non-atomic Hardware Accesses
If you cant manage a hardware resource
atomically, then the code is non-reentrant.
/* swap peripheral modes*/peripheral_reg_1=0xaa;
peripheral_reg_2=0x55;peripheral_reg_2=0x22;
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Async Hardware/Software
High 16 bits Low 16 bits
ISR
Hardware timer registerVariabletimer_hi
Overflow of timer register++timer_hi
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Async Hardware/Software
int timer_hi;interrupt timer(){++timer_hi;
}
long timer_read(void){unsigned int low, high;
low =inword(hardware_register);high=timer_hi;return (((ulong)high
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Async Hardware/Software
long timer_read(void){unsigned int low, high;
(hardware_register=ffff, timer_hi=0000)low =inword(hardware_register);(overflow; low=ffff, timer_hi=0001)
high=timer_hi;return (((ulong)high
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long timer_read(void)
{unsigned int low, high;
push_interrupt_state;disable_interrupts;
low=inword(hardware_register);high=timer_hi;if(timer_overflow){++high;low=inword(hardware_register);}
pop_interrupt_state;return (((ulong)high)
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Input Capture Register
Register To CPU
Bits 0-15
Bits 16-31
Data hold
Metastable design! Will surely fail
32 bit
counter
clock
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Speed Kills
Required reading:High Speed Digital Design
(a Handbook of Black Magic)by Howard
Johnson and Martin Graham (1993 PTR
Prentice Hall, NJ)
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Speed is a function of the edges, not clock rate.
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Bouncing in a 10 Inch wire
TP1 - driving
signal
TP2 - after
10 of wire
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Now Terminated
TP4
TP3
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The Tek TPP1000 Probe
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Common Impedance Problems
ALE
Edge sensitive interrupts (e.g., NMI)
All signals going off-board
Clock - particular problem as it goes all over
the typical board. Few CPUs accept TTL clock
signals; many wont tolerate anything less thana perfect clock.
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Resources
An Embedded Software Primerby David E. Simon
1999, Addison Wesley Longman
ISBN 0-201-61569-X
MicroC/OS-IIby Jean J. LaBrosse
1999, Miller Freeman
ISBN 0-87930-543-6
http://embedded.com/design/205203908 - Great multicore article
MicroC/OS-IIIby Jean J. LaBrosse - MicroC/OS-III
http://www.ecoscentric.com - ecos
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Questions?