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2008 Litho ITRS Update

Lithography iTWG

December 2008

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Outline

• Lithography Potential Solutions

• Multiple Targets and Solutions

• Double Exposure Challenges

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ITRS Working Group

• United States– Greg Hughes and Michael Lercel (Chairs)

• Japan– Iwao Higashikawa (Chair)

• Europe– Mauro Vasconi (Chair)

• Taiwan• Korea

– Cho (Chair)

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Preferred Technology by Year2008 SEMATECH Litho Forum survey results

45nm HP 32nm HP 22nm HP

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Potential Solutions 2008 - 2009DRAM 1/2 Pitch

Development Underway Qualification/Pre-Production Continuous ImprovementResearch Required

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.

65nm

20072008 2009

45nm

20102011 2012

32nm

20132014 2015

22nm

20162017 2018

16nm

20192020 2021

11nm

2022

DRAM Half-pitch

Flash Half-pitch

193 nm immersion with water193 nm immersion double patterning

Narrowoptions45

193 nm immersion double patterningEUV193 nm immersion with other fluids and lens materialsML2, Imprint

32Narrowoptions

EUVInnovative 193 nm immersionML2, imprint, innovative technology

Narrowoptions

22

Innovative technologyInnovative EUV, ML2, imprint, Directed Self Assembly

Narrowoptions

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193 nm193 nm immersion with water

65

193 nm Immersion with H2O193 Immersion double patterning

193 nm Immersion Double PatternEUV (DRAM) Immersion other fluidsML2, Imprint

EUV193 nm Immersion Double PatternML2, Imprint

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Looking at 16nm Half Pitch

2008 SEMATECH Litho Forum survey results

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2008 SEMATECH Litho Forum survey results

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MPU Printed Gate Length Change

0

10

20

30

40

50

60

70

2006 2008 2010 2012 2014 2016 2018 2020

MPU/ASIC Metal 1 (M1) ½ Pitch

DRAM ½ Pitch (nm) (contacted)

Flash ½ Pitch (un-contacted Poly)

MPU Printed Gate Length

WAS MPU Printed Gate Length

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2007 Format

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2008 Lithography Technology Requirements DRAM

FLASH

MPU

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MPU DetailsTable LITH3a&b Lithography Technology Requirements—Near-term YearsYear of Production 2008 2009 2010 2013 2014 2015

IS MPU/ASIC Metal 1 (M1) ½ pitch (nm) 59 52 45 32 28 25

WAS MPU gate in resist (nm) 38 34 30 21 19 17

IS MPU gate in resist (nm) 47 41 35 25 22 20

WAS MPU physical gate length (nm) * 23 20 18 13 11 10

IS MPU physical gate length (nm) * 29 27 24 18 17 15.3

IS Gate CD control (3 sigma) (nm) [B] ** 3.0 2.8 2.5 1.9 1.7 1.6

IS Contact in resist (nm) 73 64 56 39 35 31

IS Contact after etch (nm) 67 58 51 36 32 28

IS Overlay [A] (3 sigma) (nm) 15 13 11 8.0 7.1 6.3

NA required for logic (single exposure) 1.04 1.20 1.38 1.94

NA required for double exposure (logic) 0.72 0.82 0.95 1.34 1.50 1.68

MPU

Restricted Definition of CD - one direction, single pitch,

single iso dense ratio.

Restricted Definition to Single Litho Tool

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• Simple shot-noise model predicts 1/dose relationship between LER and dose

Data courtesy of Dr. P. Naulleau (LBNL) and Dr. T. Wallow (AMD)

0

2

4

6

8

10

12

14

0 10 20 30 40

Dose (mJ/cm2)

LER

(nm

, 3 s

igm

a)

ITRS Dose vs LER

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Resist TableTable LITH4AB Resist Requirements

Year of Production 2007 2008 2009 2010 2013

DRAM ½ pitch (nm) (contacted) 68 59 52 45 32

Resist Characteristics *

Resist meets requirements for gate resolution and gate CD control (nm, 3 sigma) **† 3.3 3.0 2.8 2.5 1.9

Resist thickness (nm, single layer) *** 105-190 85-160 80-145 70-130 50-90

PEB temperature sensitivity (nm/C) 1.75 1.5 1.5 1.5  1 

Backside particle density (particles/cm2

) 0.28 0.28 0.28 0.28 0.28

Back surface particle diameter: lithography and measurement tools (nm) 120 120 100 100 75

Defects in spin-coated resist films (#/cm2

) † 0.01 0.01 0.01 0.01 0.01

Minimum defect size in spin-coated resist films (nm) 40 35 30 30 20Defects in patterned resist films, gates, contacts, etc.

(#/cm2

) 0.04 0.03 0.03 0.03 0.02

Minimum defect size in patterned resist (nm) 40 35 30 30 20Low frequency line width roughness: (nm, 3 sigma) <8% of CD ***** 4.3 3.7 3.2 2.8 2.0

Correlation Length 40.8 33.8 29.2 25.8 19.6

Defects in spin-coated resist films for double patterning (#/cm2) 0.005 0.005 0.005 0.005 0.005

Backside particle density for double patterning (#/cm2) 0.14 0.14 0.14 0.14 0.14

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Double Patterning Challenge

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Double Exposure• Simple double exposure: each feature is exposed

independently (2006 ITRS)– Mask Image Placement tightens 70%– Mask Mean to target has to be matched for the two masks

MTT/2• 2007 ITRS- Define Double spaces (Independent Images)

– Adds wafer etch bias uniformity and repeatability.• Define Double Lines (Dependent Images)

– Mask Image Placement tightens– Mask CD 3 sigma tightens

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2008 Update Mask Requirements (DE/DP)

Optical Mask Requirements 2007 2010 201365 45 32

Image Placement (Single Exposure) 8.2 5.4 3.8 1 node

Image Placement (Double Exposure) (Independent)5.8 3.8 2.7Image Placement (DE) ( Lines Dependent) 2.4 1.6 1.1 4 nodes

Mean to Target (MTT) 5.5 3.6 2.5Difference in CD MTT for DE 2.7 1.8 1.3 2 nodes

CD Uniformity (nm, 3 Sigma) Isolated Lines 3.3 1.8 1.4CD Uniformity (nm, 3 Sigma) Dense Lines 5.2 3.4 2.4DE - Dual Line Mask CD (nm, 3 Sigma) 2.4 1.6 1.1 2 nodes

Note these are issues with LELE, LLENot the spacer Technology

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Summary• Lithography potential solutions are being narrowed for 45nm

DRAM half-pitch– CoO is Driving 193 Immersion Single Exposure– 2009 update will be major decision point for 32nm DRAM half-pitch

(Double Patterning or EUV)• LER and CD Control Still remain as a Dominant Issue • Relief on some near term specifications but imaging challenges

remain– Flash pushing Half Pitch and Double Patterning

• Overlay requirements for the Dependent Geometry will remain the challenge

– Contact Imaging Remains a challenge for all device types• Double exposure / patterning requires a complex set of

parameters when different exposures are used to define single features