1 2 3 4 5 6 7 8 9 10class.ece.iastate.edu/ee330/lectures/ee 330 lect 16...arbaaz khan chengrui yang...

1 2 6 73 4 5 98 10

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3

4

1

2

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11John

Heiling David Orona

Scott Melvin

Peter Bonnie

Michael Miller

Benjamin Meis

Patrick Schmidt

Yeap Yeoh

Andrew Snawerdt

Arisa Tajima

Samuel Jones

Christian Hurst

Kyle Perkins

Brian Anderson

Korbin Stich

Ashlyn Freestone

Nathaniel Byrne

Caleb Redman

Dalton Strauser

Joseph Freeland

Adam Cha

Brendan Bartels

Braden Rosengren

Benjamin Wiggins

Jongik Lee

Garrett Lassek

Aaron Haywood

James Tran

Richard Jiles

Adam Dau

Mitchell Wheaton

55

Mehdy Faik

Samuel Christy

Robert Buckley

Kurt Turner

Arbaaz Khan

Chengrui Yang

Kebei Wang

Lyle Bishop

Logan Boas

Xinian Bo

Liuchang Li

Mukund Choudhary

Yulin Song

Jiangning Xiong

EE 330 Spring 2016 Seating

EE 330

Lecture 16

MOSFET Modeling

CMOS Process Flow

Basic Devices and Device Models

• Resistor

• Diode

• Capacitor

• MOSFET

• BJT

Review from Last Lecture

Model Extension Summary

1

GS T

DS

D OX GS T DS GS DS GS T

2

OX GS T DS GS T DS GS T

0 V V

VWI μC V V V V V V V V

L 2

WμC V V V V V V V V

2L

T

BST0T VVV

Model Parameters : {μ,COX,VT0,φ,γ,λ}

Design Parameters : {W,L} but only one degree of freedom W/L

0I

0I

B

G


Operation Regions by Applications

0

50

100

150

200

250

300

0 1 2 3 4 5

Id

Vds

Saturation

Region

Triode

Region

Cutoff

Region

Analog

Circuits

Digital

Circuits

DI

DSV

Most analog circuits operate in the saturation region

(basic VVR operates in triode and is an exception)

Most digital circuits operate in triode and cutoff regions and switch

between these two with Boolean inputs


How many models of the MOSFET do we have?

Switch-level model (2)

Square-law model (with λ and bulk additions)

α-law model (with λ and bulk additions)

BSIM model

Square-law model

BSIM model (with binning extensions)

BSIM model (with binning extensions and process corners)


ID

VDS

VGS1

VGS2

VGS3

Actual

Modeled with one model

Local Agreement

with Any Model

(and W/L variations or

Process Variations)


Process Variations)


Process Variations)


Process Variations)

The Modeling Challenge

VDS

VBS = 0

VGS

ID

IG

IB

D 1 GS DS

G 2 GS DS

B 3 GS DS

I = f V ,V

I = f V ,V

I = f V ,V

Difficult to obtain analytical functions that

accurately fit actual devices over bias, size, and

process variations


Model Status

Simple dc Model

Small

Signal

Frequency

Dependent Small

Signal

Better Analytical

dc Model

Sophisticated Model

for Computer

Simulations

Simpler dc Model

Square-Law Model

Square-Law Model (with extensions for λ,γ effects)

Short-Channel α-law Model

BSIM Model

Switch-Level Models

• Ideal switches

• RSW and CGS

In the next few slides, the models we have

developed will be listed and reviewed

• Square-law Model

• Switch-level Models

• Extended Square-law model

• Short-channel model

• BSIM Model

• BSIM Binning Model

• Corner Models

Square-Law Model

ID

VDS

GS T

DS


2

OX GS T GS T DS GS T

0 V V


L 2

WμC V V V V V V V

2L

T

VGS1

VGS3

VGS2

VGS4

Model Parameters : {μ,COX,VT0}


VGS

RSW

CGS

S

DG

Switch-Level Models

Switch-level model including gate capacitance and drain resistance

Switch closed for VGS=“1”

CGS and RSW dependent upon device sizes and process

For minimum-sized devices in a 0.5u process

1.5fFCGS

channelp6KΩ

channeln2KΩRsw

Considerable emphasis will be placed upon device sizing to manage CGS and RSW

Drain

Gate

Source

Model Parameters : {CGS,RSW}

Extended Square-Law Model

1

GS T

DS


2

OX GS T DS GS T DS GS T

0 V V


L 2

WμC V V V V V V V V

2L

T

BST0T VVV

Model Parameters : {μ,COX,VT0,φ,γ,λ}


0I

0I

B

G

Short-Channel Model

1

1

GS T

2 2 2

D OX GS T DS GS DS GS

1

2

2 OX GS T GS T DS GS

0 V V

WI μC V V V V V V V

L

WμC V V V V V V

L

T T

T

V

V

α is the velocity saturation index, 2 ≥ α ≥ 1

Channel length modulation (λ) and bulk effects can be added to the velocity

Saturation as well

BSIM model

Note this model has 95 model parameters !

BSIM Binning Model - multiple BSIM models !

With 32 bins, this model has 3040 model parameters !

- Bin on device sizes

BSIM Corner Models

- five different BSIM models !

With 4 corners, this model has 475 model parameters !

- Often 4 corners in addition to nominal TT, FF, FS, SF, and SS

TT: typical-typical

FF: fast n, fast p

FS: fast n, slow p

SF: slow n, fast p

SS: slow n, slow p

W

L

Accuracy

Complexity

Switch-Level

Models

Number of Model

Parameters

0 to 2

Square-Law

Models

Number of Model

Parameters 3 to 6

BSIM

Models

Number of Model

ParametersApprox 100

BSIM Binning

Models

Number of Model

Parameters

Approx 3000

(for 30 bins)

An

aly

tica

lN

um

erica

l (f

or

sim

ula

tio

n o

nly

)

Hierarchical Model Comparisons

TT

Typical-Typical

SS

(Slow n, Slow p)

SF

(Slow n, Fast p)

FS

(Fast n, Slow p)

FF

(Fast n, Fast p)

Basic Model

Corner Model

Corner Models

Applicable at any level in model hierarchy (same model, different parameters)

Often 4 corners (FF, FS, SF, SS) used but sometimes many more

Designers must provide enough robustness so good yield at all corners

n-channel …. p-channel modeling

GS Tn

DS

D n OX GS Tn DS GS DS GS Tn

2

n OX GS Tn GS Tn DS GS Tn

G B

0 V V

VWI μ C V V V V V V V V

L 2

Wμ C V V V V V V V

2L

I =I =0

Tn

0

0.5

1

1.5

2

2.5

3

0 1 2 3 4 5

VDS

ID

VGS1

VGS2

VGS4

VGS3

GS4 GS3 GS2 GS1V V V V > 0

VDS

D

BG

S

VDS

VGSVBS

ID

IG IB

D D

S S

G G

D

BG

S

Gate DrainSource

Bulk

n-channel MOSFET

Positive VDS and VGS cause a positive ID

(for enhancement devices)


D D

S S

G G

D

BG

S

D

BG

S

VDS

VGS

VBS

ID

IG IB

GS Tp

DS

D p OX GS Tp DS GS Tp DS GS Tp

2

p OX GS Tp GS Tp DS GS Tp

G B

0 V V

VWI -μ C V V V V V V V V

L 2

W-μ C V V V V V V V

2L

I =I =0

Gate DrainSource

Bulk

p-channel MOSFET

Negative VDS and VGS cause a negative ID


Functional form of models are the same, just sign differences and some

parameter differences (usually mobility is the most important)


D

BG

S

VDS

VGS

VBS

ID

IG IB

GS Tp

DS


2


G B

0 V V


L 2


2L

I =I =0

Gate DrainSource

Bulk

p-channel MOSFET


GS Tp

DS


2


G B

0 V V


L 2

Wμ C V V V V V V V

2L

I =I =0

Alternate equivalent representation

These look like those for the n-channel device but with ||

D D

S S

G G

D

BG

S

D

BG

S

VDS

VGSVBS

ID

IG IB

0

0.5

1

1.5

2

2.5

3

0 1 2 3 4 5

VDS

ID

VGS1

VGS2

VGS4

VGS3

GS4 GS3 GS2 GS1V V V V > 0

VDS

GS Tn

DS

D n OX GS Tn DS GS DS GS Tn

2

n OX GS Tn GS Tn DS GS Tn

G B

0 V V


L 2

Wμ C V V V V V V V

2L

I =I =0

Tn

D D

S S

G G

D

BG

S

D

BG

S

VDS

VGS

VBS

ID

IG IB

GS Tp

DS


2


G B

0 V V


L 2


2L

I =I =0


Models essentially the

same with different signs

and model parameters

Model Relationships

Determine RSW and CGS for an n-channel MOSFET from square-law model

In the 0.5u CMOS process if L=1u, W=1u

(Assume μCOX=100μAV-2, COX=2.5fFu-2,VT0=1V, VDD=3.5V, VSS=0)

GS T

DS


2


0 V V


L 2

WμC V V V V V V V

2L

T

when SW is on, operation is “deep” triode

Model Relationships

(Assume μCOX=100μAV-2, COX=2.5fFu-2,VT0=1V, VDD=3.5V, VSS=0)

DS

D OX GS T DS OX GS T DS

VW WI μC V V V μC V V V

L 2 L

14

14 3 5 1

1

K

E

GS DD

GS

DS

SQ

D V =VOX GS T

V =3.5V

V 1R =

WIμC V V ( ) .

L

CGS= COXWL = (2.5fFµ-2)(1µ2) = 2.5fF

Determine RSW and CGS for an n-channel MOSFET from square-law model


Model Relationships

( COX=2.5fFu-2,VT0=1V, VDD=3.5V, VSS=0)

GS T

DS


2


0 V V


L 2

WμC V V V V V V V

2L

T

When SW is on, operation is “deep” triode

Determine RSW and CGS for an p-channel MOSFET from square-law model


Observe µn\ µp≈3

Model Relationships

DS

D p OX GS T DS p OX GS T DS

VW WI μ C V V V μC V V V

L 2 L

112

1 14 3 5 1

3 1

K

E

GS DD

GS

DS

SQ

D V =Vp OX GS T

V =3.5V

V 1R =

WIμ C V V ( ) .

L

CGS= COXWL = (2.5fFµ-2)(1µ2) = 2.5fF

Determine RSW and CGS for an p-channel MOSFET from square-law model


( COX=2.5fFu-2,VT0=1V, VDD=3.5V, VSS=0)

Observe µn\ µp≈3

Observe the resistance of the p-channel device is approximately 3 times

larger than that of the n-channel device for same bias and dimensions !

Modeling of the MOSFET

Drain

Gate Bulk

ID

ID IB

VDS

VBS

VGS

Goal: Obtain a mathematical relationship between the

port variables of a device.

Simple dc Model

Small

Signal

Frequency

Dependent Small

Signal

Better Analytical

dc Model

Sophisticated Model

for Computer

Simulations

Simpler dc Model

BSDSGS3B

BSDSGS2G

BSDSGS1D

V,,VVfI

V,,VVfI

V,,VVfI

Small-Signal Model

Goal with small signal model is to predict

performance of circuit or device in the

vicinity of an operating point

Operating point is often termed Q-point

Small-Signal Modely

x

Q-point

XQ

YQ

Analytical expressions for small signal model will be developed later

Technology Files

• Design Rules

• Process Flow (Fabrication Technology)

• Model Parameters

n-well

n-well

n-

p-

Bulk CMOS Process Description• n-well process

• Single Metal Only Depicted

• Double Poly

− This type of process dominates what is used for high-volume “low-

cost” processing of integrated circuits today

− Many process variants and specialized processes are used for lower-

volume or niche applications

− Emphasis in this course will be on the electronics associated with the

design of integrated electronic circuits in processes targeting high-

volume low-cost products where competition based upon price

differentiation may be acute

− Basic electronics concepts, however, are applicable for lower-volume

or niche applicaitons

Components Shown

• n-channel MOSFET

• p-channel MOSFET

• Poly Resistor

• Doubly Poly Capacitor

A A’

B’B

C

C’

D

D’

Consider Basic Components

Only

Well Contacts and Guard Rings Will be

Discussed Later

A A’

B’B

A A’

B’B

n-channel MOSFET

S

D

G

S

D

BG

Metal details hidden to reduce clutter

A A’

B’B

S

D

BG

W L

A A’

B’B

n-channel MOSFET

Capacitor

p-channel MOSFET

Resistor

n-well

n-well

n-

p-

A A’

B’B

N-well Mask

Detailed Description of First

Photolithographic Steps Only

• Top View

• Cross-Section View

~

Blank Wafer

p-doped Substrate

ExposeDevelop

Photoresistn-well Mask

Implant

A A’

B’B

Will use positive photoresist(exposed region soluble in developer)

A-A’ Section

B-B’ Section

PhotoresistN-well MaskExposureDevelop

A-A’ Section

B-B’ Section

Implant

N-well Mask

A-A’ Section

B-B’ Sectionn-well

n-well

n-well

n-

p-

A A’

B’B

Active Mask

Active Mask

A-A’ Section

B-B’ Section

Field Oxide Field Oxide Field Oxide

Field Oxide

n-well

n-well

n-

p-

A A’

B’B

Poly1 Mask

A A’

B’B

n-channel MOSFET

Capacitor

P-channel MOSFET

Resistor

Poly plays a key role in all four types of devices !

Poly 1 Mask

A-A’ Section

B-B’ Section

Gate Oxide Gate Oxide

n-well

n-well

n-

p-

A A’

B’B

Poly 2 Mask

Poly 2 Mask

A-A’ Section

B-B’ Section

n-well

n-well

n-

p-

A A’

B’B

P-Select

P-Select Mask – p-diffusion

A-A’ Section

B-B’ Section

p-diffusion

Note the gate is self aligned !!

n-Select Mask – n-diffusion

A-A’ Section

B-B’ Section

n-diffusion

n-well

n-well

n-

p-

A A’

B’B

Contact Mask

Contact Mask

A-A’ Section

B-B’ Section

n-well

n-well

n-

p-

A A’

B’B

Metal 1 Mask

Metal Mask

A-A’ Section

B-B’ Section

A A’

B’B

A A’

B’B

n-channel MOSFET

Capacitor

P-channel MOSFET

Resistor

How does the inverter delay compare between a 0.5u

process and a 0.13u process?

VIN VOUT

VDD

VSS

VIN VOUT

How does the inverter delay compare between a 0.5u process and a 0.13u process?

VIN

VOUT

Assume n-channel and p-channel devices are minimum sized

5.0 1.25

tHL=RpdCL

tLH=RpdCL

n

pd

n OX n DD TN

LR

C W V V

p

pu

p OX p DD TP

LR

C W V V

L OX n n p pC C W L W L

0.5u 0.13u

CL 1.25E-15 3.549E-16

Rpd 2217 4128

Rpu 6098 23529

THL 2.77E-12 1.47E-12

TLH 7.62E-12 8.35E-12 Rpu for the p-ch 0.13 is in question

End of Lecture 16

1 2 3 4 5 6 7 8 9 10class.ece.iastate.edu/ee330/lectures/ee 330 lect 16...arbaaz khan chengrui yang...

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