JMR 30-Nov-00HANDBOOK OFVLSI MICROLITHOGRAPHYSECOND EDITIONPrinciples, Technology, and ApplicationsJMR- 30-Nov-00JMR 30-Nov-00HANDBOOK OFVLSI MICROLITHOGRAPHYSECOND EDITIONPrinciples, Technology, and ApplicationsEdited byJohn N. HelbertMotorola, Inc.Phoenix, ArizonaNOYES PUBLICATIONSPark Ridge, New Jersey, U.S.A.WILLIAM ANDREW PUBLISHING, LLCNorwich, New York, U.S.A.Copyright 2001 by Noyes PublicationsNo part of this book may be reproduced orutilized in any form or by any means, elec-tronic or mechanical, including photocopying,recording or by any information storage andretrieval system, without permission in writingfrom the Publisher.Library of Congress Catalog Card Number: 00-028173ISBN: 0-8155-1444-1Printed in the United StatesPublished in the United States of America byNoyes Publications / William Andrew Publishing, LLC13 Eaton AvenueNorwich, NY 138151-800-932-7045www.knovel.com10 9 8 7 6 5 4 3 2 1Library of Congress Cataloging-in-Publication DataHandbook of VLSI Microlithography / [edited] byJohn Helbert.--2nd editionp. cm.Includes bibliographical references and index.ISBN 0-8155-1444-11. Integrated circuits--Very large scale integration. 2. Microlithography.I. Helbert, John N.TK7874 .H3494 2001621. 3815' 31--dc21 00- 028173 CIPvMATERIALS SCIENCE AND PROCESS TECHNOLOGY SERIESSeries EditorsRointan F. Bunshah, University of California, Los AngelesGary E. McGuire, Microelectronics Center of North CarolinaStephen M. Rossnagel, IBM Thomas J. Watson Research CenterElectronic Materials and Process TechnologyCHARACTERIZATION OF SEMICONDUCTOR MATERIALS, Volume 1: edited by Gary E.McGuireCHEMICAL VAPOR DEPOSITION FOR MICROELECTRONICS: by Arthur ShermanCHEMICAL VAPOR DEPOSITION OF TUNGSTEN AND TUNGSTEN SILICIDES: by John E.J. SchmitzCHEMISTRY OF SUPERCONDUCTOR MATERIALS: edited by Terrell A. VanderahCONTACTS TO SEMICONDUCTORS: edited by Leonard J. BrillsonDIAMOND CHEMICAL VAPOR DEPOSITION: by Huimin Liu and David S. DandyDIAMOND FILMS AND COATINGS: edited by Robert F. DavisDIFFUSION PHENOMENA IN THIN FILMS AND MICROELECTRONIC MATERIALS: edited byDevendra Gupta and Paul S. HoELECTROCHEMISTRY OF SEMICONDUCTORS AND ELECTRONICS: edited by JohnMcHardy and Frank LudwigELECTRODEPOSITION: by Jack W. DiniHANDBOOK OF CARBON, GRAPHITE, DIAMONDS AND FULLERENES: by Hugh O.PiersonHANDBOOK OF CHEMICAL VAPOR DEPOSITION, Second Edition: by Hugh O. PiersonHANDBOOK OF COMPOUND SEMICONDUCTORS: edited by Paul H. Holloway and GaryE. McGuireHANDBOOK OF CONTAMINATION CONTROL IN MICROELECTRONICS: edited by DonaldL. TolliverHANDBOOK OF DEPOSITION TECHNOLOGIES FOR FILMS AND COATINGS, SecondEdition: edited by Rointan F. BunshahHANDBOOK OF ION BEAM PROCESSING TECHNOLOGY: edited by Jerome J. Cuomo,Stephen M. Rossnagel, and Harold R. KaufmanHANDBOOK OF MAGNETO-OPTICAL DATA RECORDING: edited by Terry McDaniel andRandall H. VictoraHANDBOOK OF MULTILEVEL METALLIZATION FOR INTEGRATED CIRCUITS: edited bySyd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr.HANDBOOK OF PLASMA PROCESSING TECHNOLOGY: edited by Stephen M. Rossnagel,Jerome J. Cuomo, and William D. WestwoodHANDBOOK OF POLYMER COATINGS FOR ELECTRONICS, 2nd Edition: by James Licariand Laura A. HughesHANDBOOK OF REFRACTORY CARBIDES AND NITRIDES: by Hugh O. PiersonJMR- 30-Nov-00vi SeriesHANDBOOK OF SEMICONDUCTOR SILICON TECHNOLOGY: edited by William C. OMara,Robert B. Herring, and Lee P. HuntHANDBOOK OF SEMICONDUCTOR WAFER CLEANING TECHNOLOGY: edited by WernerKernHANDBOOK OF SPUTTER DEPOSITION TECHNOLOGY: by Kiyotaka Wasa and ShigeruHayakawaHANDBOOK OF THIN FILM DEPOSITION PROCESSES AND TECHNIQUES: edited by KlausK. SchuegrafHANDBOOK OF VACUUM ARC SCIENCE AND TECHNOLOGY: edited by Raymond L.Boxman, Philip J. Martin, and David M. SandersHANDBOOK OF VLSI MICROLITHOGRAPHY: edited by William B. Glendinning and JohnN. HelbertHIGH DENSITY PLASMA SOURCES: edited by Oleg A. PopovHYBRID MICROCIRCUIT TECHNOLOGY HANDBOOK, Second Edition: by James J. Licariand Leonard R. EnlowIONIZED-CLUSTER BEAM DEPOSITION AND EPITAXY: by Toshinori TakagiMOLECULAR BEAM EPITAXY: edited by Robin F. C. FarrowSEMICONDUCTOR MATERIALS AND PROCESS TECHNOLOGY HANDBOOK: edited byGary E. McGuireULTRA-FINE PARTICLES: edited by Chikara Hayashi, R. Ueda and A. TasakiCeramic and Other MaterialsProcessing and TechnologyADVANCED CERAMIC PROCESSING AND TECHNOLOGY, Volume 1: edited by Jon G. P.BinnerCEMENTED TUNGSTEN CARBIDES: by Gopal S. UpadhyayaCERAMIC CUTTING TOOLS: edited by E. Dow WhitneyCERAMIC FILMS AND COATINGS: edited by John B. Wachtman and Richard A. HaberCORROSION OF GLASS, CERAMICS AND CERAMIC SUPERCONDUCTORS: edited byDavid E. Clark and Bruce K. ZoitosFIBER REINFORCED CERAMIC COMPOSITES: edited by K. S. MazdiyasniFRICTION AND WEAR TRANSITIONS OF MATERIALS: by Peter J. BlauHANDBOOK OF CERAMIC GRINDING AND POLISHING: edited by Ioan D. Mavinescu, HansK. Tonshoff, and Ichiro InasakiHANDBOOK OF INDUSTRIAL REFRACTORIES TECHNOLOGY: by Stephen C. Carnigliaand Gordon L. BarnaSHOCK WAVES FOR INDUSTRIAL APPLICATIONS: edited by Lawrence E. MurrSOL-GEL TECHNOLOGY FOR THIN FILMS, FIBERS, PREFORMS, ELECTRONICS ANDSPECIALTY SHAPES: edited by Lisa C. KleinSOL-GEL SILICA: by Larry L. HenchSPECIAL MELTING AND PROCESSING TECHNOLOGIES: edited by G. K. BhatSUPERCRITICAL FLUID CLEANING: edited by John McHardy and Samuel P. SawanviiPrefaceThe chapter topics of this lithography handbook deal with the criticaland enabling aspects of the intriguing task of printing very high resolution,high density integrated circuit (IC) patterns into thin resist-process pattern-transfer coatings. Circuit pattern density or resolution drives DynamicRandom Access Memory (DRAM) technology, which is the principal circuitdensity driver for the entire Very Large Scale Integrated Circuit (VLSI)industry. This books main theme concerns the special printing processescreated by workers striving to achieve volume high density IC chipproduction. The current goal is pattern features sizes near 0.25 m for 64Mbit DRAM lithography and, ultimately, the production of devices withfeatures well below 0.1 m. The text is meant for a full spectrum of readersspanning university, industrial, and government research and developmentscientists, and production-minded engineers, technicians, and students.Specifically, we have attempted to consider the needs of lithography-oriented students and practicing industrial engineers and technicians.The leadoff chapter focuses on the view that lithography methods(printing patterns) are pursued for the singular purpose of manufacturing ICchips in the highly competitive commercial sector, and it attempts todelineate the factors determining lithographic tool selection. The reader isdrawn to consider IC device electrical performance criteria versus plausibleand alternative energetic, or circuit density limited, particle printing meth-odsvisible or shorter UV optical, electron, x-ray, and ion beams. Thecriteria for high quality micrometer and submicrometer lithography is verysimply defined by the three major patterning parameters: line/space resolu-tion, line edge, and pattern feature dimension control, which when combinedwith pattern-to-pattern alignment capability determine lithographic overlayJMR- 30-Nov-00viii Prefaceaccuracy. Patterning yield and throughput further enter as dependenteconomic factors.Resist and resist process equipment technology have a logical, promi-nent, second-chapter position indicative of resists overall importance inlithography, i.e., the end product of any IC lithography process is thepatterned-resist masking layer needed to delineate the VLSI circuit level.Example coverage of optical resist process optimization assures the readera grasp of the most commonly and widely used (worldwide) lithographicprocess and equipment technologies. The coauthors believe this chapter tobe the first comprehensive and practical work describing the relationshipbetween the resist process and the resist processing equipment parameters.The basic resist design concepts and definitions as well as advancedlithographic processes are thoroughly covered .Chapter 3 deals primarily with basic lithographic resist processdefectivity and the potential yield limiting effect on device production yields.It is also a fairly comprehensive summary of defectivity detection systemsused for basic lithographic process characterization, and device yieldenhancement efforts in general.Basic metrology considerations (Chapter 4) are absolutely imperativeto rendering a total description of lithography pattern transfer methodology.The task of precisely measuring printed linewidth or space artifacts atdimensions which are submicron and below is of paramount interest tolithographic technology. The elucidation of optical, scanning-electron-mi-croscope (SEM), and electrical test device linewidth measurements datapresents the reader with key boundary conditions essential for obtainingmeaningful linewidth characterization.The portrayal of energetic photon or particle microlithography is totallyincomplete without some detail of the actual printing tool concepts, design,construction, and performance. The printing tools and their usage in the ICmanufacturing world are presented and described in the later chapters,beginning with Chapter 5. Clearly, optical lithography has been the backboneand mainstay of the worlds microchip production activity and will most likelycontinue in this dominant role into the next century. In the optical arena, it isfound that 15X reduction printers, of the projection scanned and unscannedvariety, must be described in subsets according to coherent and non-coherent radiation, as well as by wavelengths ranging from visible to deepultraviolet (UV), then extending to angstrom levels. Higher resolution ormore energetic sourced tools are also well described.The goals of Chapters 6 and 8 were to provide the first source ofdocumented information on basic lithographic tool automation and vibra-tional analysis principles. Heretofore, these topics were always relegated toJMR 30-Nov-00Preface ixprivate communications and private notebooks of individual engineers ornon-lithographic journal sources. The editor thanks the authors of these twochapters for providing this important and incisive information.Next, in world manufacturing usage, electron beam (e-beam) patternprinting has been vital, mostly because of its application in a patterngeneration capacity for making photo masks and reticles, but also becauseof direct- write-on-wafer device photo usage. The writing strategy dividese-beam printers, in general, into three groups: Gaussian beam raster scan,principally for pattern generation, newer stenciled projection systems, andfixed or variable-shaped beam vector scan for direct-write-on-waferapplications. Subsets of the latter groups depend upon site-by-site versuswrite-on-the-fly substrate movements. The sophistication and complexity ofe-beam printers requires diverse expertise in many technical areas such aselectrostatic and electromagnetic beam deflection, high speed beam blank-ing, intense electron sources, precise beam shapers, and ultra fast data flowelectronics and storage. Interestingly, important special beam relationshipsof maximum current, density, and writing pattern path-speed require theobservance of unique boundary conditions in meeting printing criteria.On a worldwide basis, x-ray printing does not yet have high volume ICdevice production background examples, but high density prototype CMOSdevices have been fabricated by IBM, and their feasibility demonstrated.The x-ray chapter presents x-ray lithography as a system approach withsource, mask, aligner, and resist components. Of the competing volumemanufacturing printing methods (optical and x-ray), the x-ray process isunique as a proximity and 1:1 method. As such, in order to meet the ICpatterning quality criteria, extreme demands are placed on the maskfabrication process, much more so than for masks or reticles produced forthe optical analogue. For economically acceptable IC production, laser/diodeplasma and synchrotron ring x-ray sources must be presented as high densityphoton emitters. In the second part of Chapter 10, the synchrotron is givenspecial attention and is presented as a unique x-ray generator with an x-rayflux collimation feature. In spite of the synchrotrons massive size and verylarge cost, its multi-port throughput capacity makes it viable for the very highproduction needs of certain industrial IC houses or possibly for multi-company or shared-company situations.In the last of the charged particle printing tool chapters, Chapter 9, theenergetic ion is depicted in a controllable, steerable, particle-beam serial-pattern writer performing lithography at a high mass ratio compared to an e-beam writer. The focused ion beam not only can deposit energy to form ICpattern latent resist images, but offers, as another application, the directimplant of impurity ions into semiconductor wafers, obviating completely theJMR- 30-Nov-00x Prefaceneed for any resist whatsoever and greatly simplifying the IC chip processingsequence. The versatile energetic ion plays yet another and possibly its mostsignificant role in a steered beam tool, indispensable for optical and x-raymask repair through the precise localized ablation and/or deposition of maskabsorber material.One of the editors purposes in assembling this book has been toaccurately disseminate the results of many and varied microlithographyworkers. Since it is not possible in any one book to provide enough detail tosatisfy every readers full curiosity, weve attempted to enable him toperform his own valid analysis and make some meaningful conclusionsregarding the status and trends of the vital technical thrust areas ofsubmicron IC pattern printing technology.Many individuals representing industrial, government, and universitysectors have been extremely helpful in providing technical discussions, data,and figures to the chapter authors of this book. Gratitude is extended hereto those persons and their organizations. Gratitude is also expressed viacourtesy annotations in the figure captions. Finally, we commend and thankRoxie Helbert for her compilation and editing skills.March 21, 2000 John N. HelbertMesa, ArizonaxiContributorsPhillip BlaisWestinghouse Electric Corp. (Retired)Baltimore, MarylandFranco CerrinaUniversity of WisconsinMadison, WisconsinTony DaouMotorola, Inc.Chandler, ArizonaWilliam B. GlendinningConsultantSouth Bristol, MaineJohn N. HelbertMotorola, Inc.Mesa, ArizonaCharles T. LambsonASMLHong Kong, ChinaFourmun LeeMotorola, Inc.Chandler, ArizonaAllen LeporeArmy Research LaboratoryAdelphi, MarylandKenneth MedearisKenneth Medearis AssociatesFort Collins, ColoradoJohn MelngailisUniversity of MarylandCollege Park, MarylandMichael MichaelsWestinghouse Electric Corp.Baltimore, MarylandWhit WaldoMotorola, Inc.Austin, TexasArnold YanofMotorola, Inc.Chandler, ArizonaNOTICETo the best of our knowledge the information in this publication isaccurate; however the Publisher does not assume any responsibilityor liability for the accuracy or completeness of, or consequencesarising from, such information. This book is intended for informationalpurposes only. Mention of trade names or commercial products doesnot constitute endorsement or recommendation for use by the Publisher.Final determination of the suitability of any information or productfor use contemplated by any user, and the manner of that use, is thesole responsibility of the user. We recommend that anyone intendingto rely on any recommendation of materials or procedures mentionedin this publication should satisfy himself as to such suitability, andthat he can meet all applicable safety and health standards.Contents xiiixiiiContents1 Issues and Trends Affecting Lithography Tool SelectionStrategy .................................................................................... 1Phillip Blais, Michael Michaels, and John N. Helbert1.0 INTRODUCTION................................................................................. 11.1 Device Lithography Requirements:Advances and Predictions ......................................................... 31.2 Semiconductor World Fab Status .............................................. 81.3 Wavefront Engineering andReticle Fabrication Maskshop Issues ...................................... 102.0 STRATEGY ........................................................................................ 162.1 Charter ..................................................................................... 172.2 Marketing................................................................................. 202.3 Product Development .............................................................. 222.4 Production Facility................................................................... 242.5 Technical Capability ................................................................. 252.6 Types of Lithography .............................................................. 252.7 Economic Factors..................................................................... 573.0 IMPLEMENTATION OF STRATEGY ................................................ 634.0 SUMMARY ....................................................................................... 70REFERENCES ............................................................................................. 71xiv Handbook of VLSI Microlithography2 Resist TechnologyDesign, Processing,and Applications ..................................................................... 74John N. Helbert and Tony DaouPREFACE ................................................................................................. 741.0 INTRODUCTION TO PATTERN TRANSFER TECHNOLOGY.......... 752.0 RESIST DESIGN................................................................................. 772.1 Conventional Photoresists ...................................................... 772.2 Deep UV Resists ...................................................................... 962.3 Radiation Resists ................................................................... 1112.4 Future Resists ........................................................................ 1193.0 RESIST PROCESSING...................................................................... 1203.1 Resist Parameter Screening .................................................... 1203.2 Resist Adhesion Requirements.............................................. 1463.3 Resist Application ................................................................. 1613.4 Prebake/Exposure/Postbake/Development Processing.......... 1634.0 LITHOGRAPHIC PROCESSING EQUIPMENT ................................ 1874.1 Wafer Processes and Equipment (Wafer Tracks) ................... 1874.2 Resist and Develop Track Fab Qualification .......................... 2414.3 DUV Resist Wafer Tracks ...................................................... 2524.4 Photochemical Support to Modern Fabs ............................... 2565.0 APPLICATIONS AND SPECIAL PROCESSES ................................ 2595.1 Future Device Demands ......................................................... 2595.2 Introduction to Multilayer Applications ................................ 2605.3 Introduction to MLM Lithography ........................................ 2625.4 Applications .......................................................................... 2625.5 Summary and Future Predictions ........................................... 3135.6 Future Processes ................................................................... 313REFERENCES ........................................................................................... 3143 Lithography Process Monitoring and Defect Detection.... 327Fourmun Lee1.0 OVERVIEW...................................................................................... 3272.0 DEFECT DETECTION TOOLS......................................................... 3292.1 History ................................................................................... 3292.2 Inspection Equipment Requirements ..................................... 3312.3 Detection Techniques ............................................................ 3323.0 DATA ANALYSIS AND DEFECT CHARACTERIZATION ............ 352Contents xv4.0 PROCESS OPTIMIZATION AND QUALIFICATION...................... 3545.0 DEFECT REDUCTION..................................................................... 3566.0 CASE STUDIES ............................................................................... 3586.1 Center Stripe Defects ............................................................. 3586.2 Circle Defects ......................................................................... 3636.3 Repeater Defects .................................................................... 3676.4 New Process Optimization ..................................................... 369REFERENCES ........................................................................................... 3814 Techniques and Tools for Photo Metrology ....................... 382Arnold Yanof1.0 INTRODUCTION............................................................................. 3822.0 CD SCANNING ELECTRON MICROSCOPE (CD-SEM) .................. 3832.1 Basic CD-SEM Equipment and Measurement ........................ 3832.2 Characteristics and Limitations of Low Voltage SEMImaging and Metrology ......................................................... 3892.3 CD-SEM Measurement Validity ............................................. 4043.0 ELECTRICAL CD (ECD) METROLOGY........................................... 4143.1 Types of ECD Test Structures ................................................ 4153.2 Gauge Capability and Accuracy of ECD ................................ 4164.0 OVERLAY MEASUREMENT .......................................................... 4204.1 Basic Optical Overlay Measurement ...................................... 4204.2 Overlay Metrology Tool Performance.................................... 4214.3 Plotting Overlay Results ........................................................ 4264.4 Process-Related Overlay Measurement Errors ...................... 4275.0 FILM THICKNESS BY ELLIPSOMETRY AND REFLECTANCESPECTROMETRY ............................................................................ 4365.1 Optical Thin Film Phenomena ................................................ 4375.2 Light Polarization Basics for Ellipsometry .............................. 4385.3 Basic Ellipsometer .................................................................. 4395.4 Film Thickness Instrumentation for Semiconductor Use ....... 4405.5 Physics of Optical Film Thickness Measurement .................. 4426.0 STATISTICAL APPLICATIONS TO METROLOGY........................ 4536.1 Definitions of Accuracy, Precision,Reproducibility and Matching ............................................... 4536.2 Analysis of Variance for Metrology Gauge Studiesand Process Analysis ............................................................ 4546.3 Chi-Square Test for Variance Comparisons ............................ 462REFERENCES ........................................................................................... 466xvi Handbook of VLSI Microlithography5 Techniques and Tools for Optical Lithography .................. 472Whit Waldo1.0 INTRODUCTION............................................................................. 4722.0 FRAUNHOFER DIFFRACTION ...................................................... 4752.1 Diffraction Through a Rectangular Aperture ......................... 4762.2 Diffraction Through a Circular Aperture ................................ 4772.3 Airy Disk................................................................................ 4783.0 THEORETICAL RESOLUTION LIMIT ............................................ 4804.0 DIFFRACTION GRATINGS ............................................................. 4845.0 FOURIER SYNTHESIS..................................................................... 4876.0 ABBES THEORY OF IMAGE FORMATION .................................. 4897.0 INTRODUCTION TO TRANSFER FUNCTIONS ............................. 4917.1 Spread Functions ................................................................... 4927.2 Modulation ............................................................................ 4937.3 Modulation, Phase, and Optical Transfer Functions ............. 4947.4 Cascading Linear Functions .................................................. 4957.5 Illumination Degree of Coherence .......................................... 4967.6 Wavelength Effect on MTF ................................................... 5047.7 Depth of Focus ...................................................................... 5047.8 Diffraction Limited Resolution ............................................... 5077.9 Minimum MTF Requirement .................................................. 5087.10 Field Application of Transfer Functions ................................ 5098.0 DESIGN CONSIDERATIONS FOR IMAGING EFFECTS ................. 5108.1 Laser Interferometry ............................................................... 5128.2 Aberration Modeling ............................................................. 5168.3 Aerial Image Intensity Distribution........................................ 5238.4 Shaped Illumination Sources and Spatial Filtering................. 5289.0 NUMERICAL AND STATISTICAL METHODS.............................. 5349.1 Data Regression ..................................................................... 5349.2 F-Test and T-Test ................................................................... 5369.3 Multifactor Experiments ......................................................... 5389.4 Analysis of Experiments ........................................................ 5429.5 Process Control ...................................................................... 54210.0 PRACTICAL IMAGING QUALITY ................................................. 54710.1 Field Diameter and Resolution ............................................... 54710.2 Exposure-Defocus Diagrams .................................................. 54810.3 Depth Of Focus Issues .......................................................... 55210.4 Illumination ............................................................................ 56210.5 Thin Film Interference and Standing Waves .......................... 57110.6 Vibration................................................................................. 579Contents xvii10.7 Miscellaneous Processing Issues .......................................... 58010.8 Industrially Accepted Designs .............................................. 58111.0 PRACTICAL IMAGE PLACEMENT ............................................... 58211.1 Alignment .............................................................................. 58211.2 Field Errors ............................................................................. 59212.0 MASK ISSUES ................................................................................ 60112.1 Particulate Protection ............................................................. 60112.2 Phase Shifting Masks ............................................................ 60412.3 Serifs ...................................................................................... 62812.4 Excimer Laser Irradiation Damage .......................................... 62812.5 Registration Error Contributions ............................................ 629REFERENCES ........................................................................................... 6306 Microlithography Tool Automation .................................... 644Charles T. Lambson1.0 AUTOMATION BASICS................................................................. 6441.1 Introduction ........................................................................... 6441.2 Automation Is a Gradual Process........................................... 6451.3 Cluster Tools .......................................................................... 6452.0 CELL CONTROLLERS ..................................................................... 6462.1 Motivation for Cell Controllers .............................................. 6462.2 Work Cells .............................................................................. 6472.3 Model Cell Controller ............................................................. 6472.4 Cell Controller Benefits .......................................................... 6503.0 EQUIPMENT COMMUNICATION INTERFACES .......................... 6513.1 SECS-I Protocol ...................................................................... 6513.2 The SECS-II Standard ............................................................ 6523.3 The GEM Standard ................................................................ 6533.4 The SEM Standards ............................................................... 6554.0 STATE MODELS ............................................................................. 6555.0 LADDER DIAGRAMS..................................................................... 6626.0 MATERIAL TRANSPORT............................................................... 6636.1 Fab Layout Considerations for AutomatedMaterial Transport ................................................................. 6646.2 Interface Considerations for Automated Material Transport . 6656.3 CIM (Computer Integrated Manufacturing)Architecture Considerations .................................................. 668REFERENCES ........................................................................................... 669xviii Handbook of VLSI Microlithography7 Electron-Beam ULSI Applications ...................................... 670Allen Lepore1.0 INTRODUCTION............................................................................. 6702.0 THE LITHOGRAPHY PROCESS ...................................................... 6732.1 Logistics of Exposure............................................................. 6732.2 Physics of Exposures ............................................................. 6762.3 Lithography Process Issues and Parameters ......................... 6863.0 ELECTRON-BEAM LITHOGRAPHY EQUIPMENT ........................ 6983.1 Introduction ........................................................................... 6983.2 Electron-Optical System......................................................... 7003.3 Writing Strategies and Architecture ...................................... 7093.4 Calibrations ............................................................................ 7143.5 Examples of Commercial Equipment ....................................... 7153.6 Novel Electron-Beam Technologies ....................................... 7254.0 RESIST............................................................................................. 7294.1 Introduction ........................................................................... 7294.2 Resist Properties .................................................................... 7334.3 Positive Electron-Beam Resists.............................................. 7354.4 Multiple-Layer Resist Strategies ............................................ 7384.5 Negative Electron-Beam Resists ............................................ 7434.6 Conductive Overlayers .......................................................... 7454.7 Inorganic Resists and Self-Assembled Monolayers .............. 7465.0 COMPETING TECHNOLOGIES ....................................................... 7466.0 ACKNOWLEDGEMENTS ............................................................... 750REFERENCES ........................................................................................... 7508 Rational Vibration and Structural Dynamics forLithographic Tool Installations ........................................... 756Kenneth Medearis1.0 INTRODUCTION............................................................................. 7562.0 STRUCTURAL DYNAMICS, VIBRATION, AND STRUCTURALENGINEERING ................................................................................. 7583.0 TOOL EXCITATION SOURCES AND LEVELS ............................... 7583.1 Tool Excitation Sources and LevelsCase Study 1 .............. 7603.2 Tool Excitation Sources and LevelsCase Study 2 .............. 762Contents xix4.0 DISPLACEMENT, VELOCITY, OR ACCELERATION CRITERIA.... 7674.1 Floor Displacement Criteria .................................................... 7684.2 Tool Manufacturers Floor Vibration Specifications ............... 7745.0 VIBRATION-RESISTANT SUPPORT PEDESTALS FOR TOOLS .... 7766.0 SYSTEM ISOLATION .................................................................. 7837.0 CONCLUSIONS AND COMMENTS ............................................... 7848.0 RECOMMENDED TOOL AND FLOOR VIBRATION CRITERIA.... 787REFERENCES ........................................................................................... 7899 Applications of Ion Microbeams Lithographyand Direct Processing.......................................................... 790John Melngailis1.0 INTRODUCTION............................................................................. 7902.0 ION-SURFACE INTERACTION....................................................... 7923.0 FOCUSED ION BEAMS................................................................... 7993.1 Machinery .............................................................................. 7993.2 Point Sources of Ions............................................................. 8003.3 Ion Column ............................................................................ 8053.4 Beam Writing ......................................................................... 8064.0 FOCUSED ION BEAM APPLICATIONS ......................................... 8144.1 Low Energy Ga Ion Beam Applications ................................. 8144.2 Applications of the High-Voltage Mass-Separated FIB Systems .......................................................................... 8275.0 FOCUSED ION BEAM LITHOGRAPHY.......................................... 8326.0 MASKED ION BEAM LITHOGRAPHY .......................................... 8366.1 The Mask ............................................................................... 8367.0 ION PROJECTION LITHOGRAPHY ................................................ 8407.1 Ion Source .............................................................................. 8417.2 Mask ...................................................................................... 8417.3 Ion Optical Column ................................................................ 8447.4 Pattern Lock System .............................................................. 8447.5 Optical Column Design .......................................................... 8457.6 Stochastic Blur ....................................................................... 8467.7 Resist Exposure...................................................................... 846xx Handbook of VLSI Microlithography8.0 CONCLUSION ................................................................................. 848REFERENCES ........................................................................................... 84910 X-Ray Lithography .............................................................. 856William B. Glendinning and Franco CerrinaPART I ....................................................................................................... 8561.0 INTRODUCTION............................................................................. 8562.0 X-RAY PRINTING METHODSYSTEM APPROACH................... 8572.1 X-Ray System Definitions ...................................................... 8592.2 Minimum Feature Size and Line Width Control ...................... 8592.3 Overlay Accuracy .................................................................. 8622.4 Throughput ............................................................................ 8633.0 X-RAY SYSTEM COMPONENTS.................................................... 8643.1 Sources for X-Ray Flux .......................................................... 8654.0 MASK TECHNOLOGY .................................................................... 8704.1 Minimum Line Width and Control .......................................... 8724.2 Overlay .................................................................................. 8744.3 Throughput ............................................................................ 8745.0 MASK CONSTRUCTION................................................................ 8745.1 Mechanical and Optical Distortions ...................................... 8795.2 Defects ................................................................................... 8845.3 Inspection .............................................................................. 8865.4 Pattern Generation ................................................................. 8866.0 ALIGNMENT ................................................................................... 8876.1 Interferometric Schemes ......................................................... 8896.2 Non-Interferometric Schemes................................................. 8977.0 RESIST............................................................................................. 8998.0 METROLOGY .................................................................................. 9019.0 X-RAY SYSTEM.............................................................................. 9029.1 X-Ray Radiation Damage to IC Devices ................................ 90810.0 CONCLUSION FOR PART I ............................................................. 910PART II ..................................................................................................... 91211.0 SYNCHROTRON RADIATION SOURCES ...................................... 91211.1 Introduction ........................................................................... 91211.2 Properties of Synchrotron Radiation ..................................... 91312.0 TYPES OF MACHINES ................................................................... 930Contents xxi13.0 BEAM TRANSPORT SYSTEMS ..................................................... 93313.1 Vacuum Requirements ............................................................ 93613.2 Optical .................................................................................... 94013.3 Data Communication .............................................................. 94413.4 Safety Issues ......................................................................... 94413.5 Machines and Lithography.................................................... 94614.0 ACKNOWLEDGMENT ................................................................... 947REFERENCES ........................................................................................... 948Index........................................................................................... 957JMR- 30-Nov-00Lithography Tool Selection 1JMR11/30/0011.0 INTRODUCTIONIntegrated Circuit (IC) fabrication requires performing a long se-quence of many complex processes. Lithography, which recurs typically asmany as ten to thirty-plus times for a given device flow, is the mostimportant of these complex processes as it is used to define the dimensions,doping, and interconnection of each segment of each device. Literally, thisindirect process defines nearly all of the working elements for the IC device.The domination of lithography in the total cycle time to fabricate an ICdevice is shown in Fig. 1.[1] Lithography consumes ~60% of the total timeand roughly 40% of the cost required to fabricate IC devices! Since labor1Issues and TrendsAffecting LithographyTool Selection StrategyPhillip Blais and Michael MichaelsWestinghouse Electric CorporationAdvanced Technology LabsBaltimore, MarylandJohn N. HelbertMotorola, Inc.Compound Semiconductor Fab-2Mesa, Arizona2 Handbook of VLSI Microlithography11/30/00JMRcosts are directly proportional to cycle time, the selection of the appropri-ate, and hopefully optimum, lithographic technique and associated tool canbe critical to the success of a wafer fab operation. The best choices maydiffer for experimental fab operations compared to high volume productionfabs, but in either situation, the choice can be critical. Factors governinglithographic technique and tool selection begin with a basic requirement fortechnical capability, continue through economic considerations, and fi-nally end with such factors as production volume, turnaround time, productplanning, process availability, and others.Since the early days of semiconductor production, optical lithogra-phy has always been the choice for volume semiconductor manufacturing.The real question is when will this choice be for a non-optical method? Thenon-optical players have not really changed since the early 1980s, exceptfor their delay to become mainstream or used for volume production. Theseplayers are still e-beam, x-ray, ion-beam, and extreme-UV (EUV).[2] Forexample, since the 1960s optical lithography has been the cost effective toolof choice, while the industry has seen the number of CMOS device levelsgo from eight to thirty-plus layers; in the meantime, x-ray lithography(1979) has been relegated to an R&D status and probably will remain thereuntil dimensions become less than 0.130.10. The barriers are always costand infrastructure, not technical capability, even for the next opticalgenerations. Infrastructure is defined as reliable resist processing andsupplies, appropriate mask technology, metrology with a gauge capabilityat the next generation of critical dimension (CD), tool vendor support, andso on.Figure 1. Lithography dominates in determining the total cycle time for IC processing.Lithography Tool Selection 3JMR11/30/00In the 1970s and early 1980s, optical exposure tools operated at ~400nm on average, and the feature sizes were always greater than the wave-length of the exposure tool at 1.5 to many microns. In 1996, Sematech felt0.30 m was the limit for i-line lithography, and this limit was now less thanthe tool illumination wavelength for the first time.[3] For optical lithogra-phy, there has always been an effort to use imaging fabrication tools atfeatures less than the wavelength of the tools actinic source. In the past,these efforts were mainly focused in research or development areas, but inthe future, production tools will also be employed at more aggressiveperformance levels. Optical design rules at a fixed numerical aperture(NA)/wavelength (WL) ratio are governed by k1 selection and confined tok1 for space and pitched line sums greater than 0.5. To extend optical toolusage at a given NA/WL to lower k values requires the application ofwavefront engineeringoff-axis reticle illumination schemes (OAI), op-tical proximity connection (OPC) and the use of phase shifting masktechnology (PSM), or all three. OPC has seen applications over the last twoyears, but the powerful combinations of techniques are still being devel-oped. If achieved, these combinations could lead to E2: At impact energies higher than E2, the beam penetrates muchdeeper than the escape depth LSE. Each incoming electron gives rise to fewerthan one exiting electron. The local potential tends to become more negative.PE = E2: At E2, each incoming electron gives rise to one exitingelectron. There is no charging at this impact energy. Just below E2, thecharging effect increases the impact energy, and just above E2, the chargingeffect decreases the impact energy. E2 is, therefore, a stable point ofoperation, which is ideal for avoiding charging effects.Calculated Sil icon Electron Yield00.20.40.60.811.21.41.61.820.1 1 10Beam Energy, PE( keV)Yield, +E2 E1Figure 17. Total electron yield ( + ) as a function of primary beam electron energy.402 Handbook of VLSI Microlithography11/30/00JMRInfluence of Charging on Contrast. The discussion above, Con-trast in CD-SEM Images, indicated better SE emitterswhether due tosurface tilt, material difference, or surface texturewill produce a brighterimage than poorer SE emitters. This is true only for grounded, highlyconducting samples. If charging occurs, contrast between different por-tions of the image also depends upon the local electrical potential. E2 is astable point. Different parts of a low conductivity sample tend towardsdifferent local potential, so that the local impact energy tends toward thelocal value of E2. The contrast then results from differences in detectorefficiency. Positively charged areas have a lower electric field driving SEto the detector and appear darkeven black. Negatively charged areasappear bright or whiteso-called blooming. Such effects vary withchoice of PE, magnification, beam current, and scan rate.As discussed in the above section on edge contrast, a tilted samplesurface produces higher electron yields. Thus the yield curve, Fig. 17,shifts upwards for tilted surfaces. This has been exploited in tilt-stageSEMs to reduce negative charging when the beam energy is higher thanE2 on the flat surface.[19][20] Figure 18 shows scans of isolated resist lineson silicon under varying conditions of beam current and tilt.[21]In Fig. 18, the high dose scan on the flat sample ( = top down) withPE > E2 causes a bright resist image due to negative charging. Whentilted, as in the middle scan, the same resist sample now has E2 > PE. Thisresults in positive charging, and a darkened resist image. In the third scan,a reduction in dose (beam current) eliminates blooming on a flat sample.The trailing edge (right side) of the third scan, however, exhibits increasedbrightness due to negative sample charging during the scan.Figure 19 shows three rotated scans of the same sample of resist onsilicon. Charging is responsible for the varying image of the silicon nearthe ends of the lines. As the beam rasters left-to-right across the sample,the SE production, trajectory, and detection is influenced by chargeleft behind at previous locations in the scan. Without chargingsincenothing is changed other than the scan directionall three images wouldbe identical.Figure 18. Scans of isolated resist lines on silicon under varying conditions of beam currentand tilt. The beam energy is 1.0 kV.Techniques and Tools For Photo Metrology 403JMR11/30/00Effect of Charging on CD Measurement. The changing verticallevel of the arrowheads in the above Fig. 18 indicates the difficulty ofchoosing the correct threshold of brightness for determining the linewidth. Charging alters the contrast or brightness level. This affects thebase line location, which is a fundamental starting point for CD measure-ment algorithms. Surface charge also bends the actual electron paths,producing a distorted image or measurement scan.[23] Figure 20 illustratesa calculation of the distortion effect for large beam currents. In this model,the beam induces a conducting layer at each surface of the insulator. Theelectrostatic field due to negative charging deflects the primary beamlaterally. In Fig. 20, the CD measured would be smaller than the actualsize.The above theory explains only one particular charging effect. Ingeneral, however, charging degrades CD-SEM measurement accuracyand reproducibility in a number of ways, most of which are poorlyaccounted at the present time.Figure 19. Evidence of charging effects in a scan rotation.Figure 20. Illustration of a possible mechanism of image distortion due to negativecharging.[23]404 Handbook of VLSI Microlithography11/30/00JMR2.3 CD-SEM Measurement ValidityThe fundamental issues in SEM CD metrology are single-toolreproducibility, tool-to-tool reproducibility or matching, and accuracy ofthe measurements. Statistical process control of single tool reproducibilityis important because when photolithographic or etch processes vary,metrology is always a possible initial suspect. Statistical tool matching isimportant because any such complex tool will suffer downtime for main-tenance or repair, and a certifiably equivalent CD-SEM must be substi-tuted to avoid interruption in the flow of product. Accuracy of measure-ments would be less important if offsets were absolutely constant. Ascritical dimensions have decreased, the offsets have become a largerfraction of the measurement (~20 % for 0.25 m technology). Any changein the offset due to process changes such as sidewall profile, surfacecondition, charging, etc., impact the reproducibility.Single Tool CD-SEM Statistical Process Control. A standardmetrology tool control chart plots the daily measurement(s) on a goldenwafer at the same site(s) every day. Statistical process control (SPC) ofthe CD-SEM is hampered by a lack of repeatability due to sample degra-dation. This section first discusses the target degradation. An examplebased upon actual control charts is given to illustrate the standard linewidth SPC and typical 0.5 micron generation CD-SEM reproducibilityperformance. Finally there is brief discussion of delta-to-predicted(DTP) statistical process control. DTP is a more sophisticated chart whichcompensates for target drift.Problem of Target Degradation. Degradation can result in mea-surement feature shrinkage, growth, or both, depending on the number ofrepeated measurements. Figure 21 shows line broadening after repeatedmeasurements. F. Mizuno et al. have discussed electron beam assisteddeposition of hydrocarbons, resist shrinkage due to electron beam inducedcross-linking, and charging.[24] The effects have been statistically mod-eled by K. Monahan, et al.[25] They point out that the traditional methodsfor mitigating such effects are to minimize beam current, sampling time,and magnification. Unfortunately, these methods also reduce signal-to-noise and increase the uncertainty of the measurement.SPC control of the measurement tool relies upon long-term repeti-tion of measurements on the same target. A typical way to circumvent theproblem of degradation is to rotate targets. A common method for dealingwith degradation on etched targets is to use an O2 plasma clean to removecontamination on a regular basis.[26] W. Keese has suggested theTechniques and Tools For Photo Metrology 405JMR11/30/00methodology of measuring a different site every day.[27] The SPC wafercontains thirty-one sites, and the first site is measured on the first day ofthe month, second site on second day of the month, etc. It then takes ~1month to establish statistical process control.Figure 21. Repeated measurements cause substantial increase in measured line width. (SeeRef. 29, p. 219)Example of CD-SEM Single-Tool Statistical Process Control.Figures 2224 illustrate about nine months of statistical process control ona 0.5 micron generation CD-SEM. The method used in this example wasto measure four sites daily, as well as a fifth site for pitch verification. Thefour sites consisted of two horizontally- and two vertically-oriented linewidth targets. Anticipating target wearout, a large number of sites weremeasured initially. These initial values became the target numbers forchecking long-term reproducibility.DeltatoT arget-0.02-0.0100.010.023-Feb 3-Apr 2-Jun 1-Aug 30-Sep4 Sites AvgSigma DTTtargetchangeFigure 22. Delta-to-target SPC chart shows target degradation and periodic replacement.406 Handbook of VLSI Microlithography11/30/00JMRTypes of Control Charts for CD-SEM SPC. The SPC approach wasto measure daily and plot the average of the four deltas-to-target (DTT).(See Fig. 22.) The standard deviation of the four |DTT|s was placed underSPC as well. The difference between the vertical average DTT and thehorizontal average DTT was tracked to provide further information aboutbeam alignment (Fig. 24). The pitch measurement was tracked to providea very basic accuracy check (Fig. 23).CD-SEM Reproducibility Performance. The dominant characteris-tic of the CD-SEM performance revealed in Fig. 22 was target wearout.Within two to eight weeks the CD measurement grew beyond the allowedlimit, and required replacement. The fresh site was generally much closerto its target value. However, the next few readings showed a negativetrend, due to a reduction in the sidewall image brightness. After severalreadings, a positive growth trend, ~1 nm per repeat, began to dominate thecharacteristic.The SPC record for the first ~30 days (Fig. 22) indicated anothertypical problem. This was a period of start-up, characterized by improperbeam maintenance. The stigmation plot was particularly sensitive tobeam setup errors. Vertical and horizontal features had a different focusdue to astigmatism. The poorly focused orientation measured largerthan the sharply focused orientation due to the thresholding line widthPitch2.472.482.492.52.512.523-Feb 3-Apr 2-Jun 1-Aug 30-SepPitchStigmation-0.02-0.0100.010.023-Feb 3-Apr 2-Jun 1-Aug 30-SepStigmatFigure 23. Pitch SPC plot is a sensitive warning signal against SEM magnification changes.Figure 24. Stigmation SPC plot charts the difference between vertical and horizontalmeasurements. Beam tuning errors are detected.Techniques and Tools For Photo Metrology 407JMR11/30/00algorithm.[28] The pitch record of Fig. 23 showed no abnormality. Pitch isvery insensitive to focus and other beam problems. Sigma DTT showedsome large values due to stigmation errors.Toward the end of the record, DTT, sigma DTT, and Pitch recordssignaled a scanning amplifier calibration error. This is an unusual, but avery serious, problem. A pitch record is basic to assuring scanning accuracy.Delta-to-Predicted (DTP) Statistical Process Control. The el-egant way to handle target degradation is to plot and control thedifference between measured and predicted target values.[29] Figure 25shows a target degradation trend. Figure 26 shows the same plot after alinear correction is made for daily target growth. The target growth inthis case was 0.7 nm/reading. Note that the control limits were 73 nmwhen the target degradation was not compensated (DTT), whereas itwas 15 nm in the DTP scheme. There was thus a ~5X tightening ofcontrol using DTP.Figure 25. Trend of target degradation in a conventional delta-to-target (DTT) control chart.The step indicates a change in target.Figure 26. Trend of target degradation is theoretically compensated in a delta-to-predicted(DTP) control chart.408 Handbook of VLSI Microlithography11/30/00JMRMulti-Tool CD-SEM Matching. The complexity of the CD-SEMmeasurement process limits the throughput: the high vacuum interlock,multiple optical and SEM image pattern search/recognition and alignmentsteps, automated mechanical and e-beam focusing, multiple low-currentmeasurement scans, and multi-site measurement plans each play a part inlimiting the wafer throughput of the tool. The quantity of stepper setupjobs and product CD measurement tasks usually requires the capacity ofseveral CD-SEMs in a semiconductor facility. CD-SEMs are subject todown-time for replacement of e-beam components due to contaminationand wear out. Major preventive maintenance and repairs to the e-beamcolumn incur additional downtime (824 hours) to bake out the vacuumsystem before resuming operation.Because of the above circumstances, it is essential that the multipleCD-SEMs within the fab be interchangeable for semiconductor measure-ments. The measurements must match. Matching is likely to be achievedonly when the hardware is identical (same manufacturer and model num-ber), the software recipe is identical (preferably downloaded from acommon server), and the beam is maintained and tuned according to adaily or shiftly schedule (focus, astigmatism, aperture alignment).Matching can be defined as the tool-to-tool component of measure-ment reproducibility. Matching is, therefore, a statistical concept, andstatistical process control is used to flag CD-SEMs that do not match.[30]The accepted procedure is to measure the same wafer(s) with each of theCD-SEMs in the fab. Measurement problems are specific to each layer, sowafers should be chosen to represent the critical layers in the manufactur-ing process. Wafers should be specially patterned with a focus-exposurearray so that the different sites on the wafer represent a realistic range ofprocess variations encountered in manufacturing. Because most line widthsgrow a fraction of a nanometer with each repeated measurement, thesequence of tools should be rotated or randomized, and/or the apparentgrowth can be taken into account.[31] An assessment of the contaminationgrowth can be made by observing the growth trend in the test data over aperiod of many days, orwhat is slightly differentby observing growthin a dynamic repeatability test on a single tool.Matching Statistics. A single matching test on one layer consists ofmeasuring each of several sites on a wafer, using exactly the same recipe,on each of the CD-SEMs. As an example, the test data for five differentCD-SEMs on a wafer with five sites is shown in Table 1. The correctionfor line width growth is assumed to be negligible. The data is plotted inFig. 27.Techniques and Tools For Photo Metrology 409JMR11/30/00Matching Raw Data0.2060.2080.210.2120.2140.2160.2180.220.2220.2240.2260 1 2 3 4 5 6site #sem 1sem 2sem 3sem 4sem 5Figure 27. Plot of line width measurements at 5 different sites on a test wafer using 5 SEMsto be matched.In this example, SEM 4 is apparently different from the other toolsin the set. The question is, which SEMs differ significantly from theothers. The following three tests[32] can supply an answer: (1) The ANOVAtest can determine whether changing SEMs is a significant effect, but doesnot determine which SEMs are different. (2) A t-test can be used betweeneach different pair of SEMs to determine whether there is a statisticallysignificant difference between that pair. This test becomes unfairly strictin very large tool sets when testing tools from opposite extremes of thedistribution. A test which loosens the criterion appropriately at the ex-tremes in large sets of tools is (3) Duncans Multiple Range Test.The ANOVA test for the data of Table 1 is shown in Table 2. In theANOVA table, column p (probability of a null effect) shows which effectsTable 1. Example Matching Test DataLinewidth, micronsSEM # site 1 site 2 site 3 site 4 site 5 wafer avg.sem 1 0.207 0.213 0.215 0.211 0.209 0.211sem 2 0.212 0.217 0.212 0.213 0.213 0.2134sem 3 0.214 0.214 0.214 0.215 0.215 0.2144sem 4 0.219 0.225 0.222 0.219 0.223 0.2216sem 5 0.207 0.21 0.211 0.215 0.211 0.2108site avg. 0.2118 0.2158 0.2148 0.2146 0.2142410 Handbook of VLSI Microlithography11/30/00JMRare important. In this case, changing SEMs contributes strongly, andchanging sites contributes weakly, to the total variation in the measure-ment data. The ANOVA table is important because it calculates the meansquare error (MSE)i.e., the residual measurement noise remaining afterknown influences such as SEM differences and the site differences aremodeled. The MSE will, therefore, be the quantity of importance in anystatistical tests. In Table 2, the MSE is found in the error row under thecolumn ms.A simple t-test for each pair of CD-SEMs is illustrated in Table 3.The left side of the table lists all pairs of SEMs. For each pair, the absolute-value of the difference in average reading is shown. On the right side of thetable, the difference is compared with (2.MSE/5). This is the uncertaintyin the difference between two averages of five readings. The t-test can beused to determine the significance of the difference between two averagereadings. For 0.05 probability of error, the appropriate statistic is the two-sided t-distribution with (degrees of freedom) df = # measurements - #SEMs = 20 and an of 0.025. The significant differences according to thistest are underlined.sem differences: t-test:|difference|/Pair |difference| sqrt(2*mse/5) t.025,20 1&2 0.0024 1.76 2.086 1&3 0.0034 2.50 1&4 0.0106 7.78 1&5 0.0002 0.15 2&3 0.001 0.73 2&4 0.0082 6.02 2&5 0.0026 1.914&3 0.0072 5.28 3&5 0.0036 2.64 4&5 0.0108 7.93Table 3. T-Test Tabulation for the Above Matching DataTable 2. ANOVA Table for the Data of Table 1source SS df ms F p Fcritsem-to-sem 0.000386 4 9.65 E-05 20.81 3.52 E-06 3.01site-to-site 0.000044 4 1.10 E-05 2.38 9.52 E-02 3.01error 0.000074 16 4.64 E-06total 0.000505 24 2.10 E-05Techniques and Tools For Photo Metrology 411JMR11/30/00Figure 28 illustrates the results of the t-tests performed above. Asolid line connects the CD-SEMs 1, 2, and 5, which have insignificantdifferences. CD-SEM 3 is marginally different from 1 and 5, as indicatedby the dashed black line. The dot-dashed line shows the main problem:SEM 4 is significantly different from all other SEMs. The appropriateaction is to correct SEM 4, followed by SEM 3.Figure 28. Matching analysis chart. Statistical methods determine which pairs of SEMs areunmatched. SEM 4 shows statistical difference from all other SEMs. It has top priority forcorrective action.Duncans test is slightly more sophisticated, and may be justifiedfor matching large numbers of tools. A tabulation of Duncans Test for theabove matching data set is shown in Table 4. In the first section of thetable, the SEMs are sorted by descending line width average result. In themiddle section, all possible pairs of SEMs are listed: first the adjacentpairs in the ordered list (p = 2), then next neighboring pairs (p = 3), etcetera. For each pair, the difference in average reading is tabulated. In therightmost section, the difference is divided by (MSE / # sites), which isthe uncertainty of a 5-site average. The quotient in this column is ameasure of the significance of the difference, and is to be compared withr.05(p, 25), for p = 2, 3, 4, and 5. These r-values are tabulated significantranges for Duncans Multiple Range Test. Here, 0.05 is the probability ofa null effect, and 25 is the number of measurements in the data set. Thesignificant ranges are underlined. Note as p increases, the r-values areincreasing slightly, making the test less stringent at the extremes of thedistribution. Also note the comparisons made in the t-test for signifi-cance are basically equivalent to those in Duncans test: in Duncans testthe columns are in approximately the same ratio as in the t-test, so thecomparisons are approximately equivalent.412 Handbook of VLSI Microlithography11/30/00JMRsort averages: find all pair differences: test significance:difference/SEM# averages Pair p differences sqrt(mse/5) r.05(p,25)4 0.2216 4&3 2 0.0072 7.47 2.923 0.2144 3&2 2 0.001 1.04 2.922 0.2134 2&1 2 0.0024 2.49 2.921 0.211 1&5 2 0.0002 0.21 2.925 0.2108 4&2 3 0.0082 8.51 3.07 3 &1 3 0.0034 3.53 3.07 2&5 3 0.0026 2.70 3.07 4&1 4 0.0106 11.00 3.15 3&5 4 0.0036 3.74 3.15 4&5 5 0.0108 11.21 3.225Matching Corrective Actions. The corrective action for a matchingerror is usually to retune the adjustable beam parameters, change theaperture, or perform some other routine maintenance of the maverickSEM. High quality recipe management systems, which download recipesfrom a common server at the time of use, assume that all tools run identicalrecipes. This rules out recipe-dependent slope-offset corrections for indi-vidual tools. Any corrections to the maverick tool must, therefore, be on asystem-wide level of hardware or software.CD-SEM Calibration. Calibration standards are important for ametrology tool to maintain reproducible and accurate measurements.Whereas a golden standard can provide a basis for determining reproduc-ibility over time within a fab, a certifiable standard can guarantee repro-ducible processing across geographically and/or temporally separatedfabs. Calibration standards are especially important for the CD-SEMbecause of the strong dependence of line width measurement upon thechoice of algorithm used to interpret the line scan.The CD-SEM has excellent sensitivity as a line width comparator:small differences in line width can be detected, provided all other vari-ables are kept constant. This suggests that the existence of a good linewidth reference standard would make possible more accurate and repro-ducible measurements.The utility of a line width calibration standard for CD-SEMs isdiminished by the fact that the e-beam sample interaction is very material-dependent. Consequently a different reference standard would be neededTable 4. Table Illustrating Duncans Multiple Range TestTechniques and Tools For Photo Metrology 413JMR11/30/00for each different material. The sidewall angle and other details of theprofile must be identical between the product sample and the referencestandard to give a correct calibration. The charging phenomenon on manymaterialsincluding photoresistis variable from sample to sample.Charging also dictates low voltage and beam current, resulting in rela-tively poor contrast, resolution, and signal-to-noise. Under low signal-to-noise conditions, the information offered by comparison with a standard isdiminished. Finally, target degradation requires that the reference stan-dard be renewed frequently, or certified at a large number of sites.Pitch Calibration Standards. A pitch standard does not present somany difficulties as a line width standard. The edge location offsets due tobeam-sample interaction, sidewall details, charging, and even target deg-radation are essentially invariant from one line to an adjacent line in apitch standard. Most any algorithm can successfully measure the pitch.Although the pitch is not directly important to the operation of mostsemiconductor circuits, it does contain very significant information aboutthe absolute magnification and any variability in magnification. All CD-SEMs assume correct and constant magnification as a given in the outputof a line width measurement.The key requirements of a pitch calibration standard have beenpointed out by E. Chain et al.[33] These include traceability, low edgeroughness and pitch variation, good contrast, construction out of materialscompatible with semiconductor facilities, and a size range commensuratewith submicron semiconductor device features. Such a standard can bepermanently mounted on the SEM stage. The standard has been used tomatch magnification among several SEMs to within 0.6% at 60,000X.Pitch standards are available, including the 0.24 micron pitch stan-dard used by the above authors.[34] This pitch standard was patterned usinglaser interferometer lithography.[35]The National Institute of Standards and Technology (NIST) devel-oped a Standard Reference Material (SRM)-484 in 1977.[36] This materialconsists of alternating electrodeposited layers of gold and nickel turned onedge and polished. The spacings are viewed using a FE-SEM with a laserinterferometer stage to measure the displacements under the beam. Thepitch between gold lines ranges from ~0.5 micron (spacing uncertainty~4%) up to even larger sizes, so that this material is pass with respect toadvanced lithographic requirements.NIST has developed SRM-2090A as a magnification calibrationstandard to replace SRM-484.[37] Prototype samples were fabricated bymetal lift-off on e-beam-written patterns. The pitch ranges from 3000 to414 Handbook of VLSI Microlithography2/23/01JMR0.2 micron. Experimental samples are available but not yet certified at thetime of this writing.Line Width Standards. Despite the challenges, certifiable line widthstandards are being developed. The methodology is to fabricate sub-microncontrolled-geometry, single-crystal silicon electrical line width struc-tures.[38] The structures are patterned on (110) SIMOX and BESOI silicon,which are substrate technologies in use for Silicon-on-Insulator (SOI) devices.As is well known, a wet KOH etch will stop on the {111} crystallinefaces of silicon, resulting in vertical etch sidewalls on the (110) material.Therefore, it is possible to produce electrically isolated, free-standingrectangular silicon bars with atomically smooth sidewalls. An example ofstructures fabricated in (110) BESOI are shown in Fig. 29.[39] Measure-ments by optical, SEM, AFM, and SEM cross-section techniques are allpossible on the same material and are relatively easy to model. The physics ofconduction should also be easy to understand for these structures. Theintent is to compare metrology techniques, to establish the true line width,and to take advantage of the ease and precision of electrical resistancemeasurements to proliferate certified line width standards inexpensively.Figure 29. Nearly ideal geometry line width test structure fabricated from (110) BESOI. Thefeature depicted is ~1 micron high and ~1 micron wide, has precisely vertical sidewalls, andrests on an insulating substrate. (See Ref. 39, p. 127.)3.0 ELECTRICAL CD (ECD) METROLOGYElectrical CD measurements have always occupied an importantplace in final device testing. Because the CD-SEM has gauge capabilityand accuracy issues for 0.18 micron technology and below, ECD measure-ment has also become an important in-line CD measurement and controltechnique. ECD is useful only on conducting layers. Polysilicon gate andmetal are two critical layers that fall into this category. The advantages ofTechniques and Tools For Photo Metrology 415JMR11/30/00ECD are superior gauge capability, higher throughput, and lower equip-ment cost. Furthermore, the line conductances directly affect circuitperformance. Top-down line width per se is not a device parameter.The main disadvantage is electrical contact with the wafer may causecontamination.ECD can also be used off-line to characterize stepper performance.[40]The additional time required for etch processing is more than compen-sated by high gauge and speed, which permits many thousands of mea-surements to be made for a characterization.3.1 Types of ECD Test StructuresThe simplest accurate test configuration for electrical resistance is afour-terminal network, shown in Fig. 30. A current is forced through twoof the terminals, and the voltage is read at the other two. Separateterminals for current and voltage allow the measurement to be indepen-dent of contact resistance.Figure 30. Four terminal resistance for accurate line width measurement.An electrical line width measurement combines a four-terminalresistance measurement with a sheet resistance measurement to compen-sate for local film thickness and doping variations. The sheet resistance ismeasured using a coarse line width van der Pauw pattern, Fig. 31. Thesheet resistance is given byEq. (5) ( )( ) 2 ln I V Rsheet where V = |V1 - V2|, and I = | Iin | = |Iout|. Rsheet is then used to calculate thenumber of squares in the four-terminal resistance. The number of squaresequals the ratio of length to width of the line between the voltage taps.Eq. (6)width linelengthRRsheetterm

4Since the length of the network is known with good relative accuracy, theline width can be accurately obtained.416 Handbook of VLSI Microlithography11/30/00JMRThe electrical cross bridge combines the van der Pauw and thefour-terminal network into one basic test structure.[41] Buehler et al. haveproposed a more advanced split-cross-bridge.[42] The latter combinesthe van der Pauw and two four-terminal networks in series. One large-width line is placed in series with a second large-width line that has aspace cut out. This second conducting network permits both lines andspaces to be measured. (See Fig. 32.) The authors have worked outtheoretically all the design rules for this structure to provide accurate CDmeasurements.The split-cross-bridge concept can be extended to the measurementof contact hole size. (See Fig. 33.) Contact hole geometries are cut outfrom a wide line and the size is calculated from the increased resistance ofthe remaining conducting material.[43]3.2 Gauge Capability and Accuracy of ECDTypical ECD gauge capability is indicated[44] in Fig. 34. For compari-son, contemporaneous CD-SEMs give ~5 nm reproducibility, about anorder of magnitude larger than ECD. Several advantages favor the greaterreproducibility of ECD metrology: (a) The ECD test structure samples asignificantly longer line than a CD-SEM. ECD gives a more precise linewidth reading because it averages line width non-uniformities. (b) Thespecific location of sampling is absolutely fixed in ECD, whereas sam-pling location depends upon accurate measurement gate placement in theCD-SEM. (c) There is no evidence of target degradation in ECD.Figure 31. Van der Pauw resistor for determining sheet resistance.Techniques and Tools For Photo Metrology 417JMR2/23/01Figure 32. The Split-Cross-Bridge[26] is a carefully designed network which providesaccurate electrical measurements of both lines and spaces.Figure 33. The structure shown here consists of a conducting sheet with an array of contactholes etched out. This network can provide electrical measurements of contact holedimensions.418 Handbook of VLSI Microlithography11/30/00JMRThere is usually a substantial offset between ECD and top-down orcross-sectional SEM CD measurements. Figure 35 shows the relationshipbetween electrical and top-down CD-SEM measurement of submicronpolysilicon lines.[44] There is a substantial, variable offset between the twotechniques. A different comparison[45] of electrical and SEM over a widerrange of sub-micron nested poly line widths is shown in Fig. 36. There isa significant, constant offset between electrical and SEM measurements.The offset is due either to the uncertainty in SEM accuracy (beamwidth, charging, obscuration by overhanging or protruding parts of thefeature, inaccurate SEM algorithm, etc.) or to the lack of a correct theoreti-cal model of the actual conducting cross-section and conductivity in ECD.Electrical measurements are smaller than both CD-SEM and cross-sectionSEM measurements throughout the literature. This includes small linesfrom 150 nm[46] up to lines wider than two microns, first studied byBuehler and Hershey.[42] The CD-SEM presumably detects the maximum-width point of the cross-section, which must be equal to or greater than theaverage electrical cross-section. Advanced IC metrology needs a morecomplete understanding of the discrepancy.Figure 34. Daily measurement data demonstrating the excellent reproducibility of electricalline width measurements.[28]Techniques and Tools For Photo Metrology 419JMR11/30/00Figure 36. Relationship between ECD and SEM metrology of sub-micron nested polysiliconlines.[45] Note that SEM measurements have a positive offset from electrical measurements.Figure 35. Relationship between ECD and CD-SEM metrology of submicron polysiliconlines.[44]420 Handbook of VLSI Microlithography11/30/00JMR4.0 OVERLAY MEASUREMENTOverlay measurement detects the shift in positioning between twodifferent lithographic layers which are designed to be perfectly aligned. Ifcircuit elements such as metal lines and contacts, metal contacts and gates,transistor gates and isolation regions, etc., are not properly registeredacross the entire wafer, the circuits will not function.[47][49]The overlay tool has a few main uses in the photo area: (a) to checkthe alignment of photoresist images on product so that misaligned waferlots can be re-worked, (b) to check alignment on exposed product so thatoffsets can be anticipated and reduced on new work, and (c) to set upexposure tool alignment systems on test wafers and maintain registrationmatching between exposure tools.Optical overlay tools measure misregistration by scanning the mi-croscope image of an overlay target consisting of marks patterned at twodifferent layers. The marks are cleanly defined on many front-end waferprocesses. At such layers, the linearity of optics and the symmetry of themarks guarantee current overlay tools can achieve good measurementaccuracy and precisionadequate for the overlay requirements of todaysleading edge devices. On the contrary, there are unavoidable processes atcritical layers for which marks are poorly defined. At such layers theoverlay measurements can be noisy and unacceptably inaccurate. Unfor-tunately, the characteristics which compromise measurement marks atsuch layers frequently compromise the stepper alignment features as well.It then becomes doubly important to check the alignment performanceusing accurate overlay metrology.4.1 Basic Optical Overlay MeasurementThe overlay feature consists of inner and outer marks patterned attwo different layers. A typical feature is illustrated in Fig. 37. The overlaytool maps the scan of each edge of the mark onto the reflected scan of thesymmetrically opposing edge. The offset which causes the two scans tooverlap with maximum correlation determines the midpoint (or centroid)of the mark. The difference in centroids of the inner and outer marks is themisregistration between layers.Techniques and Tools For Photo Metrology 421JMR11/30/00inner mark10 umouter mark20 umouter box scanFigure 37. Typical optical overlay mark and optical scans.4.2 Overlay Metrology Tool PerformanceTool-Induced Shift (TIS). The accuracy of overlay measurementdepends upon the symmetry of the hardware. Any imperfection in theoptics, including the illuminator, the objective, or the camera/scanner, cancause an asymmetry in the image. This introduces an offset in the results.This offset is called tool-induced shift (TIS). Figure 38 shows how a tiltin the optics produces a parallax contribution to TIS.Tilted optical axisshifted imageFigure 38. Illustrates how asymmetry in the overlay measurement optics causes an apparentshift in alignment known as tool-induced shift (TIS).422 Handbook of VLSI Microlithography11/30/00JMRLarge TIS problems are associated with back-end processing inwhich the aligned layers can have a large Z-separation. In Fig. 39, the TIShas been plotted for a large number of different targets with a variety ofprocesses and z-separations between inner and outer targets.[50] Figure 39shows the correlation between TIS and Z-separation for one particular tiltof the illumination axis. The relationship is 45 nm TIS per micron of z.Figure 39. Correlation between measured value TIS and z-separation between the inner andouter overlay target.[50]In practice, TIS errors can generally be held to within a few nanom-eters. Since wafer topography is often microns in depth, just minutes of tiltor equivalent optical asymmetry can cause this level of TIS. TIS across thewhole range of process targets must be minimized by fine adjustment ofthe optical hardware.TIS depends strongly upon focus. For each individual process layer,optimum focus minimizes TIS. Surprisingly, blurring the image moder-ately does not adversely affect the repeatability of the overlay measure-ment. Within limits, there is considerable latitude to choose the focus thatoptimizes TIS or some other critical parameter. This latitude is extendedTechniques and Tools For Photo Metrology 423JMR11/30/00even further by focusing separately upon the inner and the outer targets.The additional time and hardware activity have a slightly adverse affectupon repeatability of the measurement, but the trade-off in terms of TISimprovement is significant.The overlay tool must have an extremely repeatable focusing capa-bility. The tool must select the same focus for every target encountered bya given recipe. Certain overlay tools use an interferometric microscope toidentify the exact focus.[51] Figure 40 is a diagram of a Linnik interfero-metric microscope.[52] Other tools insert a knife edge at the optical cross-over above the objective to test the exact focus.[53]Figure 40. Linnik interferometric microscope provides image phase contrast and permitshighly repeatable focus.TIS Correction. The TIS at the backend of the process (metalliza-tion) is usually significant, even at the best focus for minimizing TIS.Furthermore, it may be important to adjust focus to optimize site capture,flyer reduction, or target process noise instead of TIS. The accuracy ofoverlay measurement at the backend of the process, therefore, depends ongood TIS correction.424 Handbook of VLSI Microlithography11/30/00JMRThe overlay tool can measure and correct TIS. Rotating the wafer180 changes the sign of an actual misregistration; the TIS remainsunchanged. The formula for TIS is thenEq. (7)2180 0mreg mregTIS +

If tool utilization permits the additional measurement time, it ispossible to measure and subtract the TIS offset at every site. If toolutilization does not permit TIS measurement of every wafer, it may beadvantageous to include a fixed TIS offset in the recipe. This approachdepends on the TIS stability of the tool and upon the TIS stability of theprocess. This raises the question of TIS variability.TIS Variability. The TIS varies from site to site on a wafer. Across-wafer process variations such as film thickness and sidewall profilevariations cause TIS variability. The key recipe parametersthe numeri-cal aperture of the optics, inner target focus, and outer target focusmustbe optimized to minimize the average TIS as well as to avoid excessiveTIS due to normal process variation. It is possible to adjust most recipes sothat TIS variability is 3 510 nm, the upper number applying toconventional backend layers.Overlay Tool Repeatability. The overlay tool repeatability is typi-cally 3 ~ 3 nm. Larger values are unusual and indicate very low contrasttargets or hardware malfunction.Overlay Tool Matching. The matching of overlay tools has beenstudied by Merrill et al.[54] The chosen methodology avoids choice of onetool as a golden standard, but rather optimizes each machine separatelyby adjusting the hardware to minimize TIS and calibrating against a pitchstandard to minimize linearity error. The standard stage and focus calibra-tions were also performed on each tool separately. After these calibra-tions, the system-to-system variations were characterized on fifteen dif-ferent wafers on five different product layers. Each recipe was carefullyduplicated on all machines.Each recipe was offset so as to correct for tool induced shift (TIS) byperforming a TIS calibration. TIS correction is a standard procedure inoverlay metrology. TIS is not calibrated on every wafer because of thethroughput penalty. In the context of a multi-machine installation, how-ever, the TIS correction has the disadvantage of being a recipe-level ratherthan a system-level correction. In order to maintain recipe portability amongTechniques and Tools For Photo Metrology 425JMR11/30/00multiple machines, TIS correction should be the same for all the matchingtools. In the context of total quality, TIS correction must be a documentedcomponent of the recipe specification for the process layer in question.The misregistration was measured at 32 intentionally offset sites oneach of the five wafers using three overlay tools. The wafer average x- andy-misregistration was calculated for each overlay tool. The range acrossthe three tools of the wafer average x- and y- misregistrations for eachlevel are plotted in Fig. 41. Also plotted are the pooled standard deviationsof the mismatch for each site (mismatch being the difference between theindividual tool and the average of the tools at the site in question).MATCHING CHARACTERISTICS024681012NitrideXNitrideYPoly XPoly YOxide XOxide YTungstenSilicide XTungstenSilicide YMetal XMetal YNanometersRangePooled 3 Sigma Figure 41. Matching of misregistration measurements between three separate overlay tools.The range is the discrepancy of the wafer average among the three tools. The pooled 3-sigmavalues represent the across-the-wafer variation in mismatch between tools.The wafer average range of mismatch values are comparable with,and must be added to, other inaccuracies such as TIS and long termreproducibility.Figure 41 shows the overlay mismatch problem is complicated bythe fact that mismatch is highly site dependent. For example, at Metal, thestandard deviation of the mismatch for each site is considerably largerthan the wafer-average mismatch. Although it was possible to match themachines by inserting a matching offset (TIS correction) into the recipe ofeach tool at the metal level, the site variability of the TIS correction islarge. The matching at this layer is probably not robust with respect toprocess variations.426 Handbook of VLSI Microlithography11/30/00JMR4.3 Plotting Overlay ResultsIt is often useful to plot misregistration data on a spreadsheet.Typical output of an overlay tool consists of a list of X and Y misregistrationpairs, labeled by the die indices and the X-, Y- offset coordinates within thedie. This is illustrated after loading into a spreadsheet in Fig. 42.A B C D E F1 DieX DieY X_OFF Y_OFF Mis_X Mis_Y2 3 4 -9.33 -11.02 -0.003 0.073 1 2 -9.33 -11.02 0.099 -0.1294 3 0 -9.33 -11.02 0.15 -0.0055 5 2 -9.33 -11.02 0.042 0.1546 3 2 -9.33 -11.02 0.061 -0.027 ... ... ... ... ... ... G H1 Plot_X Plot_Y2 =B2*20+ROUND(D2,-1)+10+F2*40 =C2*20+ROUND(E2,-1)+10+G2*40Figure 42. Typical registration tool data output in spreadsheet format.The data can be plotted using simple spreadsheet functions. The X-and Y- transformations for plotting appear in column G and H, respec-tively, of Fig. 43. The object of these transformations is to use thespreadsheet chart grid as a representation of the wafer grid. The deviationof the plotted points from the grid vertices is in direct proportion to theregistration offsets.Figure 43. Spreadsheet formulas to represent overlay data as a dot-plot. These cells shouldbe appended in the columns to the right of Fig. 33, and Row 2 should be copied down.In the formula, the X- die index is multiplied by 20, the approximatedie size in mm. The offset within the die needs to be rounded off so that azero-misregistration point would fall exactly on a graph vertex. Themisregistration is magnified by a factor of 40, although this number isarbitrary and can be placed in a fixed spreadsheet cell such as $J$1. Theresult of these transformations is the very revealing plot in Fig. 44.Figure 44 shows the misregistration at the four corners of five dieson a wafer. This particular wafer has a large rotation error of both the gridand the individual dies. There is also a definite offset in the positive x-direction.Techniques and Tools For Photo Metrology 427JMR11/30/004.4 Process-Related Overlay Measurement ErrorsThere are two main process-related overlay measurement problems:(1) Marks are designed to be symmetrical, but the process can produceasymmetrical structures, and (2) local process effects, such as metal grainstructure, can distort the overlay target and produce target noise.Overlay Mark Asymmetry. Figure 45 shows a typical cornerlessframe-in-frame overlay feature. This overlay mark is highly immune toprocess variations. The removal of the corners reduces the influence of theprior mark on the resist flow for the subsequent mark. The overlaymeasurement structure has a symmetrical design and extends over only afew tens of microns. Most process variations that can affect line width andfeature profile such as exposure, film thickness(es), focus, surfacereflectivity, and surface morphology do not affect the measurement,provided all