08 rangkaian sekuensial
TRANSCRIPT
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RANGKAIAN SEKUENSIAL
• Flip flop
• Model Rangkaian Sekuensial
• Finite State Machines
• Diskripsi FSM
• Contoh
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Rangkaian Sekuensial
• Have memory (state)
– Present state depends not only on the current input,
but also on all previous inputs (history)
– Future state depends on the current input and state
))t(Q),t(X(F)t(Z
x1
x2
xn
z1
z2
zm
Z = z1 z2... zm
X = x1 x2... xn
Q = Q1 Q2... Qk
))(),(()( tQtXGtQ
Q
Flip-flops are
commonly used as
storage devices:
D-FF, JK-FF, T-FF
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Model Rangkaian Sekuensial
• Sifat:
– Sinkron
– Asinkron
• Model:
– Moore
– Mealy
• Finite State Machine
– Jumlah state berhingga (2 hingga 2N)
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Desain Synchronous
• Menggunakan Clock untuk meng-singkronkan semua operasi
FF, register, dan counter pada sistem
– Semua perubahan terjadi secara langsung mengikuti perubahan clock
– Periode clock harus cukup sehingga semua perubahan FF, register,
counter memiliki waktu yang cukup untuk menstabilkan statusnya
sebelum clock berubah ke keadaan selanjutnya
• Typical design: Control section + Data Section
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Principles mendesain Synchronous
• Metoda– Semua input clock ke flip-flop, register, counter, dll,
digerakkan secara langsung dari clock sistem atau dari clock yang di-AND-kan dengan kontrol sinyal
• Hasil– Semua state berubah secara langsung mengikuti
perubahan sinyal clock dalam keadaan active edge
• Keuntungan – Semua switching transients, switching noise, dll. terdapat
di antara clock pulse dan tidak memiliki efek terhadap performansi sistem
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Desain Asynchronous
• Kerugian- Lebih sulit– Masalah
• Race conditions: final state tergantung urutan perubahan variabel
• Hazards
– Diperlukan teknik spesial untuk mendesain agar kondisi race dan hazard terhindari
• Keuntungan = kerugian dari Desain Synchronous– Pada desain high-speed synchronous delay propagasi pada wiring
sangat significant sinyal clock harus hati-hati dirutekan sehingga dapat menjangkau semua perangkat pada waktu yang sama
– Inputs tidak sinkron dengan clock –dibutukan untuk mensingkronkan
– Siklus Clock is didefinisikan oleh delay dalam keadaan terburuk
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Model Rangkaian Sekuensial (1)
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Rangkaian Sekuensial: MooreOutputs hanya tergantung present state
))t(Q(F)t(Z
x1
x2
xn
z1
z2
zm
Z = z1 z2... zm
X = x1 x2... xn
Q = Q1 Q2... Qk
))t(Q),t(X(G)t(Q
Q
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Model Umum dari Mesin Sekuensial Moore
))t(Q(F)t(Z
Inputs(X)
Clock
Z = z1 z2... zm
X = x1 x2... xn
Q = Q1 Q2... Qk
))t(Q),t(X(G)t(Q
Combinational
Network
State
Register
Next
State
Outputs hanya tergantung present state!
Outputs(Z)
State(Q)
Combinational
Network
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Model Rangkaian Sekuensial (2)
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Rangkaian Sekuensial: MealyModel Umum Rangkaian Sekuensial Mealy
(1) X inputs dirubah ke nilai yg baru
(2) Setelah delay, Z outputs dan next state tampil sebagai output di CM
(3) next state dihubungkan sebagai state register dan perubahan state
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Finite State Machines (1)
• Representasi FSM:
– Diagram Keadaan
– Tabel Transisi Keadaan
– Bagan Algorithmic State Machines
– Hardware Description Language
• VHDL
• Verilog
• ABEL
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Finite State Machines (2)
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Finite State Machines (3)
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Finite State Machines (4)
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Finite State Machines (5)Rangkaian Sekuensial
FSM :
INIT
RDY
SEND
POLL
Rst
Strobe
Strobe
rdy_in
rdy_in
FSM:process(Rst, Clk)begin
if Rst’1’ thencurrent_state <= INIT;
elsif rising_edge(Clk) thencase current_state is
when INIT =>current_state <= RDY;
when RDY =>if strobe=’1’ then
current_state <= SEND;end if;
when SEND =>current_state <= POLL;
when POLL =>if rdy_in=’1’ then
current_state <= RDY;end if;
end case;end if;
end process;
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Contoh: 8421 BCD to Excess3 BCD Code
Converterx z
QX (inputs) Z (outputs)
t3 t2 t1 t0 t3 t2 t1 t0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
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State Graph dan Tabel untuk Code Converter
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Tabel Transision
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K-maps
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Implementasi
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Flip Flop (1)
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Flip Flop (2)
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Flip Flop (3)
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Flip Flop (4)
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Flip Flop (5)
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Flip Flop (6)
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Konversi/Desain Flip-Flop
1. Dibatasi dengan asumsi bahwa mekanisme
clock tidak berubah
2. Alat bantu
– Diagram state FF yang didesain
– Tabel transisi FF yang didesain
– Map Entry, seluruh kemungkinan syarat
pencabangan di-AND-kan dengan syarat input
yang diperlukan
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Contoh (1)
Jika diketahui tabel operasi dari suatu L-FF sbb :
Desain L-FF dari/menggunakan JK-FF
Qt
1
Qt+1L
1
0
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Contoh (2)
• Desainlah GM-FF dg menggunakan JK-FF jika diketahui Tabel operasi
dari GM-FF sbb
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Contoh (2)