08 mcu lecture2 lowpower...

Low-Power MCUsDr. Francesco Conti

[email protected]

Slide contributions adapted from STMicroelectronicsand from Dr. Michele Magno, others

Why Low Power Is so Important for MCUs?

• Longer battery life• Smaller products • Simpler power supplies• Less EMI simplifies PCB• Permanent battery• Reduced liability

Power as a Design Constraint

• Why worry about power?• Battery life in portable and mobile platforms• Power consumption in desktops, server farms

• Cooling costs, packaging costs, reliability, timing• Power density: 30 W/cm2 in Alpha 21364

(3x of typical hot plate)

Where does power go in CMOS?

leakshort2 VIfAVIfACVP ++= t

Dynamic power consumption

Power due to short-circuit current during transition

Power due to leakage current

Dynamic Power Consumption

fACV2A - Activity of gates How often on average do wires switch?

f – clock frequencyTrend: increasing ...

V – Supply voltage Trend: has been dropping with each successive fab

C – Total capacitance seen by the gate’s outputsFunction of wire lengths,transistor sizes, ...

Reducing Dynamic Power1) Reducing V has quadratic effect; Limits?2) Lower C - shrink structures, shorten wires3) Reduce switching activity - Turn off unused parts or

use design techniques to minimize number of transitions

Short-circuit Power Consumption

Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting

Vin Vout

CL

Ishort

fAVIshortt

Reducing Short-circuit1) Lower the supply voltage V2) Slope engineering – match the rise/fall time of the input and output signals

Leakage Power

leakVI

Sub-threshold current grows exponentially with increases in temperature and decreases in Vt

Sub-threshold current

Achieving low-power• Reducing dynamic power∝ ACV2f:

• capacitance is a physical property, can be tweaked only whendesigning the chip

• act on the frequency f: • 1. clock gating: turn down the clocks driving currently idle logic• 2. clock scaling: reduce the frequency of peripherals requiring lower speed

• act on the activity A:• do not perform useless activities J race to idle state + perform duty cycling

• act on the operating voltage V:• 3. voltage scaling: very powerful, typically done together with frequency scaling

(DVFS – dynamic voltage/frequency scaling)• pitfall: must be done in a well designed way, or logic will stop working!

• Reducing static power (mostly leakage) ∝ VIleak• leakage current depends on physical and electrical properties, not

always tweakable at runtime• exceptions exist, e.g. body biasing, but not often exposed to programmer!

• act on operating voltage V:• same as above

• Application phases:• OFF – power is not applied to MCU• STARTUP INITIALIZATION – MCU performs configuration (peripherals,

clocks, …)• Tperiod

• INACTIVE – MCU is in low power mode to reduce power consumption• ACTIVE – MCU is in normal mode and performs tasks

2

OFF STARTUP INITIALIZATION

IRQ

IDD

IRQ

TASKS

Process ACTIVE

INACTIVE

Tperiod Tperiod

TASKS

ACTIVE

INACTIVE INACTIVE

Time

Achieving low power: application phases

Achieving low power: duty cycling

9

• The relationship and balance between the performance and execution time needs to be carefully analyzed to find a best compromise which leads to lowest energy consumption.

T

T = Time of PeriodP = Activation TimeDuty Cycling = (Activity Period/Time of Period) * 100%

P

MCU A MCU B

Energy (10% activein 1s interval) 10% Duty Cycling

200.9 uJ 210.5 uJ (+4,8%)

Energy (0.1% active in 1s interval)0.1% Duty Cycling

3 uJ 2.7 uJ (-10%)

MCU Shootout

10

MCU A MCU B

Active mode 2 mA 2.1 mA (+5%)

Low power mode 1 uA 0.6 uA (-40%)

• Current or energy? And what about power profile?

MCU Shootout - 2

• What if the MCUs have different architectures and CoreMark scores? • The time spent in active mode will not be equal.

• Less time spent in active è lower total energy consumed. • We can do so by using optimization techniques.

11

MCU A(16-bit) MCU B(32-bit)

Active mode time 10 % 7 %

Energy (in 1s) 200.9 uJ 147.6 uJ (-26.6 %)

STM32L1: an ultra low-power MCU

System architecture and memory overview RM0038

42/911 DocID15965 Rev 15

2 System architecture and memory overview

2.1 System architectureThe main system consists of a 32-bit multilayer AHB bus matrix that interconnects:• Up to five masters:

– Cortex®-M3 I-bus, D-bus and S-bus– DMA1 and DMA2

• Up to five slaves:– Internal Flash memory ICode– Internal Flash memory DCode– Internal SRAM– AHB to APBx (APB1 or APB2), which connect all the APB peripherals– Flexible Static Memory Controller

These are interconnected using the multilayer AHB bus architecture shown in Figure 1:

Figure 1. System architecture (Cat.1 and Cat.2 devices)

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Cortex-M3core

The STM32L1 is a relatively simple microcontroller series from ST targetingultra-low power computing (e.g. for wireless sensor nodes)

To achieve low power, even the «simple» STM32L1 has a very sophisticated and fine-grain architecture for clocking (frequencyscaling) and power distribution (voltagescaling)

• The 5 clocks sources, the PLL and the CSS offers the maximum flexibility and safety for any battery-operated application.

HSIInternal @ 16 MHz

MSIInternal 64kHz to 4MHz

HSEExternal 1-24MHz

LSEExternal @ 32kHz

High Speed Internal clock @ 16MHz.Multiplied by 2 using the PLL to reach the 32MHZ. User trimable with +/-0.5% accuracy

Multi-Speed Internal clock Very low frequency to address ultra-low-consumption budget application.

Low Speed Internal clock (also called Security clock).Used for Watchdog security and RTC.

High Speed External clock: external quartz could be 1 to 24MHz.USB 48MHz clk will require only a 16MHz crystal(cheaper), x3 using PLL.You can still reached ultra-low-consumption value below 16MHz (down to 65KHz)In case of HSE failure Clock Security System (CSS) will switch to HSI.

Low Speed External clock (32.768 KHz)Mainly used for precise RTC.Could be used to calibrate HSI & MSI.LSE could also be calibrate by external clock (eg: 50Hz of Home power supply)

LSIInternal @ 38kHz

CSS

Clock sources in the STM32L1

From clock sources to system clocks - 1



LSIInternal @ 38kHz

HSEExternal 1-24MHz

LSEExternal @ 32kHz

System clock (SYSCLK):primary clock of the MCU, most clocks usedby digital components derive from this




LSIInternal @ 38kHz

HSEExternal 1-24MHz

LSEExternal @ 32kHz

High Performance clock (HCLK):used by the Cortex-M3 core + memory and main interconnect




LSIInternal @ 38kHz

HSEExternal 1-24MHz

LSEExternal @ 32kHz

Peripheral clock x (PCLKx):used by peripherals connected to APBx bus




LSIInternal @ 38kHz

HSEExternal 1-24MHz

LSEExternal @ 32kHz

Clock generation and source selectionClock prescaling




LSIInternal @ 38kHz

HSEExternal 1-24MHz

LSEExternal @ 32kHz

ADC clock (ADCCLK):used by analog-to-digital converter




LSIInternal @ 38kHz

HSEExternal 1-24MHz

LSEExternal @ 32kHz

Timer clocks (TIMxCLK):used by timers to count time




LSIInternal @ 38kHz

HSEExternal 1-24MHz

LSEExternal @ 32kHz

Real-time clock (RTCCLK):always-on, very slow clock used to savedata fundamental for device wake-up

Clock domains in the STM32L1


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Cortex-M3core

HCLK

PCLK1

PCLK2

Voltage domains in the STM32L1

DocID15965 Rev 15 99/911

RM0038 Power control (PWR)

126

Figure 8. Power supply overview

1. VDDA and VSSA must be connected to VDD and VSS, respectively. 2. When available (depending on packages), VREF- must be tied to VSSA.3. Depending on the operating power supply range used, some peripherals may be used with limited

functionalities or performance. For more details, please refer to section "General operating conditions" in STM32L1xxxx datasheets.

5.1.1 Independent A/D and DAC converter supply and reference voltageTo improve conversion accuracy, the ADC and the DAC have an independent power supply that can be filtered separately, and shielded from noise on the PCB.• The ADC voltage supply input is available on a separate VDDA pin• An isolated supply ground connection is provided on the VSSA pin

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VDD (1.65V-3.3V)digital devices, provided from ext,used directly for RTC, wakeup, standby


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VDD (1.65V-3.6V)digital devices, provided from ext,used directly for RTC, wakeup, standby

VCORE (1.2V-1.8V)core memories + peripherals, generatedby voltage regulatorfrom VDD

25

Typi

cal c

urre

nt

249µA/MHzFull speed (32MHz)

183µA/MHzMSI clock (4.2MHz)

900nA(300nA)

1.2µA(500nA)

9 µA4.4 µA

Dynamic RUNFrom Flash

LPRUN@ 32KHz

LPSLEEP+ 1 timer @ 32KHz

STOP w/ RTC(w/o RTC)

STANDBY w/RTC(w/o RTC)

Wake up time• Stop to Run: 8μs• Standby to run: 50μs

1/ Dhrystone power consumption value executed from 128kB Flash with VDD=3V , 25C2/ Stop and standby with RTC given with VDD=1.8V3/ Stop and standby without RTC given with VDD=3V

Power modes of STM32L1

STM32L1 operating modes: RUN• normal operating mode• all devices active• core clocked by HCLK, up to 32 MHz


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STM32L1 operating modes: RUN - 2• power consumption can be reduced with fine-grain peripheral clock gating• power also reduced with frequency scaling


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STM32L1 operating modes: RUN - 3

Curr.[uA/MHz] range 1 range 2 range 3

LP Sleep /

RunCondition: 32 MHz 16 MHz 4 MHz 65 kHzGPIOA 7 6 5 6GPIOB 7 6 5 6CRC 0.5 0.5 0.5 1DMA1 18 15 13 18FSMC 15 12 10 12

SYSCFG & RI 3 2 2 3

TIM9 8 7 6 7TIM10 6 5 5 5TIM2 13 11 9 11TIM7 4 4 4 4LCD 4 3 3 4WWDG 3 2.5 2.5 3USB 15 7 7 7PWR 3 3 3 3DAC 6 5 4.5 5………..ALL 279 221 219 215

• Clocking the peripheral increases consumption when the Bus clock is running…

• So the clock driving each peripheral can be gated

• Default mode at reset is gated, minimizing consumption

• Peripheral can be gated automatically when entering Sleep mode

• Be aware of non-synchronous consumption though!

• (GPIO sink/source, etc)

Further power savings in RUN mode:

• Run on MSI CLK: 183 µA/MHz (Active mode)

• Run full speed (32 MHz): 249 µA/MHz with 2.61 CoreMark/MHz

Value given for VDD=3V @ 25°C – Execution from Flash2/ Run from Flash with int. osc. at min values

Maximum

fCPU (MHz)

VCORE

32

1.8 V

230 µA/ DMIPS

16

1.5 V

200 µA/ DMIPS

4

1.2 V

171 µA/ DMIPS

Dynamic voltage/frequency scaling

Power

consumption

STM32L1 operating modes: RUN - 4

VDD 2 – 3.6V1.65 – 3.6 V

STM32L1 operating modes: LPRUN• low power active mode• some peripherals are disabled (retaining state), voltage regulator in LP mode• core clocked by HCLK, up to 4 MHz (must use MSI source)


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STM32L1 operating modes: LPRUN - 2

• LP RUN Mode: Core running, peripherals kept running• System Clock is set to multispeed internal (MSI) RC oscillator (131kHz max) • Execution from SRAM or Flash memory• Internal regulator is in low power mode to minimize the regulator's operating

current• FLASH can be in Power Down mode (when executing from RAM)• VREFINT can be OFF• The system clock frequency and enabled peripherals are both limited.

• Overall consumption of digital IP limited to 200µA• When flash is in Power Down Mode, interrupts must be

mapped to RAM

31

STM32L1 operating modes: SLEEP• core is stopped and gated, waiting for a wakeup event or interrupt• entered with wait-for-event (WFE) or wait-for-interrupt (WFI) instruction or at

the exit from an interrupt service routine (if configured to do so)


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STM32L1 operating modes: SLEEP - 2

• SLEEP Mode: Core stopped, peripherals kept running• Entered from by executing special instructions

• WFI (Wait For Interrupt)• Exit: Any peripheral interrupt

• WFE (Wait For Event)• An event can be an interrupt enabled in the peripheral control register

but NOT in the NVIC OR an EXTI line configured in event mode• Exit: as soon as the event occurs è No time wasted in interrupt

entry/exit

• Two mechanisms to enter this mode • Sleep Now: Enter SLEEP mode as soon as WFI or WFE is executed• Sleep on Exit: Enter as soon as it exits the lowest priority ISR

• The stack is not popped before entering the sleep, it will not be pushed when the next interrupt occurs, saving running time

33

STM32L1 operating modes: LPSLEEP• core is stopped and gated, waiting for a wakeup event or interrupt• some peripherals are disabled (retaining state), voltage regulator in LP mode• Flash can be in power-down


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STM32L1 operating modes: LPSLEEP - 2

• LP sleep Mode: core stopped, peripherals kept running• Entered by executing special instructions from LPRUN mode

• WFI (Wait For Interrupt)• WFE (Wait For Event)

• Internal regulator is in low power mode to minimize current draw• FLASH can be in Power Down mode• VREFINT can be OFF

35

STM32L1 operating modes: STOP• all VCORE clocks are gated• voltage regulator in LP mode, SRAM and registers retain state


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STM32L1 operating modes: STOP - 2• STOP Mode: all peripheral clocks, PLL, MSI, HSI and HSE are disabled, SRAM and

register contents are preserved. • If the RTC, LCD and IWDG are running they are not stopped• Voltage Regulator can be put in Low Power mode• Wake-up sources:

• WFI was used for entry: any EXTI Line configured in Interrupt mode• WFE was used for entry: any EXTI Line configured in event mode• EXTI sources can be: one of the 16 GPIO lines, PVD, RTC sources,

Comparators, USB wake-upè After resuming from STOP, the clock config returns to its reset

state (MSI used as system clock)

Wake-up time from Stop mode on MSI RC at 4MHz STM32L15x typ

Regulator in run or in low power mode mode (VREFINT ON) 7.9 µs

Regulator in run or in low power mode mode (VREFINT OFF with Fast Wakeup) 7.9µs

37

• Wake Up Time from STOP mode is defined here as “from IT event to the interrupt vector fetch”

• Wake Up time contributors:

• ANALOG delay :

• MSI start up : 3.5us • REGULATOR switch from LP to MR mode : 3.5us (voltage range has an impact on the

startup of the regulator / temperature also has an impact è 6.5µs MAX)• EEPROM start up : 3us MAX (after the ready of the regulator)

• DIGITAL delay• System synchronization: 10 clock cycles

• Interrupt vector fetch / context restoring : 20 clock cycles• Wake Up clock :

• Wakeup sequence is done on MSI and its frequency is the one selected before entering STOP mode. (max wakeup freq is 4.2MHz)

• Wake Up time in datasheet :• 8.2µs typ / 9.3µs max (range 1 and range 2)

STM32L1 operating modes: STOP - 3

WakeUp Event

MSI PD

MSI READY

MSI StartUp (3.5us MAX)

REG PD

READY

LP mode MR mode

EE PD

EE wakeup (3us MAX)

EE READY

MSI Clock

MSI 4MHZ

REGULATOR

EEPROM

“Analog” WakeUp

WakeUp Time

Interrupt vector fetch

1st ISR word fetch startInterrupt vector fetch

IddQ mode Operating mode

CPU CLK

20 cycles

6.5µs 2µs

7 cycles3 cycles 20 cyclesAnalog delay

REG StartUp (3.5us MAX)

STM32L1 operating modes: STOP - 4

STM32L1 operating modes: STANDBY• all VCORE clocks are gated, HSI/MSI/HSE oscillators off• waiting for external wakeup or RTC wakeup/alarm/tamper event (auto-wakeup)• voltage regulator is off, only RTC register contents are retained


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• STANDBY Mode: VCORE domain is powered off and VREFINT can be OFF. • SRAM and register contents are lost except registers in the STANDBY circuitry• RTC and IWDG are kept running in STANDBY (if enabled)• In STANDBY mode all IO pins are high impedance except

• Reset pad (still available)• RTC_AF1 pin, if configured• WKUP1, WKUP2 and WKUP3 pins if enabled

• Wake-up sources:• WKUP1, WKUP2, WKUP3 pins rising edge• RTC alarm A, RTC alarm B, RTC Wakeup, Tamper event, TimeStamp• External reset in NRST pin• IWDG resetè After wake-up from STANDBY mode, program execution will restart in the same

way as after a RESET.

Wake-up time from STANDBY mode on MSI RC at 2MHz STM32L15x typ

STANDBY with VREFINT ON 57.2 µs

STANDBY with VREFINT OFF 2.4 ms41

STM32L1 operating modes: STANDBY - 2

Standby Circuitry

32kHz OSC(LSE)

RTC + 128 Bytes DataRTC_AF1 Wakeup

Pin 2

RCC CSRreg

WakeupLogic

IWDG

Wakeup Pin 1

Wakeup Pin 3WakeupPin 2

LSI

• Standby Circuitry contains• Low power calendar RTC (Alarm, periodic

wakeup)

• 80 Bytes Data RTC registers

• Separate 32KHz Osc (LSE) for RTC

• RCC CSR register: Clock + LSE config

-> Reset only by RTC domain RESET

• Wakeup sources• 3 wakeup pins (1 for MD)

• RTC Alarm A or AlarmB

• RTC Wakeup Timer

• RTC Tamper / Timestamps Events

• RTC Alternate functions• Tamper detection: resets all RTC user backup

registers

• RTC Alarm Outputs: Alarms A/B, Wakeup on AF1 pin

• RTC Clock calibration Output

STM32L1 operating modes: STANDBY - 3

Exercise

Mode MCU A (1.8V to 3V)

MCU B(1.5V to 3V)

ACTIVE 2 mA @ 8Mhz 3 mA @ 16Mhz

LP 0.6 uA 1 uA

Assume:1. MCU A and B as in table2. A battery of 100 mAh @ 3.7V3. A task that has to be repeated

forever, taking 1s @ 16MHz (2s @ 8MHz)

• Evaluate the minimum duty cyclingthat can achieve two weeks of operation for the two MCUs

• How much energy is spent in the active and low power mode for the two MCUs?

• Consider a duty cycle of 1/1000. Which MCU lasts longer?

08 mcu lecture2 lowpower...

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