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SINGLE CHIP UHF RFID READER DIGITAL BASEBAND DESIGN

BOYANG ZHANG, GUANGJUN WEN" LIU YANG, BOWEN ZHENG

I Center for FIC and System Tecnology, School of Communication and Information Engineerng, Universit of Electronic Science and Tecnology of China, Chengdu, 611731, Chna

E-MIL: [email protected]@[email protected]@gmail.com

Abstract:The most important blocks in the digital part of a RFD

reader are the MCU which controls all the system work in anecient way and the modulator which is used to accomplishthe digital signal processing. As now most commercial RFDreaders are discrete component design and researching onimplementation of single chip RFID reader is few, this paperpoint out a design that concentrates on the research of singlechip RFID reader design in digital baseband part. In the newdesign, we make use of the open source IP core Leon3 which isdeveloped by the Aeroex Gaisler to control the digitalmodulator to nish the signal processing including CRC check,code and decode ltering and so on And all theimplementations are described in VHDL and simulated byModelsim. We use the Virtex-6 FPGA to prove that it canwork properly at the same time.

Keords:

RFD- Reader; Leon3; Digital- Baseband; SOC;FPGA

1. Introduction

Nowadays, the UHF FID readers and tags are rapidlydeveloped in tecnology and the amount of the product'ssale is upward in high speed. In tes of tecnology, lower power, longer working distance, higher speed to read a tag, more stable and lower cost are the directions of the researchin FD reader.

Most FID readers' baseband signal processing chip isdiscrete component design d employs the existing MCU(microcontroller unit) which is developed by othercompanies. The ROOO FD reader chip developed byImpinj is a tpical example []. Users only need to accessan AM7, and write soware code to accomplish thenction call to ish the protocol between readers and tags.This requires uses to make a purchase and pay the high costof patent, resulting in high prices FD reader. Up to now, there is only one signal chip FD reader which isdeveloped by Phychips. So the designing of basebandsignal processor based on the open source IP core Leon3

978-1-4673-4685-6/12/$31.00 ©2012 IEEE 203

and eventually accomplish the baseband signal processor which meet the requirements of the FID reader can reduce the cost of the product effectively, and as domestic researching on this aspect is few, therefore, aer thecompletion of the subject, this project will be of great

prospects and signicace.

2. Architecture of RFID reader

In the design, all the reader's working mode and stateis controlled by the programmed MCU and the FD readersupports both the IS18000-6B and EPC Class-Generation2 UHF FID protocol. The whole reader chipstructure is shown in Fig.. In Fig., our work will

concentrate on the design which is put in the red part. Herein order to make reading data om the Leon3 inteal AMBA bus ad sending data to slaves on the bus moreconvenience, in our design we add a AMBA AHB interfaceand a dual-port M to buffer the data either come om the AMBA bus and the modulator[2]. In this way, when the modulator wat to commicate with the MCU, there is no need to make a complex interface to lll the protocol of AMBA, it will decrease the difcult of the system design.

Fig. FD reader chip architecture

Then the digital part can be conected to the F transceiver to ish the whole reader. ther parts of thedesign in Fig. are offered by the Leon3 open source IP

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core, they are congurable and we need to x the hardwarecode to tting our design and make program in it toaccomplish the FD protocol.

2.1. Baseband modem architecture

The baseband modem is consist of the transmit partand the receive part. nd their working state is controlled by the control register which is written by MCU trough the AMBA interface. The digital baseband architecture isshown in Fig.2, the most right part is AMBA AHB bus,aer that there is a interface to lll the protocol of

AHB. The dual-port M is a bridge, in the right side the

AM's nterface is AB, and in the le side, the M isact as a normal AM. So when we design other part of thesystem, it just likes conecting to a simple M but not the

AMBA.--_.._---_.._---_ .._--_.._---_.._-

0: • -----4=A -----I, ______:._.______ __ .-

Fig.2 Digital baseband architecture

2.2. Transmit path

First of all, we need a state machine to conl the transmit path when transmitting the data and what's the time to stop, so Fig.3 shows the state transition n transmit

path. When the data path is enabled, the parallel data whichis ready to send is transferred to series and then being coded by FMO or Manchester, at the same time the code is added 5or 16 bit CRC check code. Then the data will be shaped by the pulse shaping sub-model, in order to make the powerconsumption lower and tting multi-data-rate, we use thedate which is already gure out and saved in registerinstead of a raised cosne lter to accomplish the work [].If the system is set to send the data in SSB, the hilber lter will be enabled and generate the quadrature data [3].Finally the data is processed by the DAC and ansmitted to the tags.

Fig.3 Transmit state transition

2.3. Receive path

Fig.4 Receive state transition

Just like the nsmit path, there is also need a state machine to control the receive path, Fig shows the state transition in receive path. hen the receive path is enabledand begin to receive data om tag, the rst thing to do is to make the data rate slower to make signal process easer adconsumption lower. So in the beginng is a two stagedecimation lter [4]. nd followed by the chanel lter which is consist of a FIR and an R [5]. Then the data will be sent to both the RSSI and phase recover sub-model.

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The RSSI use the wideband signal received om the analog part directly and the narrowband signal received om theoutput of chanel lter to make a signal power feedback to the analog par [6]. The nction of hase recovery is toimlementation bit-synconization. Here we useintersymbol syncronization but not earlylate gatesyncronization because u to now the signal is not thesuare wave yet [7]. Then the signal will be samled anddecoded, and nally submitted to MCU to handling.

3 Simulation and veried by FPGA

e use the modelsim to do the simulation and ML605

FPGA development kit to prove our design is properly. In this case we just test the communication with tag in baseband, and trough the test we can veri that the IPcore, AMBA interface, baseband modem and the state machine we programmed is working properly.

Fig. Transmit data path simulation result

Fig.5 shows the transmit path nction simulation result. It is made by modelsim ad in the test data is"0001-0010-0011-0100, in Fig.5 the result is accordance with the theoretical. e can see that in the receive register we can receive the data properly. In the receive path, wecan use a more convenience tool offered by AeroexGaisler to test if the register has already received the data

properly. nd our test result shows us that we have received

data successlly.Fig.6 is the FPGA Develoment board, we use ML605

as o veri latform. Fig.7 ad Fig.8 is the FPGAverication result for both the trasmit ath and receiveath. In Fig.7 we use PIE code and we can see clearly that the outut result is "0001-0010-0011-0100. As on thechiscoe we can only simle 1024 point, so Fig.8 justshow part of the receive data.

4 Conclusions

e have implemented the digital part of the singlechip FD reader design, the physical layer is described in

VHDL and has been simulated by modelsim, then weveried if on the FPGA development platform to prove itcan work properly and efciently to accomplishment thecommunication with tag under the IS18000-6B or EPCC1 G1 protocol. Now we almost nish the ont-end design, then our rther work will do more test and nish thedesign work in the back-end part.

Fig.6 FPGA development platform

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Fig.7 Transmit path FPGA verication result

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Fig.8 Receive path FPGA verication result

Acknowledgments

i

This paper is supported by Professor en Guanun,all the colleagues in our lab, and Universit of ElectronicScience and Tecnology of China.

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References

[1] Indy R000 Reader Chip Datasheet, Impinj, 2010.[2] nurag Srivastava, "Performance Comparison of

AMBA Bus-Based System-n-Chip CommunicationProtocol, 2011 Inteational Conference onCommunication Systems and Netork Tecnologies(CSNT) pp. 449 454, une.20 11.

[3] Ewa Hermanowicz, Agnieszka Parzel, "Farrwstrcte for complex digital Hilbert lter of lowcomplexit, Signal Processing Algoritms, rchitectures, rrngements and Applications, 2007, pp. 91-96, Sept. 2007.

[4] Digital decimation lter design and simulation fordelta-sigma ADC with high performance, ASICN2007 : 2007 7th Inteational Conference on ASIC proceeding: ctober 25-29, 2007, Guilin, Chna, pp.922-925, ct. 2007.

[5] Yihao Chen, Research on the Critical Modules of theDigital Baseband of FD Reader Compatible withEPC CG2 Protocol, Publisher, East China NormalUniversit, 2008.

[6] Vinita Daiya, emimah Ebenezer, S.A.V. Sata Mt,Baldev Raj, "Experimental nalysis of RSSI forDistance and Position Estimation, 2011 InteationalConference on Recent Trends in Infoation

Tecology (CRTT), pp. 1093-1098, June.2011.[7] L.E.FKS, "Carier and Bit Synconization in

Data Communication--A Tutorial Review, IEEETransactions on Communications, pp. 1107-1121, Aug1980.

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